diff options
| author | Christine Gharzuzi <chrisg@marvell.com> | 2017-06-20 22:39:25 +0300 |
|---|---|---|
| committer | Kostya Porotchkin <kostap@marvell.com> | 2017-07-16 18:05:09 +0300 |
| commit | dfcdadcbcd9e640d95413db9ca67c4d3036ed51e (patch) | |
| tree | a5b2ee7a2e5879a5b6516751373d2d452cfc5a3c /plat/marvell/a8k/common/plat_ble_setup.c | |
| parent | 0e478a6a1980b28bd7b1d2b057ee6fae1f6409f5 (diff) | |
atf: ARO: Introduce Adaptive Ring Oscillator
is a clock generator, which is used in AP806 as a source
clock for the CPU clusters.
In AP806 the ARO is not the major clock, and this document discuss
the way to switch from PLL mode (which is the default mode) to ARO mode.
The motivation for ARO usage is improving the Yield of the device
at 2Ghz and improving the power consumption at that work point.
In general – ARO allow lower Vmin for running in this premium work point
which serves both cause (yield and power).
Change-Id: I76a391a29cd98abedcd003f52d37a60459ee8b80
Signed-off-by: Christine Gharzuzi <chrisg@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/40640
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Hanna Hawa <hannah@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Diffstat (limited to 'plat/marvell/a8k/common/plat_ble_setup.c')
| -rw-r--r-- | plat/marvell/a8k/common/plat_ble_setup.c | 23 |
1 files changed, 3 insertions, 20 deletions
diff --git a/plat/marvell/a8k/common/plat_ble_setup.c b/plat/marvell/a8k/common/plat_ble_setup.c index 8815051a..7203a11d 100644 --- a/plat/marvell/a8k/common/plat_ble_setup.c +++ b/plat/marvell/a8k/common/plat_ble_setup.c @@ -39,6 +39,7 @@ #include <sys_info.h> #include <dram_if.h> #include <ccu.h> +#include <aro.h> #include <rfu.h> #include <apn806_setup.h> #include <cp110_setup.h> @@ -143,26 +144,6 @@ #define EFUSE_SVC_REVISION_ID_0 0x8 #define EFUSE_SVC_BIN_PREMIUM 0x1 -enum cpu_clock_freq_mode { - CPU_2000_DDR_1200_RCLK_1200 = 0x0, - CPU_2000_DDR_1050_RCLK_1050 = 0x1, - CPU_1600_DDR_800_RCLK_800 = 0x4, - CPU_1800_DDR_1200_RCLK_1200 = 0x6, - CPU_1800_DDR_1050_RCLK_1050 = 0x7, - CPU_1600_DDR_900_RCLK_900 = 0x0B, - CPU_1600_DDR_1050_RCLK_1050 = 0x0D, - CPU_1600_DDR_900_RCLK_900_2 = 0x0E, - CPU_1000_DDR_650_RCLK_650 = 0x13, - CPU_1300_DDR_800_RCLK_800 = 0x14, - CPU_1300_DDR_650_RCLK_650 = 0x17, - CPU_1200_DDR_800_RCLK_800 = 0x19, - CPU_1400_DDR_800_RCLK_800 = 0x1a, - CPU_600_DDR_800_RCLK_800 = 0x1B, - CPU_800_DDR_800_RCLK_800 = 0x1C, - CPU_1000_DDR_800_RCLK_800 = 0x1D, - CPU_DDR_RCLK_INVALID -}; - /* Notify bootloader on DRAM setup */ void pass_dram_sys_info(struct dram_config *cfg) { @@ -504,6 +485,8 @@ int ble_plat_setup(int *skip) /* Setup AVS */ ble_plat_svc_config(); + init_aro(); + /* Get dram data from platform */ cfg = (struct dram_config *)plat_get_dram_data(); |