io-decode: a3700: update the max dram decode windows number

- Not all configurable decode windows could be used for dram, some
  units have to reserve one decode window for other unit they have
  to communicate with; for example, DMA engineer has 3 configurable
  windows, but only two could be for dram while the last one has to
  be for pcie, so for DMA, its max dram decode windows number is 2;
- Only io dram decode windows needs to be reconfigured for different
  dram size boards(512MB, 2GB and 4GB), this patch renames the field
  member max_win to max_dram_win and updates the old io max decode
  windows number to max dram decode windows number.

Change-Id: I61ed0c936baa5b2f73c5e7d0c41dfc81c7033b90
Signed-off-by: Ken Ma <make@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/38956
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Hua Jing <jinghua@marvell.com>

3 files changed, 18 insertions, 11 deletions

diff --git a/plat/marvell/a3700/common/include/io_addr_dec.h b/plat/marvell/a3700/common/include/io_addr_dec.h
index a24192c3..d998c8bf 100644
--- a/plat/marvell/a3700/common/include/io_addr_dec.h
+++ b/plat/marvell/a3700/common/include/io_addr_dec.h
@@ -40,10 +40,17 @@
 /* Target number for dram in cpu decoder windows. */
 #define DRAM_CPU_DEC_TARGET_NUM	0
 
+/*
+* Not all configurable decode windows could be used for dram, some units have
+* to reserve one decode window for other unit they have to communicate with;
+* for example, DMA engineer has 3 configurable windows, but only two could be
+* for dram while the last one has to be for pcie, so for DMA, its max_dram_win
+* is 2.
+*/
 struct dec_win_config {
 	uint32_t dec_reg_base; /* IO address decoder register base address */
 	uint32_t win_attr;     /* IO address decoder windows attributes */
-	uint32_t max_win;      /* How many decoder windows that this unit has */
+	uint32_t max_dram_win; /* How many configurable dram decoder windows that this unit has; */
 	uint32_t max_remap;    /* The decoder windows number including remapping that this unit has */
 	uint32_t win_offset;   /* The offset between continuous decode windows within the same unit, typically 0x10 */
 };
diff --git a/plat/marvell/a3700/common/io_addr_dec.c b/plat/marvell/a3700/common/io_addr_dec.c
index 41c5c2b8..5e2b95ca 100644
--- a/plat/marvell/a3700/common/io_addr_dec.c
+++ b/plat/marvell/a3700/common/io_addr_dec.c
@@ -98,13 +98,13 @@ static int set_io_addr_dec(struct dram_win_map *win_map, struct dec_win_config *
 	int id;
 
 	/* disable all windows first */
-	for (id = 0; id < dec_win->max_win; id++)
+	for (id = 0; id < dec_win->max_dram_win; id++)
 		mmio_write_32(MVEBU_DEC_WIN_CTRL_REG(dec_win->dec_reg_base, id, dec_win->win_offset), 0);
 
 	/* configure IO decode windows for DRAM, inheritate DRAM size, base and target from CPU-DRAM
 	 * decode window, and others from hard coded IO decode window settings array.
 	 */
-	if (win_map->dram_win_num > dec_win->max_win) {
+	if (win_map->dram_win_num > dec_win->max_dram_win) {
 		/*
 		* If cpu dram windows number exceeds the io decode windows max number,
 		* then fill the first io decode window with base(0) and size(4GB).
@@ -172,8 +172,8 @@ int init_io_addr_dec(struct dram_win_map *dram_wins_map, struct dec_win_config *
 			return -1;
 		}
 		INFO("Set IO decode window successfully, base(0x%x)", io_dec_win->dec_reg_base);
-		INFO(" win_attr(%x) max_win(%d) max_remap(%d) win_offset(%d)\n",
-		     io_dec_win->win_attr, io_dec_win->max_win, io_dec_win->max_remap, io_dec_win->win_offset);
+		INFO(" win_attr(%x) max_dram_win(%d) max_remap(%d) win_offset(%d)\n",
+		     io_dec_win->win_attr, io_dec_win->max_dram_win, io_dec_win->max_remap, io_dec_win->win_offset);
 	}
 
 	return 0;
diff --git a/plat/marvell/a3700/common/marvell_plat_config.c b/plat/marvell/a3700/common/marvell_plat_config.c
index c399325c..963ed6db 100644
--- a/plat/marvell/a3700/common/marvell_plat_config.c
+++ b/plat/marvell/a3700/common/marvell_plat_config.c
@@ -36,16 +36,16 @@
 #include <io_addr_dec.h>
 
 struct dec_win_config io_dec_win_conf[] = {
-	/* dec_reg_base  win_attr  max_win  max_remap  win_offset */
-	{0xc000,         0x3d,     3,       0,        0x08}, /* USB */
-	{0xc100,         0x3d,     3,       0,        0x10}, /* USB3 */
-	{0xc200,         0x3d,     3,       0,        0x10}, /* DMA */
+	/* dec_reg_base  win_attr  max_dram_win  max_remap  win_offset */
+	{0xc000,         0x3d,     2,       0,        0x08}, /* USB */
+	{0xc100,         0x3d,     2,       0,        0x10}, /* USB3 */
+	{0xc200,         0x3d,     2,       0,        0x10}, /* DMA */
 	{0xc300,         0x3d,     2,       0,        0x10}, /* NETA0 */
 	{0xc400,         0x3d,     2,       0,        0x10}, /* NETA1 */
 	{0xc500,         0x3d,     2,       0,        0x10}, /* PCIe */
-	{0xc800,         0x3d,     3,       0,        0x10}, /* SATA */
+	{0xc800,         0x3d,     2,       0,        0x10}, /* SATA */
 	{0xca00,         0x3d,     2,       0,        0x08}, /* SD */
-	{0xcb00,         0x3d,     3,       0,        0x10}, /* eMMC */
+	{0xcb00,         0x3d,     2,       0,        0x10}, /* eMMC */
 };
 
 int marvell_get_io_dec_win_conf(struct dec_win_config **win, uint32_t *size)