diff options
| author | Hanna Hawa <hannah@marvell.com> | 2017-08-25 15:37:06 +0300 |
|---|---|---|
| committer | Kostya Porotchkin <kostap@marvell.com> | 2017-08-27 13:43:28 +0300 |
| commit | 706491128e2792853e704453554a5052d742d4fe (patch) | |
| tree | 96a866440a127e9f51202d650d1b02f69202e818 /plat | |
| parent | 4f605e21472aa212a760a03237c1e31243dd8c9a (diff) | |
fix: mvebu: pm: a8k: update cpu unreset defines
Change-Id: I3034e01025aad9d343194b9419b840e6d495068a
Signed-off-by: Hanna Hawa <hannah@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/43392
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Diffstat (limited to 'plat')
| -rw-r--r-- | plat/marvell/a8k/common/plat_pm.c | 9 |
1 files changed, 4 insertions, 5 deletions
diff --git a/plat/marvell/a8k/common/plat_pm.c b/plat/marvell/a8k/common/plat_pm.c index 9086bb02..5c6fa640 100644 --- a/plat/marvell/a8k/common/plat_pm.c +++ b/plat/marvell/a8k/common/plat_pm.c @@ -53,8 +53,8 @@ #define MVEBU_PRIVATE_UID_REG 0x30 #define MVEBU_RFU_GLOBL_SW_RST 0x84 -#define MVEBU_CCU_RVBAR(i) (MVEBU_REGS_BASE + 0x640 + (i * 4)) -#define MVEBU_CCU_CPU_UN_RESET (MVEBU_REGS_BASE + 0x650) +#define MVEBU_CCU_RVBAR(cpu) (MVEBU_REGS_BASE + 0x640 + (cpu * 4)) +#define MVEBU_CCU_CPU_UN_RESET(cpu) (MVEBU_REGS_BASE + 0x650 + (cpu * 4)) #define MPIDR_CPU_GET(mpidr) ((mpidr) & MPIDR_CPU_MASK) #define MPIDR_CLUSTER_GET(mpidr) MPIDR_AFFLVL1_VAL((mpidr)) @@ -313,11 +313,10 @@ int plat_marvell_cpu_on(u_register_t mpidr) mmio_write_32(MVEBU_REGS_BASE + MVEBU_PRIVATE_UID_REG, cluster + 0x4); /* Set the cpu start address to BL1 entry point (align to 0x10000) */ - mmio_write_32(MVEBU_CCU_RVBAR(0) + (cpu_id << 2), - PLAT_MARVELL_CPU_ENTRY_ADDR >> 16); + mmio_write_32(MVEBU_CCU_RVBAR(cpu_id), PLAT_MARVELL_CPU_ENTRY_ADDR >> 16); /* Get the cpu out of reset */ - mmio_write_32(MVEBU_CCU_CPU_UN_RESET + (cpu_id << 2), 0x10001); + mmio_write_32(MVEBU_CCU_CPU_UN_RESET(cpu_id), 0x10001); return 0; } |