ap810: update naming convention

get_ap_count		--> ap810_get_ap_count
get_connected_cp_per_ap --> ap810_get_cp_per_ap_cnt
get_static_cp_per_ap	--> ap810_get_cp_per_ap_static_cnt

Change-Id: Ia3f569ac7cc9dc414fdc7291cfbdc2ca11c1de51
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/50860
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Hanna Hawa <hannah@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>

7 files changed, 35 insertions, 35 deletions

diff --git a/plat/marvell/a8k-p/a8xxy/board/marvell_plat_config.c b/plat/marvell/a8k-p/a8xxy/board/marvell_plat_config.c
index a3205d0e..a20bb853 100644
--- a/plat/marvell/a8k-p/a8xxy/board/marvell_plat_config.c
+++ b/plat/marvell/a8k-p/a8xxy/board/marvell_plat_config.c
@@ -80,7 +80,7 @@ struct addr_map_win gwin_memory_map4_ap3[] = {
 
 int marvell_get_gwin_memory_map(int ap, struct addr_map_win **win, uint32_t *size)
 {
-	int ap_count = get_ap_count();
+	int ap_count = ap810_get_ap_count();
 
 	if (ap_count < 3) {
 		switch (ap) {
@@ -171,7 +171,7 @@ uint32_t marvell_get_ccu_gcr_target(int ap)
 
 int marvell_get_ccu_memory_map(int ap, struct addr_map_win **win, uint32_t *size)
 {
-	int ap_count = get_ap_count();
+	int ap_count = ap810_get_ap_count();
 
 	if (ap_count < 3) {
 		switch (ap) {
@@ -241,7 +241,7 @@ uint32_t marvell_get_io_win_gcr_target(int ap_index)
 
 int marvell_get_io_win_memory_map(int ap, struct addr_map_win **win, uint32_t *size)
 {
-	int ap_count = get_ap_count();
+	int ap_count = ap810_get_ap_count();
 
 	if (ap_count < 3) {
 		switch (ap) {
@@ -510,8 +510,8 @@ int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, uintpt
 {
 	int  ap, cp;
 
-	for (ap = 0; ap < get_ap_count(); ap++) {
-		for (cp = 0; cp < get_connected_cp_per_ap(ap); cp++) {
+	for (ap = 0; ap < ap810_get_ap_count(); ap++) {
+		for (cp = 0; cp < ap810_get_cp_per_ap_cnt(ap); cp++) {
 			if (MVEBU_CP_REGS_BASE(ap, cp) == base) {
 				*win = iob_map[ap][cp];
 				*size = iob_map_size[ap][cp];
@@ -554,8 +554,8 @@ int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, uintpt
 {
 	int  ap, cp;
 
-	for (ap = 0; ap < get_ap_count(); ap++) {
-		for (cp = 0; cp < get_connected_cp_per_ap(ap); cp++) {
+	for (ap = 0; ap < ap810_get_ap_count(); ap++) {
+		for (cp = 0; cp < ap810_get_cp_per_ap_cnt(ap); cp++) {
 			if (MVEBU_CP_REGS_BASE(ap, cp) == base) {
 				*win = amb_map[ap][cp];
 				*size = amb_map_size[ap][cp];
diff --git a/plat/marvell/a8k-p/common/mss/mss_bl2_setup.c b/plat/marvell/a8k-p/common/mss/mss_bl2_setup.c
index 9c6ad2b3..ee48639e 100644
--- a/plat/marvell/a8k-p/common/mss/mss_bl2_setup.c
+++ b/plat/marvell/a8k-p/common/mss/mss_bl2_setup.c
@@ -73,7 +73,7 @@ static void bl2_plat_mss_remap(void)
 	 * then MSS remap will remap the address to 0x81_0000_0000
 	 */
 	/* MSS remap for CP1 */
-	for (i = 0; i < get_ap_count(); i++) {
+	for (i = 0; i < ap810_get_ap_count(); i++) {
 		mmio_write_32(MSS_REMAP_WIN1_ALR(i), MSS_WIN_ALR_VAL);
 		mmio_write_32(MSS_REMAP_WIN1_AHR(i), MSS_WIN_AHR_VAL);
 		mmio_write_32(MSS_REMAP_WIN1_CR(i), MSS_WIN1_CR_ADDR_MASK |
@@ -122,12 +122,12 @@ uintptr_t bl2_plat_get_ap_mss_regs(int ap_idx)
 
 uint32_t bl2_plat_get_cp_count(int ap_idx)
 {
-	return get_connected_cp_per_ap(ap_idx);
+	return ap810_get_cp_per_ap_cnt(ap_idx);
 }
 
 uint32_t bl2_plat_get_ap_count(void)
 {
-	return get_ap_count();
+	return ap810_get_ap_count();
 }
 
 void bl2_plat_configure_mss_windows(uintptr_t mss_regs)
diff --git a/plat/marvell/a8k-p/common/plat_bl1_setup.c b/plat/marvell/a8k-p/common/plat_bl1_setup.c
index a9e4ffdc..4b1860ee 100644
--- a/plat/marvell/a8k-p/common/plat_bl1_setup.c
+++ b/plat/marvell/a8k-p/common/plat_bl1_setup.c
@@ -127,11 +127,11 @@ static void a8kp_mci_turn_off_links(uintptr_t mci_base)
 	int ap_id, cp_id, mci_id;
 
 	/* Go over the APs and turn off the link of MCIs */
-	for (ap_id = 0; ap_id < get_ap_count(); ap_id++) {
+	for (ap_id = 0; ap_id < ap810_get_ap_count(); ap_id++) {
 		ap810_win_route_open(ap_id, mci_base, MVEBU_MCI_REG_SIZE_REMAP, IO_0_TID);
 
 		/* Go over the MCIs  */
-		for (cp_id = 0; cp_id < get_static_cp_per_ap(ap_id); cp_id++) {
+		for (cp_id = 0; cp_id < ap810_get_cp_per_ap_static_cnt(ap_id); cp_id++) {
 			struct addr_map_win iowin_temp_win = {
 				.base_addr = mci_base,
 				.win_size = MVEBU_MCI_REG_SIZE_REMAP,
@@ -204,11 +204,11 @@ static int mci_wa_initialize(void)
 	a8kp_mci_mpp_reset(MPP_MCI_RELEASE_FROM_RESET);
 
 	/* 3rd stage - Re-init the MCI phy in AP side & in CP side */
-	for (ap_id = 0; ap_id < get_ap_count(); ap_id++) {
+	for (ap_id = 0; ap_id < ap810_get_ap_count(); ap_id++) {
 		ap810_win_route_open(ap_id, mci_base, MVEBU_MCI_REG_SIZE_REMAP, IO_0_TID);
 
 		/* Go over the MCIs in every APx */
-		for (cp_id = 0; cp_id < get_static_cp_per_ap(ap_id); cp_id++) {
+		for (cp_id = 0; cp_id < ap810_get_cp_per_ap_static_cnt(ap_id); cp_id++) {
 			uint32_t reg;
 			struct addr_map_win iowin_temp_win = {
 				.base_addr = mci_base,
@@ -294,11 +294,11 @@ static int a8kp_mci_configure_threshold(void)
 	debug_enter();
 
 	/* Run MCI WA for performance improvements */
-	for (ap_id = 0; ap_id < get_ap_count(); ap_id++) {
+	for (ap_id = 0; ap_id < ap810_get_ap_count(); ap_id++) {
 		ap810_win_route_open(ap_id, mci_base, MVEBU_MCI_REG_SIZE_REMAP, IO_0_TID);
 
 		/* Go over the MCIs in every APx */
-		for (cp_id = 0; cp_id < get_connected_cp_per_ap(ap_id); cp_id++) {
+		for (cp_id = 0; cp_id < ap810_get_cp_per_ap_cnt(ap_id); cp_id++) {
 			struct addr_map_win iowin_temp_win = {
 				.base_addr = mci_base,
 				.win_size = MVEBU_MCI_REG_SIZE_REMAP,
@@ -350,11 +350,11 @@ static void update_cp110_default_win(void)
 	/* Go over the APs and update every CP with
 	 * the new configuration address
 	 */
-	for (ap_id = 0; ap_id < get_ap_count(); ap_id++) {
+	for (ap_id = 0; ap_id < ap810_get_ap_count(); ap_id++) {
 		ap810_win_route_open(ap_id, cp110_temp_base, MVEBU_CP_DEFAULT_BASE_SIZE, IO_0_TID);
 
 		/* Go over the connected CPx in the APx */
-		for (cp_id = 0; cp_id < get_connected_cp_per_ap(ap_id); cp_id++) {
+		for (cp_id = 0; cp_id < ap810_get_cp_per_ap_cnt(ap_id); cp_id++) {
 			struct addr_map_win iowin_temp_win = {
 				.base_addr = cp110_temp_base,
 				.win_size = MVEBU_CP_DEFAULT_BASE_SIZE,
@@ -388,7 +388,7 @@ static void ap810_addr_decode_init(void)
 
 	debug_enter();
 
-	for (ap_id = 0; ap_id < get_ap_count(); ap_id++) {
+	for (ap_id = 0; ap_id < ap810_get_ap_count(); ap_id++) {
 		/* configure IO-WIN windows */
 		init_io_win(ap_id);
 		/* configure GWIN windows */
diff --git a/plat/marvell/a8k-p/common/plat_bl31_setup.c b/plat/marvell/a8k-p/common/plat_bl31_setup.c
index 93805e9d..aa3be813 100644
--- a/plat/marvell/a8k-p/common/plat_bl31_setup.c
+++ b/plat/marvell/a8k-p/common/plat_bl31_setup.c
@@ -74,8 +74,8 @@ static void cp110_die_init(void)
 {
 	int ap_id, cp_id;
 
-	for (ap_id = 0; ap_id < get_ap_count(); ap_id++)
-		for (cp_id = 0; cp_id < get_connected_cp_per_ap(ap_id); cp_id++)
+	for (ap_id = 0; ap_id < ap810_get_ap_count(); ap_id++)
+		for (cp_id = 0; cp_id < ap810_get_cp_per_ap_cnt(ap_id); cp_id++)
 			cp110_init(MVEBU_CP_REGS_BASE(ap_id, cp_id));
 }
 
@@ -111,7 +111,7 @@ static void ap810_dvm_affinity(int ap_id)
 		mmio_write_32(CCU_HTC_GACR(ap_id, i), AP810_MAX_AP_MASK);
 
 	mmio_write_32(CCU_HTC_GASET(ap_id),
-			AP810_MAX_AP_MASK >> (AP810_MAX_AP_NUM - get_ap_count()));
+			AP810_MAX_AP_MASK >> (AP810_MAX_AP_NUM - ap810_get_ap_count()));
 
 	debug_exit();
 }
@@ -264,7 +264,7 @@ static void ap810_setup_events(int ap_id)
 	 */
 	switch (ap_id) {
 	case 0:
-		if (get_ap_count() == 2) {
+		if (ap810_get_ap_count() == 2) {
 			/* Port 2 - unmask local GEvent */
 			mmio_write_32(GEVENT_CR_PORTx_EVENT_MASK(ap_id, 2), 0x2f);
 			/* Port 4 (Local) - unmask Port 2 */
@@ -281,7 +281,7 @@ static void ap810_setup_events(int ap_id)
 		}
 		break;
 	case 1:
-		if (get_ap_count() == 2) {
+		if (ap810_get_ap_count() == 2) {
 			/* Port 0 - unmask local GEvent */
 			mmio_write_32(GEVENT_CR_PORTx_EVENT_MASK(ap_id, 0), 0x2f);
 			/* Port 4 (Local) - unmask Port 0 */
@@ -332,7 +332,7 @@ static void ap810_generic_timer_init(void)
 	 * In this code, we re-initialize the timer in the all APs.
 	 * TODO: move this code to be timer calibration algorithm
 	 */
-	for (i = 0; i < get_ap_count(); i++) {
+	for (i = 0; i < ap810_get_ap_count(); i++) {
 		/* Disable timer */
 		reg = mmio_read_32(MVEBU_MSS_GTCR_REG(i));
 		reg &= ~MVEBU_MSS_GTCR_ENABLE_BIT;
@@ -343,7 +343,7 @@ static void ap810_generic_timer_init(void)
 		mmio_write_32(MVEBU_MSS_GTCVHR_REG(i), 0x0);
 	}
 
-	if (get_ap_count() == 2) {
+	if (ap810_get_ap_count() == 2) {
 		/* Enable timer */
 		mmio_write_32(MVEBU_MSS_GTCR_REG(0), MVEBU_MSS_GTCR_ENABLE_BIT);
 		mmio_write_32(MVEBU_MSS_GTCR_REG(1), MVEBU_MSS_GTCR_ENABLE_BIT);
@@ -354,7 +354,7 @@ static void ap810_generic_timer_init(void)
 		ap1 = mmio_read_32(MVEBU_MSS_GTCVLR_REG(1));
 		INFO("Read time AP0 = %x - AP1 = %x\n", ap0, ap1);
 #endif
-	} else if (get_ap_count() == 4) {
+	} else if (ap810_get_ap_count() == 4) {
 		mmio_write_32(MVEBU_MSS_GTCR_REG(0), MVEBU_MSS_GTCR_ENABLE_BIT);
 		mmio_write_32(MVEBU_MSS_GTCR_REG(1), MVEBU_MSS_GTCR_ENABLE_BIT);
 		mmio_write_32(MVEBU_MSS_GTCR_REG(2), MVEBU_MSS_GTCR_ENABLE_BIT);
@@ -389,7 +389,7 @@ static void ap810_bl31_init(void)
 	ap810_enumeration_algo();
 #endif
 
-	for (ap_id = 0; ap_id < get_ap_count(); ap_id++) {
+	for (ap_id = 0; ap_id < ap810_get_ap_count(); ap_id++) {
 		INFO("Initialize AP-%d\n", ap_id);
 		/* Setup Aurora2. */
 		ap810_init_aurora2(ap_id);
diff --git a/plat/marvell/a8k-p/common/plat_ble_setup.c b/plat/marvell/a8k-p/common/plat_ble_setup.c
index 8f56c8be..86c68db6 100644
--- a/plat/marvell/a8k-p/common/plat_ble_setup.c
+++ b/plat/marvell/a8k-p/common/plat_ble_setup.c
@@ -42,7 +42,7 @@ int ble_plat_setup(int *skip)
 
 #if !PALLADIUM
 	/* SW WA for AP link bring-up over JTAG connection */
-	if ((get_ap_count() != 1) &&
+	if ((ap810_get_ap_count() != 1) &&
 	    (ap810_rev_id_get(0) == 0))
 		jtag_init_ihb_dual_ap();
 #endif
@@ -55,7 +55,7 @@ int ble_plat_setup(int *skip)
 	ap810_enumeration_algo();
 
 	/* init clocks for single AP */
-	ap810_clocks_init(get_ap_count());
+	ap810_clocks_init(ap810_get_ap_count());
 
 	/* TODO: need to check if need early cpu powerdown */
 
diff --git a/plat/marvell/a8k-p/common/plat_dram.c b/plat/marvell/a8k-p/common/plat_dram.c
index 52926faa..0ccb05ae 100644
--- a/plat/marvell/a8k-p/common/plat_dram.c
+++ b/plat/marvell/a8k-p/common/plat_dram.c
@@ -132,7 +132,7 @@ void plat_dram_freq_update(enum ddr_freq freq_option)
 	uint32_t ifaces_size, i, ap_id;
 
 	/* Update DDR topology for all APs for all interfaces */
-	for (ap_id = 0; ap_id < get_ap_count(); ap_id++) {
+	for (ap_id = 0; ap_id < ap810_get_ap_count(); ap_id++) {
 		plat_dram_ap_ifaces_get(ap_id, &iface, &ifaces_size);
 		for (i = 0; i < ifaces_size; i++, iface++)
 			iface->tm.interface_params[0].memory_freq = freq_option;
@@ -303,7 +303,7 @@ static void plat_dram_interfaces_update(void)
 {
 	struct mv_ddr_iface *iface = NULL;
 	uint32_t ifaces_size, i, ap_id, iface_cnt;
-	const uint32_t ap_cnt = get_ap_count();
+	const uint32_t ap_cnt = ap810_get_ap_count();
 
 	debug_enter();
 
@@ -354,7 +354,7 @@ static void plat_dram_addr_decode_insert(uint32_t ap_id, uint32_t dram_tgt,
 					struct addr_map_win *gwin_temp_win,
 					struct addr_map_win *ccu_dram_win)
 {
-	const uint32_t ap_cnt = get_ap_count();
+	const uint32_t ap_cnt = ap810_get_ap_count();
 
 	/* Add a single GWIN entry to AP0 for enabling remote APs access
 	 * There is no need to open GWIN on other APs, since only AP0
@@ -397,7 +397,7 @@ int plat_dram_init(void)
 {
 	struct mv_ddr_iface *iface = NULL;
 	uint32_t ifaces_size, i, ap_id, ret;
-	const uint32_t ap_cnt = get_ap_count();
+	const uint32_t ap_cnt = ap810_get_ap_count();
 	uint64_t ap_dram_size;
 	uint32_t ap_dram_tgt = DRAM_0_TID;
 
diff --git a/plat/marvell/a8k-p/common/plat_marvell_gicv3.c b/plat/marvell/a8k-p/common/plat_marvell_gicv3.c
index 6b8cee87..fd83887b 100644
--- a/plat/marvell/a8k-p/common/plat_marvell_gicv3.c
+++ b/plat/marvell/a8k-p/common/plat_marvell_gicv3.c
@@ -111,7 +111,7 @@ int gic600_multi_chip_init(void)
 
 	INFO("GIC-600 Multi Chip initialization\n");
 	/* Go over APs and configure the routing table */
-	for (nb_id = 0; nb_id < get_ap_count(); nb_id++) {
+	for (nb_id = 0; nb_id < ap810_get_ap_count(); nb_id++) {
 		unsigned int spi_block_min, spi_blocks;
 
 		INFO("Configure AP %d\n", nb_id);