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| author | Igal Liberman <igall@marvell.com> | 2017-05-15 15:00:47 +0300 |
|---|---|---|
| committer | Kostya Porotchkin <kostap@marvell.com> | 2017-05-17 11:45:50 +0300 |
| commit | 114e4915379cb5245952ac6603c898bd01d6e047 (patch) | |
| tree | 266f0d4a442349cd0d8c3fffe75d508b4eaea864 /readme.md | |
| parent | 7b3edce139d92fa6fedabde782a6ccc87e6d8b98 (diff) | |
fix: pcie: fix pcie clock selection for A2 revision
This patch fixes incorrect handling of pcie clock:
If pcie_clk is set to input (by the Sample-at-Reset),
PCIE refclk buffer 0/1 source field in
PCIe_Reference_Clock_Buffer_Control register should be
set to 1 and not 0 as it done now.
Change-Id: I14fedce9d3299b5b85eb742048f03b17f1f9ab14
Signed-off-by: Igal Liberman <igall@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/39456
Tested-by: iSoC Platform CI <ykjenk@marvell.com>
Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
Reviewed-on: http://vgitil04.il.marvell.com:8080/39544
Diffstat (limited to 'readme.md')
0 files changed, 0 insertions, 0 deletions