diff options
| -rw-r--r-- | plat/marvell/a3700/common/dram_win.c | 29 |
1 files changed, 14 insertions, 15 deletions
diff --git a/plat/marvell/a3700/common/dram_win.c b/plat/marvell/a3700/common/dram_win.c index 6062ec9c..482c7033 100644 --- a/plat/marvell/a3700/common/dram_win.c +++ b/plat/marvell/a3700/common/dram_win.c @@ -79,15 +79,14 @@ struct cpu_win_configuration mv_cpu_wins[CPU_WIN_CONFIG_MAX][MV_CPU_WIN_NUM] = { /* * When total dram size is not over 2GB: * DDR window 0 is configured in tim header, its size may be not 512MB but the - * actual dram size, no need to configure it again; the cpu pcie decode window is - * modified to be aligned with 4GB dram's configuration as below, other cpu windows - * are kept as default. + * actual dram size, no need to configure it again; other cpu windows are kept + * as default. */ { /* enabled target base size remap */ {CPU_WIN_ENABLED, CPU_WIN_TARGET_DRAM, 0x0, 0x08000000, 0x0}, {CPU_WIN_ENABLED, CPU_WIN_TARGET_MCI_EXTERNAL, 0xe0000000, 0x08000000, 0xe0000000}, - {CPU_WIN_ENABLED, CPU_WIN_TARGET_PCIE, 0xd8200000, 0x04000000, 0xd8200000}, + {CPU_WIN_ENABLED, CPU_WIN_TARGET_PCIE, 0xe8000000, 0x08000000, 0xe8000000}, {CPU_WIN_ENABLED, CPU_WIN_TARGET_RWTM_RAM, 0xf0000000, 0x00020000, 0x1fff0000}, {CPU_WIN_ENABLED, CPU_WIN_TARGET_PCIE_OVER_MCI, 0x80000000, 0x10000000, 0x80000000}, }, @@ -95,20 +94,20 @@ struct cpu_win_configuration mv_cpu_wins[CPU_WIN_CONFIG_MAX][MV_CPU_WIN_NUM] = { /* * If total dram size is more than 2GB, now there is only one case - 4GB dram; * we will use below cpu windows configurations: - * - Internal Regs, CCI-400 and Boot Rom windows are kept as default; - * - Use 4 CPU decode windows for DRAM, which cover 3.75GB DRAM; DDR window - * 0 is configured in tim header with 2GB size, no need to configure it again here; - * - The only one CPU decode window left is for PCIe, which has 32MB address. + * - Internal Regs, CCI-400, Boot Rom and PCIe windows are kept as default; + * - Use 4 CPU decode windows for DRAM, which cover 3.375GB DRAM; DDR window 0 + * is configured in tim header with 2GB size, no need to configure it again + * here; 0xFFFFFFFF ---> |-----------------------| | Boot ROM | 64KB 0xFFF00000 ---> +-----------------------+ : : - 0xFC200000 ---> +-----------------------+ - | DDR window 3 | 512 MB - 0xDC200000 ---> |-----------------------| - | PCIE | 64 MB - 0xD8200000 ---> |-----------------------| + 0xF0000000 ---> |-----------------------| + | PCIE | 128 MB + 0xE8000000 ---> |-----------------------| + | DDR window 3 | 128 MB + 0xE0000000 ---> +-----------------------+ : : 0xD8010000 ---> |-----------------------| | CCI Regs | 64 KB @@ -136,8 +135,8 @@ struct cpu_win_configuration mv_cpu_wins[CPU_WIN_CONFIG_MAX][MV_CPU_WIN_NUM] = { {CPU_WIN_ENABLED, CPU_WIN_TARGET_DRAM, 0x0, 0x80000000, 0x0}, {CPU_WIN_ENABLED, CPU_WIN_TARGET_DRAM, 0x80000000, 0x40000000, 0x80000000}, {CPU_WIN_ENABLED, CPU_WIN_TARGET_DRAM, 0xc0000000, 0x10000000, 0xc0000000}, - {CPU_WIN_ENABLED, CPU_WIN_TARGET_DRAM, 0xdc200000, 0x20000000, 0xdc200000}, - {CPU_WIN_ENABLED, CPU_WIN_TARGET_PCIE, 0xd8200000, 0x04000000, 0xd8200000}, + {CPU_WIN_ENABLED, CPU_WIN_TARGET_DRAM, 0xe0000000, 0x08000000, 0xe0000000}, + {CPU_WIN_ENABLED, CPU_WIN_TARGET_PCIE, 0xe8000000, 0x08000000, 0xe8000000}, }, }; |