diff options
| -rw-r--r-- | drivers/marvell/mci.c | 17 | ||||
| -rw-r--r-- | drivers/marvell/mochi/apn806_setup.c | 8 | ||||
| -rw-r--r-- | include/drivers/marvell/mochi/apn806_setup.h | 16 |
3 files changed, 37 insertions, 4 deletions
diff --git a/drivers/marvell/mci.c b/drivers/marvell/mci.c index b9815161..81d7d5ea 100644 --- a/drivers/marvell/mci.c +++ b/drivers/marvell/mci.c @@ -496,10 +496,19 @@ int mci_configure_a1(int mci_index) { int rval; - /* set MCI to support read/write transactions to arrive at the same time */ - rval = mci_enable_simultaneous_transactions(mci_index); - if (rval) - ERROR("Failed to set MCI for simultaneous read/write transactions\n"); + /* When boot source is from MCI, then bootROM is already enabling MCI + * simultaneous transactions (ID assignment), so in that case we must avoid + * enabling it for the 2nd time. + */ + if (apn806_sar_get_bootsrc() != SAR_MCIX4) { + VERBOSE("MCI is not used for boot source: configuring MCI ID assignment\n"); + /* set MCI to support read/write transactions to arrive at the same time */ + rval = mci_enable_simultaneous_transactions(mci_index); + if (rval) + ERROR("Failed to set MCI for simultaneous read/write transactions\n"); + } + else + VERBOSE("MCI is used for boot source: skipping MCI ID assignment\n"); /* enable PHY register mode read/write access */ mci_enable_phy_regs_access(mci_index); diff --git a/drivers/marvell/mochi/apn806_setup.c b/drivers/marvell/mochi/apn806_setup.c index 03ba5872..fb2f4e4b 100644 --- a/drivers/marvell/mochi/apn806_setup.c +++ b/drivers/marvell/mochi/apn806_setup.c @@ -87,6 +87,14 @@ enum axi_attr { AXI_MAX_ATTR, }; +uint32_t apn806_sar_get_bootsrc() +{ + uint32_t reg; + + reg = mmio_read_32(AP806_SAR0_REG_BASE); + return (reg >> AP806_SAR0_BOOT_SOURCE_OFFSET) & AP806_SAR0_BOOT_SOURCE_MASK; +} + static void apn_sec_masters_access_en(uint32_t enable) { uint32_t reg; diff --git a/include/drivers/marvell/mochi/apn806_setup.h b/include/drivers/marvell/mochi/apn806_setup.h index ca41269e..2ca9bffc 100644 --- a/include/drivers/marvell/mochi/apn806_setup.h +++ b/include/drivers/marvell/mochi/apn806_setup.h @@ -44,7 +44,23 @@ #define GWD_IIDR2_REV_ID_OFFSET 12 #define GWD_IIDR2_REV_ID_MASK 0xF +#define AP806_SAR0_REG_BASE (MVEBU_REGS_BASE + 0x6F82D4) +#define AP806_SAR0_BOOT_SOURCE_OFFSET 8 +#define AP806_SAR0_BOOT_SOURCE_MASK 0x7 + +enum ap806_sar_target_dev { + SAR_PIDI_MCIX2 = 0x0, + SAR_MCIX4 = 0x1, + SAR_SPI = 0x2, + SAR_SD = 0x3, + SAR_PIDI_MCIX2_BD = 0x4, /* BootRom disabled */ + SAR_MCIX4_DB = 0x5, /* BootRom disabled */ + SAR_SPI_DB = 0x6, /* BootRom disabled */ + SAR_EMMC = 0x7, +}; + void apn806_init(void); +uint32_t apn806_sar_get_bootsrc(void); static inline int apn806_rev_id_get(void) { |