diff options
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/marvell/amb_adec.c | 38 | ||||
| -rw-r--r-- | drivers/marvell/ap810_aro.c | 2 | ||||
| -rw-r--r-- | drivers/marvell/aro.c | 5 | ||||
| -rw-r--r-- | drivers/marvell/cache_llc.c | 44 | ||||
| -rw-r--r-- | drivers/marvell/ccu.c | 91 | ||||
| -rw-r--r-- | drivers/marvell/comphy.h | 358 | ||||
| -rw-r--r-- | drivers/marvell/comphy/comphy-cp110.h | 575 | ||||
| -rw-r--r-- | drivers/marvell/comphy/phy-comphy-cp110.c | 239 | ||||
| -rw-r--r-- | drivers/marvell/dw-pcie-ep.c | 3 | ||||
| -rw-r--r-- | drivers/marvell/eawg.c | 2 | ||||
| -rw-r--r-- | drivers/marvell/gwin.c | 44 | ||||
| -rw-r--r-- | drivers/marvell/i2c/a8k_i2c.c | 167 | ||||
| -rw-r--r-- | drivers/marvell/icu.c | 2 | ||||
| -rw-r--r-- | drivers/marvell/io_win.c | 68 | ||||
| -rw-r--r-- | drivers/marvell/iob.c | 58 | ||||
| -rw-r--r-- | drivers/marvell/jtag.c | 4 | ||||
| -rw-r--r-- | drivers/marvell/mc_trustzone/mc_trustzone.c | 2 | ||||
| -rw-r--r-- | drivers/marvell/mci.c | 409 | ||||
| -rw-r--r-- | drivers/marvell/mochi/ap807_setup.c | 54 | ||||
| -rw-r--r-- | drivers/marvell/mochi/ap810_setup.c | 2 | ||||
| -rw-r--r-- | drivers/marvell/mochi/apn806_setup.c | 66 | ||||
| -rw-r--r-- | drivers/marvell/mochi/cp110_setup.c | 201 | ||||
| -rw-r--r-- | drivers/marvell/pcie-comphy-cp110.c | 5 | ||||
| -rw-r--r-- | drivers/marvell/thermal.c | 4 |
24 files changed, 1533 insertions, 910 deletions
diff --git a/drivers/marvell/amb_adec.c b/drivers/marvell/amb_adec.c index 6051a51d..d1c930ec 100644 --- a/drivers/marvell/amb_adec.c +++ b/drivers/marvell/amb_adec.c @@ -1,15 +1,17 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ +/* AXI to M-Bridge decoding unit driver for Marvell Armada 8K and 8K+ SoCs */ + +#include <armada_common.h> #include <debug.h> #include <mmio.h> #include <mvebu.h> -#include <plat_config.h> -#include <plat_def.h> +#include <mvebu_def.h> #if LOG_LEVEL >= LOG_LEVEL_INFO #define DEBUG_ADDR_MAP @@ -41,10 +43,10 @@ static void amb_check_win(struct addr_map_win *win, uint32_t win_num) /* make sure the base address is in 16-bit range */ if (win->base_addr > AMB_BASE_ADDR_MASK) { - printf("Warning: Window %d: base address is too big 0x%llx\n", + WARN("Window %d: base address is too big 0x%llx\n", win_num, win->base_addr); win->base_addr = AMB_BASE_ADDR_MASK; - printf("Set the base address to 0x%llx\n", win->base_addr); + WARN("Set the base address to 0x%llx\n", win->base_addr); } base_addr = win->base_addr << AMB_BASE_OFFSET; @@ -52,17 +54,17 @@ static void amb_check_win(struct addr_map_win *win, uint32_t win_num) /* check if address is aligned to 1M */ if (IS_NOT_ALIGN(base_addr, AMB_WIN_ALIGNMENT_1M)) { win->base_addr = ALIGN_UP(base_addr, AMB_WIN_ALIGNMENT_1M); - printf("Warning: Window %d: base address unaligned to 0x%x\n", + WARN("Window %d: base address unaligned to 0x%x\n", win_num, AMB_WIN_ALIGNMENT_1M); - printf("Align up the base address to 0x%llx\n", win->base_addr); + WARN("Align up the base address to 0x%llx\n", win->base_addr); } /* size parameter validity check */ if (!IS_POWER_OF_2(win->win_size)) { - printf("Warning: Window %d: window size is not power of 2 (0x%llx)\n", + WARN("Window %d: window size is not power of 2 (0x%llx)\n", win_num, win->win_size); win->win_size = ROUND_UP_TO_POW_OF_2(win->win_size); - printf("Rounding size to 0x%llx\n", win->win_size); + WARN("Rounding size to 0x%llx\n", win->win_size); } } @@ -70,9 +72,12 @@ static void amb_enable_win(struct addr_map_win *win, uint32_t win_num) { uint32_t ctrl, base, size; - size = (win->win_size / AMB_WIN_ALIGNMENT_64K) - 1; /* size is 64KB granularity. - * The number of 1s specifies the size of the - * window in 64 KB granularity. 0 is 64KB */ + /* + * size is 64KB granularity. + * The number of ones specifies the size of the + * window in 64 KB granularity. 0 is 64KB + */ + size = (win->win_size / AMB_WIN_ALIGNMENT_64K) - 1; ctrl = (size << AMB_SIZE_OFFSET) | (win->target_id << AMB_ATTR_OFFSET); base = win->base_addr << AMB_BASE_OFFSET; @@ -91,8 +96,8 @@ static void dump_amb_adec(void) uint32_t size, size_count; /* Dump all AMB windows */ - printf("bank attribute base size\n"); - printf("--------------------------------------------\n"); + tf_printf("bank attribute base size\n"); + tf_printf("--------------------------------------------\n"); for (win_id = 0; win_id < AMB_MAX_WIN_ID; win_id++) { ctrl = mmio_read_32(AMB_WIN_CR_OFFSET(win_id)); if (ctrl & WIN_ENABLE_BIT) { @@ -100,11 +105,10 @@ static void dump_amb_adec(void) attr = (ctrl >> AMB_ATTR_OFFSET) & AMB_ATTR_MASK; size_count = (ctrl >> AMB_SIZE_OFFSET) & AMB_SIZE_MASK; size = (size_count + 1) * AMB_WIN_ALIGNMENT_64K; - printf("amb 0x%04x 0x%08x 0x%08x\n", attr, base, size); + tf_printf("amb 0x%04x 0x%08x 0x%08x\n", + attr, base, size); } } - - return; } #endif diff --git a/drivers/marvell/ap810_aro.c b/drivers/marvell/ap810_aro.c index 2150c608..451a128c 100644 --- a/drivers/marvell/ap810_aro.c +++ b/drivers/marvell/ap810_aro.c @@ -8,7 +8,7 @@ #include <ap810_setup.h> #include <delay_timer.h> #include <mmio.h> -#include <plat_def.h> +#include <mvebu_def.h> #define ARO_REG_BASE_ADDR(ap) (MVEBU_DFX_SR_BASE(ap) + (0xD00)) #define ARO_CLUSTER_REG0_ADDR(cluster, ap) (ARO_REG_BASE_ADDR(ap) + 0x48 + ((cluster) * 0x8)) diff --git a/drivers/marvell/aro.c b/drivers/marvell/aro.c index 31777afe..9a20568a 100644 --- a/drivers/marvell/aro.c +++ b/drivers/marvell/aro.c @@ -4,13 +4,14 @@ * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + +#include <armada_common.h> #include <aro.h> #include <debug.h> #include <delay_timer.h> #include <mmio.h> #include <mvebu.h> -#include <plat_config.h> -#include <plat_def.h> +#include <mvebu_def.h> #define CPU_ARO_CTRL_BASE MVEBU_REGS_BASE + (0x6F8D00) #define SAR_REG_ADDR MVEBU_REGS_BASE + 0x6f4400 diff --git a/drivers/marvell/cache_llc.c b/drivers/marvell/cache_llc.c index b2ce5bfa..e13e6ce2 100644 --- a/drivers/marvell/cache_llc.c +++ b/drivers/marvell/cache_llc.c @@ -1,23 +1,30 @@ /* - * Copyright (C) 2015 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ +/* LLC driver is the Last Level Cache (L3C) driver + * for Marvell SoCs in AP806, AP807, and AP810 + */ + +#include <arch_helpers.h> #include <assert.h> #include <cache_llc.h> #include <ccu.h> #include <mmio.h> -#include <plat_def.h> +#include <mvebu_def.h> #define CCU_HTC_CR(ap_index) (MVEBU_CCU_BASE(ap_index) + 0x200) #define CCU_SET_POC_OFFSET 5 +extern void ca72_l2_enable_unique_clean(void); + void llc_cache_sync(int ap_index) { - mmio_write_32(LLC_CACHE_SYNC(ap_index), 0); - /* Atumic write no need to wait */ + mmio_write_32(LLC_SYNC(ap_index), 0); + /* Atomic write, no need to wait */ } void llc_flush_all(int ap_index) @@ -42,23 +49,23 @@ void llc_disable(int ap_index) { llc_flush_all(ap_index); mmio_write_32(LLC_CTRL(ap_index), 0); - __asm__ volatile("dsb st"); + dsbishst(); } void llc_enable(int ap_index, int excl_mode) { uint32_t val; - __asm__ volatile("dsb sy"); + dsbsy(); llc_inv_all(ap_index); - __asm__ volatile("dsb sy"); + dsbsy(); val = LLC_CTRL_EN; if (excl_mode) val |= LLC_EXCLUSIVE_EN; mmio_write_32(LLC_CTRL(ap_index), val); - __asm__ volatile("dsb sy"); + dsbsy(); } int llc_is_exclusive(int ap_index) @@ -67,19 +74,11 @@ int llc_is_exclusive(int ap_index) reg = mmio_read_32(LLC_CTRL(ap_index)); - if ((reg & (LLC_CTRL_EN | LLC_EXCLUSIVE_EN)) == (LLC_CTRL_EN | LLC_EXCLUSIVE_EN)) + if ((reg & (LLC_CTRL_EN | LLC_EXCLUSIVE_EN)) == + (LLC_CTRL_EN | LLC_EXCLUSIVE_EN)) return 1; - return 0; -} -void llc_save(int ap_index) -{ - /* TBD */ -} - -void llc_resume(int ap_index) -{ - /* TBD */ + return 0; } void llc_runtime_enable(int ap_index) @@ -93,15 +92,12 @@ void llc_runtime_enable(int ap_index) INFO("Enabling LLC\n"); /* - * Enable L2 UniqueClean evictions + * Enable L2 UniqueClean evictions with data * Note: this configuration assumes that LLC is configured * in exclusive mode. * Later on in the code this assumption will be validated */ - __asm__ volatile ("mrs %0, s3_1_c15_c0_0" : "=r" (reg)); - reg |= (1 << 14); - __asm__ volatile ("msr s3_1_c15_c0_0, %0" : : "r" (reg)); - + ca72_l2_enable_unique_clean(); llc_enable(ap_index, 1); /* Set point of coherency to DDR. diff --git a/drivers/marvell/ccu.c b/drivers/marvell/ccu.c index e71975a7..13246586 100644 --- a/drivers/marvell/ccu.c +++ b/drivers/marvell/ccu.c @@ -1,16 +1,17 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ +/* CCU unit device driver for Marvell AP807, AP807 and AP810 SoCs */ +#include <armada_common.h> #include <ccu.h> #include <debug.h> #include <mmio.h> #include <mvebu.h> -#include <plat_config.h> -#include <plat_def.h> +#include <mvebu_def.h> #if LOG_LEVEL >= LOG_LEVEL_INFO #define DEBUG_ADDR_MAP @@ -38,24 +39,26 @@ static void dump_ccu(int ap_index) uint64_t start, end; /* Dump all AP windows */ - printf("\tbank target start end\n"); - printf("\t----------------------------------------------------\n"); + tf_printf("\tbank target start end\n"); + tf_printf("\t----------------------------------------------------\n"); for (win_id = 0; win_id < MVEBU_CCU_MAX_WINS; win_id++) { win_cr = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)); if (win_cr & WIN_ENABLE_BIT) { - target_id = (win_cr >> CCU_TARGET_ID_OFFSET) & CCU_TARGET_ID_MASK; - alr = mmio_read_32(CCU_WIN_ALR_OFFSET(ap_index, win_id)); - ahr = mmio_read_32(CCU_WIN_AHR_OFFSET(ap_index, win_id)); + target_id = (win_cr >> CCU_TARGET_ID_OFFSET) & + CCU_TARGET_ID_MASK; + alr = mmio_read_32(CCU_WIN_ALR_OFFSET(ap_index, + win_id)); + ahr = mmio_read_32(CCU_WIN_AHR_OFFSET(ap_index, + win_id)); start = ((uint64_t)alr << ADDRESS_SHIFT); end = (((uint64_t)ahr + 0x10) << ADDRESS_SHIFT); - printf("\tccu %02x 0x%016llx 0x%016llx\n", target_id, start, end); + tf_printf("\tccu %02x 0x%016llx 0x%016llx\n", + target_id, start, end); } } win_cr = mmio_read_32(CCU_WIN_GCR_OFFSET(ap_index)); target_id = (win_cr >> CCU_GCR_TARGET_OFFSET) & CCU_GCR_TARGET_MASK; - printf("\tccu GCR %d - all other transactions\n", target_id); - - return; + tf_printf("\tccu GCR %d - all other transactions\n", target_id); } #endif @@ -64,13 +67,15 @@ void ccu_win_check(struct addr_map_win *win) /* check if address is aligned to 1M */ if (IS_NOT_ALIGN(win->base_addr, CCU_WIN_ALIGNMENT)) { win->base_addr = ALIGN_UP(win->base_addr, CCU_WIN_ALIGNMENT); - NOTICE("%s: Align up the base address to 0x%llx\n", __func__, win->base_addr); + NOTICE("%s: Align up the base address to 0x%llx\n", + __func__, win->base_addr); } /* size parameter validity check */ if (IS_NOT_ALIGN(win->win_size, CCU_WIN_ALIGNMENT)) { win->win_size = ALIGN_UP(win->win_size, CCU_WIN_ALIGNMENT); - NOTICE("%s: Aligning size to 0x%llx\n", __func__, win->win_size); + NOTICE("%s: Aligning size to 0x%llx\n", + __func__, win->win_size); } } @@ -93,7 +98,8 @@ void ccu_enable_win(int ap_index, struct addr_map_win *win, uint32_t win_id) mmio_write_32(CCU_WIN_AHR_OFFSET(ap_index, win_id), ahr); ccu_win_reg = WIN_ENABLE_BIT; - ccu_win_reg |= (win->target_id & CCU_TARGET_ID_MASK) << CCU_TARGET_ID_OFFSET; + ccu_win_reg |= (win->target_id & CCU_TARGET_ID_MASK) + << CCU_TARGET_ID_OFFSET; mmio_write_32(CCU_WIN_CR_OFFSET(ap_index, win_id), ccu_win_reg); } @@ -142,6 +148,7 @@ void ccu_temp_win_remove(int ap_index, struct addr_map_win *win, int size) for (int i = 0; i < size; i++) { uint64_t base; uint32_t target; + win_id = MVEBU_CCU_MAX_WINS - 1 - i; target = mmio_read_32(CCU_WIN_CR_OFFSET(ap_index, win_id)); @@ -152,7 +159,8 @@ void ccu_temp_win_remove(int ap_index, struct addr_map_win *win, int size) base <<= ADDRESS_SHIFT; if ((win->target_id != target) || (win->base_addr != base)) { - ERROR("%s: Trying to remove bad window-%d!\n", __func__, win_id); + ERROR("%s: Trying to remove bad window-%d!\n", + __func__, win_id); continue; } ccu_disable_win(ap_index, win_id); @@ -175,7 +183,8 @@ static uint32_t ccu_dram_target_get(int ap_index) /* On BLE stage the AP0 DRAM window is opened by the BootROM at index 2. * All the rest of detected APs will use window at index 1. - * The AP0 DRAM window is moved from index 2 to 1 during init_ccu() execution. + * The AP0 DRAM window is moved from index 2 to 1 during + * init_ccu() execution. */ const uint32_t win_id = (ap_index == 0) ? 2 : 1; uint32_t target; @@ -191,7 +200,8 @@ void ccu_dram_target_set(int ap_index, uint32_t target) { /* On BLE stage the AP0 DRAM window is opened by the BootROM at index 2. * All the rest of detected APs will use window at index 1. - * The AP0 DRAM window is moved from index 2 to 1 during init_ccu() execution. + * The AP0 DRAM window is moved from index 2 to 1 + * during init_ccu() execution. */ const uint32_t win_id = (ap_index == 0) ? 2 : 1; uint32_t dram_cr; @@ -212,24 +222,25 @@ void ccu_dram_win_config(int ap_index, struct addr_map_win *win) */ const uint32_t win_id = (ap_index == 0) ? 2 : 1; #else /* end of BLE */ - /* At the ccu_init() execution stage, DRAM windows of all APs are arranged at index 1. - * The AP0 still has the old window BootROM DRAM at index 2, so the window-1 can be safely - * disabled without breaking the DRAM access. + /* At the ccu_init() execution stage, DRAM windows of all APs + * are arranged at index 1. + * The AP0 still has the old window BootROM DRAM at index 2, so + * the window-1 can be safely disabled without breaking the DRAM access. */ const uint32_t win_id = 1; #endif ccu_disable_win(ap_index, win_id); /* enable write secure (and clear read secure) */ - mmio_write_32(CCU_WIN_SCR_OFFSET(ap_index, win_id), CCU_WIN_ENA_WRITE_SECURE); + mmio_write_32(CCU_WIN_SCR_OFFSET(ap_index, win_id), + CCU_WIN_ENA_WRITE_SECURE); ccu_win_check(win); ccu_enable_win(ap_index, win, win_id); - - return; } /* Save content of CCU window + GCR */ -static void ccu_save_win_range(int ap_id, int win_first, int win_last, uint32_t *buffer) +static void ccu_save_win_range(int ap_id, int win_first, + int win_last, uint32_t *buffer) { int win_id, idx; /* Save CCU */ @@ -243,7 +254,8 @@ static void ccu_save_win_range(int ap_id, int win_first, int win_last, uint32_t } /* Restore content of CCU window + GCR */ -static void ccu_restore_win_range(int ap_id, int win_first, int win_last, uint32_t *buffer) +static void ccu_restore_win_range(int ap_id, int win_first, + int win_last, uint32_t *buffer) { int win_id, idx; /* Restore CCU */ @@ -288,25 +300,27 @@ int init_ccu(int ap_index) if (win_count <= 0) { INFO("No windows configurations found\n"); } else if (win_count > (MVEBU_CCU_MAX_WINS - 1)) { - ERROR("CCU memory map array greater than max available windows, set win_count to max %d\n", + ERROR("CCU mem map array > than max available windows (%d)\n", MVEBU_CCU_MAX_WINS); win_count = MVEBU_CCU_MAX_WINS; } - /* Need to set GCR to DRAM before all CCU windows are disabled for securing the normal access - * to DRAM location, which the ATF is running from. Once all CCU windows are set, which have to - * include the dedicated DRAM window as well, the GCR can be switched to the target defined - * by the platform configuration. + /* Need to set GCR to DRAM before all CCU windows are disabled for + * securing the normal access to DRAM location, which the ATF is running + * from. Once all CCU windows are set, which have to include the + * dedicated DRAM window as well, the GCR can be switched to the target + * defined by the platform configuration. */ dram_target = ccu_dram_target_get(ap_index); win_reg = (dram_target & CCU_GCR_TARGET_MASK) << CCU_GCR_TARGET_OFFSET; mmio_write_32(CCU_WIN_GCR_OFFSET(ap_index), win_reg); /* If the DRAM window was already configured at the BLE stage, - * only the window target considered valid, the address range should be updated - * according to the platform configuration. + * only the window target considered valid, the address range should be + * updated according to the platform configuration. */ - for (dram_win = win, array_id = 0; array_id < win_count; array_id++, dram_win++) { + for (dram_win = win, array_id = 0; array_id < win_count; + array_id++, dram_win++) { if (IS_DRAM_TARGET(dram_win->target_id)) { dram_win->target_id = dram_target; break; @@ -320,14 +334,16 @@ int init_ccu(int ap_index) for (win_id = win_start; win_id < MVEBU_CCU_MAX_WINS; win_id++) { ccu_disable_win(ap_index, win_id); /* enable write secure (and clear read secure) */ - mmio_write_32(CCU_WIN_SCR_OFFSET(ap_index, win_id), CCU_WIN_ENA_WRITE_SECURE); + mmio_write_32(CCU_WIN_SCR_OFFSET(ap_index, win_id), + CCU_WIN_ENA_WRITE_SECURE); } /* win_id is the index of the current ccu window * array_id is the index of the current memory map window entry */ for (win_id = win_start, array_id = 0; - ((win_id < MVEBU_CCU_MAX_WINS) && (array_id < win_count)); win_id++) { + ((win_id < MVEBU_CCU_MAX_WINS) && (array_id < win_count)); + win_id++) { ccu_win_check(win); ccu_enable_win(ap_index, win, win_id); win++; @@ -335,7 +351,8 @@ int init_ccu(int ap_index) } /* Get & set the default target according to board topology */ - win_reg = (marvell_get_ccu_gcr_target(ap_index) & CCU_GCR_TARGET_MASK) << CCU_GCR_TARGET_OFFSET; + win_reg = (marvell_get_ccu_gcr_target(ap_index) & CCU_GCR_TARGET_MASK) + << CCU_GCR_TARGET_OFFSET; mmio_write_32(CCU_WIN_GCR_OFFSET(ap_index), win_reg); #ifdef DEBUG_ADDR_MAP diff --git a/drivers/marvell/comphy.h b/drivers/marvell/comphy.h index 9ae98513..788b1b60 100644 --- a/drivers/marvell/comphy.h +++ b/drivers/marvell/comphy.h @@ -1,100 +1,132 @@ /* - * Copyright (C) 2016 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + +/* Driver for COMPHY unit that is part or Marvell A8K SoCs */ + #ifndef _COMPHY_H_ #define _COMPHY_H_ /* COMPHY registers */ #define COMMON_PHY_CFG1_REG 0x0 #define COMMON_PHY_CFG1_PWR_UP_OFFSET 1 -#define COMMON_PHY_CFG1_PWR_UP_MASK (0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET) +#define COMMON_PHY_CFG1_PWR_UP_MASK \ + (0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET) #define COMMON_PHY_CFG1_PIPE_SELECT_OFFSET 2 -#define COMMON_PHY_CFG1_PIPE_SELECT_MASK (0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET) +#define COMMON_PHY_CFG1_PIPE_SELECT_MASK \ + (0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET) #define COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET 13 -#define COMMON_PHY_CFG1_PWR_ON_RESET_MASK (0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET) +#define COMMON_PHY_CFG1_PWR_ON_RESET_MASK \ + (0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET) #define COMMON_PHY_CFG1_CORE_RSTN_OFFSET 14 -#define COMMON_PHY_CFG1_CORE_RSTN_MASK (0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET) +#define COMMON_PHY_CFG1_CORE_RSTN_MASK \ + (0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET) #define COMMON_PHY_PHY_MODE_OFFSET 15 -#define COMMON_PHY_PHY_MODE_MASK (0x1 << COMMON_PHY_PHY_MODE_OFFSET) +#define COMMON_PHY_PHY_MODE_MASK \ + (0x1 << COMMON_PHY_PHY_MODE_OFFSET) -#define COMMON_SELECTOR_PHY_OFFSET 0x140 -#define COMMON_SELECTOR_PIPE_OFFSET 0x144 +#define COMMON_SELECTOR_PHY_OFFSET 0x140 +#define COMMON_SELECTOR_PIPE_OFFSET 0x144 -#define COMMON_PHY_SD_CTRL1 0x148 +#define COMMON_PHY_SD_CTRL1 0x148 #define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_OFFSET 0 #define COMMON_PHY_SD_CTRL1_COMPHY_0_4_PORT_MASK 0xFFFF -#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET 24 -#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET) -#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET 25 -#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET) +#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET 24 +#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK \ + (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET) +#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET 25 +#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK \ + (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET) #define DFX_DEV_GEN_CTRL12 0x80 #define DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET 7 -#define DFX_DEV_GEN_PCIE_CLK_SRC_MASK (0x3 << DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET) +#define DFX_DEV_GEN_PCIE_CLK_SRC_MASK \ + (0x3 << DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET) /* HPIPE register */ #define HPIPE_PWR_PLL_REG 0x4 #define HPIPE_PWR_PLL_REF_FREQ_OFFSET 0 -#define HPIPE_PWR_PLL_REF_FREQ_MASK (0x1f << HPIPE_PWR_PLL_REF_FREQ_OFFSET) +#define HPIPE_PWR_PLL_REF_FREQ_MASK \ + (0x1f << HPIPE_PWR_PLL_REF_FREQ_OFFSET) #define HPIPE_PWR_PLL_PHY_MODE_OFFSET 5 -#define HPIPE_PWR_PLL_PHY_MODE_MASK (0x7 << HPIPE_PWR_PLL_PHY_MODE_OFFSET) +#define HPIPE_PWR_PLL_PHY_MODE_MASK \ + (0x7 << HPIPE_PWR_PLL_PHY_MODE_OFFSET) #define HPIPE_DFE_REG0 0x01C #define HPIPE_DFE_RES_FORCE_OFFSET 15 -#define HPIPE_DFE_RES_FORCE_MASK (0x1 << HPIPE_DFE_RES_FORCE_OFFSET) +#define HPIPE_DFE_RES_FORCE_MASK \ + (0x1 << HPIPE_DFE_RES_FORCE_OFFSET) #define HPIPE_G2_SET_1_REG 0x040 #define HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET 0 -#define HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET) +#define HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK \ + (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET) #define HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET 3 -#define HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET) +#define HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK \ + (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET) #define HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET 6 -#define HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET) +#define HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK \ + (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET) #define HPIPE_G3_SETTINGS_1_REG 0x048 #define HPIPE_G3_RX_SELMUPI_OFFSET 0 -#define HPIPE_G3_RX_SELMUPI_MASK (0x7 << HPIPE_G3_RX_SELMUPI_OFFSET) +#define HPIPE_G3_RX_SELMUPI_MASK \ + (0x7 << HPIPE_G3_RX_SELMUPI_OFFSET) #define HPIPE_G3_RX_SELMUPF_OFFSET 3 -#define HPIPE_G3_RX_SELMUPF_MASK (0x7 << HPIPE_G3_RX_SELMUPF_OFFSET) +#define HPIPE_G3_RX_SELMUPF_MASK \ + (0x7 << HPIPE_G3_RX_SELMUPF_OFFSET) #define HPIPE_G3_SETTING_BIT_OFFSET 13 -#define HPIPE_G3_SETTING_BIT_MASK (0x1 << HPIPE_G3_SETTING_BIT_OFFSET) +#define HPIPE_G3_SETTING_BIT_MASK \ + (0x1 << HPIPE_G3_SETTING_BIT_OFFSET) #define HPIPE_INTERFACE_REG 0x94 #define HPIPE_INTERFACE_GEN_MAX_OFFSET 10 -#define HPIPE_INTERFACE_GEN_MAX_MASK (0x3 << HPIPE_INTERFACE_GEN_MAX_OFFSET) +#define HPIPE_INTERFACE_GEN_MAX_MASK \ + (0x3 << HPIPE_INTERFACE_GEN_MAX_OFFSET) #define HPIPE_INTERFACE_DET_BYPASS_OFFSET 12 -#define HPIPE_INTERFACE_DET_BYPASS_MASK (0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET) +#define HPIPE_INTERFACE_DET_BYPASS_MASK \ + (0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET) #define HPIPE_INTERFACE_LINK_TRAIN_OFFSET 14 -#define HPIPE_INTERFACE_LINK_TRAIN_MASK (0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET) +#define HPIPE_INTERFACE_LINK_TRAIN_MASK \ + (0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET) #define HPIPE_VDD_CAL_CTRL_REG 0x114 #define HPIPE_EXT_SELLV_RXSAMPL_OFFSET 5 -#define HPIPE_EXT_SELLV_RXSAMPL_MASK (0x1f << HPIPE_EXT_SELLV_RXSAMPL_OFFSET) +#define HPIPE_EXT_SELLV_RXSAMPL_MASK \ + (0x1f << HPIPE_EXT_SELLV_RXSAMPL_OFFSET) -#define HPIPE_PCIE_REG0 0x120 +#define HPIPE_PCIE_REG0 0x120 #define HPIPE_PCIE_IDLE_SYNC_OFFSET 12 -#define HPIPE_PCIE_IDLE_SYNC_MASK (0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET) +#define HPIPE_PCIE_IDLE_SYNC_MASK \ + (0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET) #define HPIPE_PCIE_SEL_BITS_OFFSET 13 -#define HPIPE_PCIE_SEL_BITS_MASK (0x3 << HPIPE_PCIE_SEL_BITS_OFFSET) +#define HPIPE_PCIE_SEL_BITS_MASK \ + (0x3 << HPIPE_PCIE_SEL_BITS_OFFSET) #define HPIPE_LANE_ALIGN_REG 0x124 #define HPIPE_LANE_ALIGN_OFF_OFFSET 12 -#define HPIPE_LANE_ALIGN_OFF_MASK (0x1 << HPIPE_LANE_ALIGN_OFF_OFFSET) +#define HPIPE_LANE_ALIGN_OFF_MASK \ + (0x1 << HPIPE_LANE_ALIGN_OFF_OFFSET) #define HPIPE_MISC_REG 0x13C #define HPIPE_MISC_CLK100M_125M_OFFSET 4 -#define HPIPE_MISC_CLK100M_125M_MASK (0x1 << HPIPE_MISC_CLK100M_125M_OFFSET) +#define HPIPE_MISC_CLK100M_125M_MASK \ + (0x1 << HPIPE_MISC_CLK100M_125M_OFFSET) #define HPIPE_MISC_ICP_FORCE_OFFSET 5 -#define HPIPE_MISC_ICP_FORCE_MASK (0x1 << HPIPE_MISC_ICP_FORCE_OFFSET) +#define HPIPE_MISC_ICP_FORCE_MASK \ + (0x1 << HPIPE_MISC_ICP_FORCE_OFFSET) #define HPIPE_MISC_TXDCLK_2X_OFFSET 6 -#define HPIPE_MISC_TXDCLK_2X_MASK (0x1 << HPIPE_MISC_TXDCLK_2X_OFFSET) +#define HPIPE_MISC_TXDCLK_2X_MASK \ + (0x1 << HPIPE_MISC_TXDCLK_2X_OFFSET) #define HPIPE_MISC_CLK500_EN_OFFSET 7 -#define HPIPE_MISC_CLK500_EN_MASK (0x1 << HPIPE_MISC_CLK500_EN_OFFSET) +#define HPIPE_MISC_CLK500_EN_MASK \ + (0x1 << HPIPE_MISC_CLK500_EN_OFFSET) #define HPIPE_MISC_REFCLK_SEL_OFFSET 10 -#define HPIPE_MISC_REFCLK_SEL_MASK (0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET) +#define HPIPE_MISC_REFCLK_SEL_MASK \ + (0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET) #define HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG 0x16C #define HPIPE_SMAPLER_OFFSET 12 @@ -102,76 +134,101 @@ #define HPIPE_PWR_CTR_DTL_REG 0x184 #define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET 2 -#define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK (0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET) +#define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK \ + (0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET) #define HPIPE_FRAME_DET_CONTROL_REG 0x220 #define HPIPE_FRAME_DET_LOCK_LOST_TO_OFFSET 12 -#define HPIPE_FRAME_DET_LOCK_LOST_TO_MASK (0x1 << HPIPE_FRAME_DET_LOCK_LOST_TO_OFFSET) +#define HPIPE_FRAME_DET_LOCK_LOST_TO_MASK \ + (0x1 << HPIPE_FRAME_DET_LOCK_LOST_TO_OFFSET) #define HPIPE_TX_TRAIN_CTRL_0_REG 0x268 #define HPIPE_TX_TRAIN_P2P_HOLD_OFFSET 15 -#define HPIPE_TX_TRAIN_P2P_HOLD_MASK (0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET) +#define HPIPE_TX_TRAIN_P2P_HOLD_MASK \ + (0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET) #define HPIPE_TX_TRAIN_CTRL_REG 0x26C #define HPIPE_TX_TRAIN_CTRL_G1_OFFSET 0 -#define HPIPE_TX_TRAIN_CTRL_G1_MASK (0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET) +#define HPIPE_TX_TRAIN_CTRL_G1_MASK \ + (0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET) #define HPIPE_TX_TRAIN_CTRL_GN1_OFFSET 1 -#define HPIPE_TX_TRAIN_CTRL_GN1_MASK (0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET) +#define HPIPE_TX_TRAIN_CTRL_GN1_MASK \ + (0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET) #define HPIPE_TX_TRAIN_CTRL_G0_OFFSET 2 -#define HPIPE_TX_TRAIN_CTRL_G0_MASK (0x1 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET) +#define HPIPE_TX_TRAIN_CTRL_G0_MASK \ + (0x1 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET) #define HPIPE_TX_TRAIN_CTRL_4_REG 0x278 #define HPIPE_TRX_TRAIN_TIMER_OFFSET 0 -#define HPIPE_TRX_TRAIN_TIMER_MASK (0x3FF << HPIPE_TRX_TRAIN_TIMER_OFFSET) +#define HPIPE_TRX_TRAIN_TIMER_MASK \ + (0x3FF << HPIPE_TRX_TRAIN_TIMER_OFFSET) #define HPIPE_TX_TRAIN_CTRL_5_REG 0x2A4 #define HPIPE_TX_TRAIN_START_SQ_EN_OFFSET 11 -#define HPIPE_TX_TRAIN_START_SQ_EN_MASK (0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET) +#define HPIPE_TX_TRAIN_START_SQ_EN_MASK \ + (0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET) #define HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET 12 -#define HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK (0x1 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET) +#define HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK \ + (0x1 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET) #define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET 13 -#define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK (0x1 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET) +#define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK \ + (0x1 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET) #define HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET 14 -#define HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK (0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET) +#define HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK \ + (0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET) #define HPIPE_TX_TRAIN_REG 0x31C #define HPIPE_TX_TRAIN_CHK_INIT_OFFSET 4 -#define HPIPE_TX_TRAIN_CHK_INIT_MASK (0x1 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET) +#define HPIPE_TX_TRAIN_CHK_INIT_MASK \ + (0x1 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET) #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET 7 -#define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK (0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET) +#define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK \ + (0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET) #define HPIPE_CDR_CONTROL_REG 0x418 #define HPIPE_CDR_RX_MAX_DFE_ADAPT_0_OFFSET 14 -#define HPIPE_CDR_RX_MAX_DFE_ADAPT_0_MASK (0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_0_OFFSET) +#define HPIPE_CDR_RX_MAX_DFE_ADAPT_0_MASK \ + (0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_0_OFFSET) #define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET 12 -#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK (0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET) +#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK \ + (0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET) #define HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET 9 -#define HPIPE_CDR_MAX_DFE_ADAPT_0_MASK (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET) +#define HPIPE_CDR_MAX_DFE_ADAPT_0_MASK \ + (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET) #define HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET 6 -#define HPIPE_CDR_MAX_DFE_ADAPT_1_MASK (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET) +#define HPIPE_CDR_MAX_DFE_ADAPT_1_MASK \ + (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET) #define HPIPE_TX_TRAIN_CTRL_11_REG 0x438 #define HPIPE_TX_STATUS_CHECK_MODE_OFFSET 6 -#define HPIPE_TX_TX_STATUS_CHECK_MODE_MASK (0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET) +#define HPIPE_TX_TX_STATUS_CHECK_MODE_MASK \ + (0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET) #define HPIPE_TX_NUM_OF_PRESET_OFFSET 10 -#define HPIPE_TX_NUM_OF_PRESET_MASK (0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET) +#define HPIPE_TX_NUM_OF_PRESET_MASK \ + (0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET) #define HPIPE_TX_SWEEP_PRESET_EN_OFFSET 15 -#define HPIPE_TX_SWEEP_PRESET_EN_MASK (0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET) +#define HPIPE_TX_SWEEP_PRESET_EN_MASK \ + (0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET) #define HPIPE_G2_SETTINGS_4_REG 0x44C #define HPIPE_G2_DFE_RES_OFFSET 8 #define HPIPE_G2_DFE_RES_MASK (0x3 << HPIPE_G2_DFE_RES_OFFSET) #define HPIPE_G3_SETTING_3_REG 0x450 #define HPIPE_G3_FFE_CAP_SEL_OFFSET 0 -#define HPIPE_G3_FFE_CAP_SEL_MASK (0xf << HPIPE_G3_FFE_CAP_SEL_OFFSET) +#define HPIPE_G3_FFE_CAP_SEL_MASK \ + (0xf << HPIPE_G3_FFE_CAP_SEL_OFFSET) #define HPIPE_G3_FFE_RES_SEL_OFFSET 4 -#define HPIPE_G3_FFE_RES_SEL_MASK (0x7 << HPIPE_G3_FFE_RES_SEL_OFFSET) +#define HPIPE_G3_FFE_RES_SEL_MASK \ + (0x7 << HPIPE_G3_FFE_RES_SEL_OFFSET) #define HPIPE_G3_FFE_SETTING_FORCE_OFFSET 7 -#define HPIPE_G3_FFE_SETTING_FORCE_MASK (0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET) +#define HPIPE_G3_FFE_SETTING_FORCE_MASK \ + (0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET) #define HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET 12 -#define HPIPE_G3_FFE_DEG_RES_LEVEL_MASK (0x3 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET) +#define HPIPE_G3_FFE_DEG_RES_LEVEL_MASK \ + (0x3 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET) #define HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET 14 -#define HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK (0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET) +#define HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK \ + (0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET) #define HPIPE_G3_SETTING_4_REG 0x454 #define HPIPE_G3_DFE_RES_OFFSET 8 @@ -179,23 +236,28 @@ #define HPIPE_DFE_CONTROL_REG 0x470 #define HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET 14 -#define HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK (0x3 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET) +#define HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK \ + (0x3 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET) #define HPIPE_DFE_CTRL_28_REG 0x49C #define HPIPE_DFE_CTRL_28_PIPE4_OFFSET 7 -#define HPIPE_DFE_CTRL_28_PIPE4_MASK (0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET) +#define HPIPE_DFE_CTRL_28_PIPE4_MASK \ + (0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET) #define HPIPE_G3_SETTING_5_REG 0x548 #define HPIPE_G3_SETTING_5_G3_ICP_OFFSET 0 -#define HPIPE_G3_SETTING_5_G3_ICP_MASK (0xf << HPIPE_G3_SETTING_5_G3_ICP_OFFSET) +#define HPIPE_G3_SETTING_5_G3_ICP_MASK \ + (0xf << HPIPE_G3_SETTING_5_G3_ICP_OFFSET) #define HPIPE_LANE_STATUS1_REG 0x60C #define HPIPE_LANE_STATUS1_PCLK_EN_OFFSET 0 -#define HPIPE_LANE_STATUS1_PCLK_EN_MASK (0x1 << HPIPE_LANE_STATUS1_PCLK_EN_OFFSET) +#define HPIPE_LANE_STATUS1_PCLK_EN_MASK \ + (0x1 << HPIPE_LANE_STATUS1_PCLK_EN_OFFSET) -#define HPIPE_LANE_CFG4_REG 0x620 +#define HPIPE_LANE_CFG4_REG 0x620 #define HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET 3 -#define HPIPE_LANE_CFG4_DFE_EN_SEL_MASK (0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET) +#define HPIPE_LANE_CFG4_DFE_EN_SEL_MASK \ + (0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET) #define HPIPE_LANE_EQU_CONFIG_0_REG 0x69C #define HPIPE_CFG_EQ_FS_OFFSET 0 @@ -203,157 +265,209 @@ #define HPIPE_CFG_EQ_LF_OFFSET 6 #define HPIPE_CFG_EQ_LF_MASK (0x3f << HPIPE_CFG_EQ_LF_OFFSET) #define HPIPE_CFG_PHY_RC_EP_OFFSET 12 -#define HPIPE_CFG_PHY_RC_EP_MASK (0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET) +#define HPIPE_CFG_PHY_RC_EP_MASK \ + (0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET) #define HPIPE_LANE_EQ_CFG1_REG 0x6a0 #define HPIPE_CFG_UPDATE_POLARITY_OFFSET 12 -#define HPIPE_CFG_UPDATE_POLARITY_MASK (0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET) +#define HPIPE_CFG_UPDATE_POLARITY_MASK \ + (0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET) #define HPIPE_LANE_EQ_CFG2_REG 0x6a4 #define HPIPE_CFG_EQ_BUNDLE_DIS_OFFSET 14 -#define HPIPE_CFG_EQ_BUNDLE_DIS_MASK (0x1 << HPIPE_CFG_EQ_BUNDLE_DIS_OFFSET) +#define HPIPE_CFG_EQ_BUNDLE_DIS_MASK \ + (0x1 << HPIPE_CFG_EQ_BUNDLE_DIS_OFFSET) #define HPIPE_LANE_PRESET_CFG0_REG 0x6a8 #define HPIPE_CFG_CURSOR_PRESET0_OFFSET 0 -#define HPIPE_CFG_CURSOR_PRESET0_MASK (0x3f << HPIPE_CFG_CURSOR_PRESET0_OFFSET) +#define HPIPE_CFG_CURSOR_PRESET0_MASK \ + (0x3f << HPIPE_CFG_CURSOR_PRESET0_OFFSET) #define HPIPE_CFG_CURSOR_PRESET1_OFFSET 6 -#define HPIPE_CFG_CURSOR_PRESET1_MASK (0x3f << HPIPE_CFG_CURSOR_PRESET1_OFFSET) +#define HPIPE_CFG_CURSOR_PRESET1_MASK \ + (0x3f << HPIPE_CFG_CURSOR_PRESET1_OFFSET) #define HPIPE_LANE_PRESET_CFG1_REG 0x6ac #define HPIPE_CFG_CURSOR_PRESET2_OFFSET 0 -#define HPIPE_CFG_CURSOR_PRESET2_MASK (0x3f << HPIPE_CFG_CURSOR_PRESET2_OFFSET) +#define HPIPE_CFG_CURSOR_PRESET2_MASK \ + (0x3f << HPIPE_CFG_CURSOR_PRESET2_OFFSET) #define HPIPE_CFG_CURSOR_PRESET3_OFFSET 6 -#define HPIPE_CFG_CURSOR_PRESET3_MASK (0x3f << HPIPE_CFG_CURSOR_PRESET3_OFFSET) +#define HPIPE_CFG_CURSOR_PRESET3_MASK \ + (0x3f << HPIPE_CFG_CURSOR_PRESET3_OFFSET) #define HPIPE_LANE_PRESET_CFG2_REG 0x6b0 #define HPIPE_CFG_CURSOR_PRESET4_OFFSET 0 -#define HPIPE_CFG_CURSOR_PRESET4_MASK (0x3f << HPIPE_CFG_CURSOR_PRESET4_OFFSET) +#define HPIPE_CFG_CURSOR_PRESET4_MASK \ + (0x3f << HPIPE_CFG_CURSOR_PRESET4_OFFSET) #define HPIPE_CFG_CURSOR_PRESET5_OFFSET 6 -#define HPIPE_CFG_CURSOR_PRESET5_MASK (0x3f << HPIPE_CFG_CURSOR_PRESET5_OFFSET) +#define HPIPE_CFG_CURSOR_PRESET5_MASK \ + (0x3f << HPIPE_CFG_CURSOR_PRESET5_OFFSET) #define HPIPE_LANE_PRESET_CFG3_REG 0x6b4 #define HPIPE_CFG_CURSOR_PRESET6_OFFSET 0 -#define HPIPE_CFG_CURSOR_PRESET6_MASK (0x3f << HPIPE_CFG_CURSOR_PRESET6_OFFSET) +#define HPIPE_CFG_CURSOR_PRESET6_MASK \ + (0x3f << HPIPE_CFG_CURSOR_PRESET6_OFFSET) #define HPIPE_CFG_CURSOR_PRESET7_OFFSET 6 -#define HPIPE_CFG_CURSOR_PRESET7_MASK (0x3f << HPIPE_CFG_CURSOR_PRESET7_OFFSET) +#define HPIPE_CFG_CURSOR_PRESET7_MASK \ + (0x3f << HPIPE_CFG_CURSOR_PRESET7_OFFSET) #define HPIPE_LANE_PRESET_CFG4_REG 0x6b8 #define HPIPE_CFG_CURSOR_PRESET8_OFFSET 0 -#define HPIPE_CFG_CURSOR_PRESET8_MASK (0x3f << HPIPE_CFG_CURSOR_PRESET8_OFFSET) +#define HPIPE_CFG_CURSOR_PRESET8_MASK \ + (0x3f << HPIPE_CFG_CURSOR_PRESET8_OFFSET) #define HPIPE_CFG_CURSOR_PRESET9_OFFSET 6 -#define HPIPE_CFG_CURSOR_PRESET9_MASK (0x3f << HPIPE_CFG_CURSOR_PRESET9_OFFSET) +#define HPIPE_CFG_CURSOR_PRESET9_MASK \ + (0x3f << HPIPE_CFG_CURSOR_PRESET9_OFFSET) #define HPIPE_LANE_PRESET_CFG5_REG 0x6bc #define HPIPE_CFG_CURSOR_PRESET10_OFFSET 0 -#define HPIPE_CFG_CURSOR_PRESET10_MASK (0x3f << HPIPE_CFG_CURSOR_PRESET10_OFFSET) +#define HPIPE_CFG_CURSOR_PRESET10_MASK \ + (0x3f << HPIPE_CFG_CURSOR_PRESET10_OFFSET) #define HPIPE_CFG_CURSOR_PRESET11_OFFSET 6 -#define HPIPE_CFG_CURSOR_PRESET11_MASK (0x3f << HPIPE_CFG_CURSOR_PRESET11_OFFSET) +#define HPIPE_CFG_CURSOR_PRESET11_MASK \ + (0x3f << HPIPE_CFG_CURSOR_PRESET11_OFFSET) #define HPIPE_LANE_PRESET_CFG6_REG 0x6c0 #define HPIPE_CFG_PRE_CURSOR_PRESET0_OFFSET 0 -#define HPIPE_CFG_PRE_CURSOR_PRESET0_MASK (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET0_OFFSET) +#define HPIPE_CFG_PRE_CURSOR_PRESET0_MASK \ + (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET0_OFFSET) #define HPIPE_CFG_POST_CURSOR_PRESET0_OFFSET 6 -#define HPIPE_CFG_POST_CURSOR_PRESET0_MASK (0x3f << HPIPE_CFG_POST_CURSOR_PRESET0_OFFSET) +#define HPIPE_CFG_POST_CURSOR_PRESET0_MASK \ + (0x3f << HPIPE_CFG_POST_CURSOR_PRESET0_OFFSET) #define HPIPE_LANE_PRESET_CFG7_REG 0x6c4 #define HPIPE_CFG_PRE_CURSOR_PRESET1_OFFSET 0 -#define HPIPE_CFG_PRE_CURSOR_PRESET1_MASK (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET1_OFFSET) +#define HPIPE_CFG_PRE_CURSOR_PRESET1_MASK \ + (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET1_OFFSET) #define HPIPE_CFG_POST_CURSOR_PRESET1_OFFSET 6 -#define HPIPE_CFG_POST_CURSOR_PRESET1_MASK (0x3f << HPIPE_CFG_POST_CURSOR_PRESET1_OFFSET) +#define HPIPE_CFG_POST_CURSOR_PRESET1_MASK \ + (0x3f << HPIPE_CFG_POST_CURSOR_PRESET1_OFFSET) #define HPIPE_LANE_PRESET_CFG8_REG 0x6c8 #define HPIPE_CFG_PRE_CURSOR_PRESET2_OFFSET 0 -#define HPIPE_CFG_PRE_CURSOR_PRESET2_MASK (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET2_OFFSET) +#define HPIPE_CFG_PRE_CURSOR_PRESET2_MASK \ + (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET2_OFFSET) #define HPIPE_CFG_POST_CURSOR_PRESET2_OFFSET 6 -#define HPIPE_CFG_POST_CURSOR_PRESET2_MASK (0x3f << HPIPE_CFG_POST_CURSOR_PRESET2_OFFSET) +#define HPIPE_CFG_POST_CURSOR_PRESET2_MASK \ + (0x3f << HPIPE_CFG_POST_CURSOR_PRESET2_OFFSET) #define HPIPE_LANE_PRESET_CFG9_REG 0x6cc #define HPIPE_CFG_PRE_CURSOR_PRESET3_OFFSET 0 -#define HPIPE_CFG_PRE_CURSOR_PRESET3_MASK (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET3_OFFSET) +#define HPIPE_CFG_PRE_CURSOR_PRESET3_MASK \ + (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET3_OFFSET) #define HPIPE_CFG_POST_CURSOR_PRESET3_OFFSET 6 -#define HPIPE_CFG_POST_CURSOR_PRESET3_MASK (0x3f << HPIPE_CFG_POST_CURSOR_PRESET3_OFFSET) +#define HPIPE_CFG_POST_CURSOR_PRESET3_MASK \ + (0x3f << HPIPE_CFG_POST_CURSOR_PRESET3_OFFSET) #define HPIPE_LANE_PRESET_CFG10_REG 0x6d0 #define HPIPE_CFG_PRE_CURSOR_PRESET4_OFFSET 0 -#define HPIPE_CFG_PRE_CURSOR_PRESET4_MASK (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET4_OFFSET) +#define HPIPE_CFG_PRE_CURSOR_PRESET4_MASK \ + (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET4_OFFSET) #define HPIPE_CFG_POST_CURSOR_PRESET4_OFFSET 6 -#define HPIPE_CFG_POST_CURSOR_PRESET4_MASK (0x3f << HPIPE_CFG_POST_CURSOR_PRESET4_OFFSET) +#define HPIPE_CFG_POST_CURSOR_PRESET4_MASK \ + (0x3f << HPIPE_CFG_POST_CURSOR_PRESET4_OFFSET) #define HPIPE_LANE_PRESET_CFG11_REG 0x6d4 #define HPIPE_CFG_PRE_CURSOR_PRESET5_OFFSET 0 -#define HPIPE_CFG_PRE_CURSOR_PRESET5_MASK (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET5_OFFSET) +#define HPIPE_CFG_PRE_CURSOR_PRESET5_MASK \ + (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET5_OFFSET) #define HPIPE_CFG_POST_CURSOR_PRESET5_OFFSET 6 -#define HPIPE_CFG_POST_CURSOR_PRESET5_MASK (0x3f << HPIPE_CFG_POST_CURSOR_PRESET5_OFFSET) +#define HPIPE_CFG_POST_CURSOR_PRESET5_MASK \ + (0x3f << HPIPE_CFG_POST_CURSOR_PRESET5_OFFSET) #define HPIPE_LANE_PRESET_CFG12_REG 0x6d8 #define HPIPE_CFG_PRE_CURSOR_PRESET6_OFFSET 0 -#define HPIPE_CFG_PRE_CURSOR_PRESET6_MASK (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET6_OFFSET) +#define HPIPE_CFG_PRE_CURSOR_PRESET6_MASK \ + (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET6_OFFSET) #define HPIPE_CFG_POST_CURSOR_PRESET6_OFFSET 6 -#define HPIPE_CFG_POST_CURSOR_PRESET6_MASK (0x3f << HPIPE_CFG_POST_CURSOR_PRESET6_OFFSET) +#define HPIPE_CFG_POST_CURSOR_PRESET6_MASK \ + (0x3f << HPIPE_CFG_POST_CURSOR_PRESET6_OFFSET) #define HPIPE_LANE_PRESET_CFG13_REG 0x6dc #define HPIPE_CFG_PRE_CURSOR_PRESET7_OFFSET 0 -#define HPIPE_CFG_PRE_CURSOR_PRESET7_MASK (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET7_OFFSET) +#define HPIPE_CFG_PRE_CURSOR_PRESET7_MASK \ + (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET7_OFFSET) #define HPIPE_CFG_POST_CURSOR_PRESET7_OFFSET 6 -#define HPIPE_CFG_POST_CURSOR_PRESET7_MASK (0x3f << HPIPE_CFG_POST_CURSOR_PRESET7_OFFSET) +#define HPIPE_CFG_POST_CURSOR_PRESET7_MASK \ + (0x3f << HPIPE_CFG_POST_CURSOR_PRESET7_OFFSET) #define HPIPE_LANE_PRESET_CFG14_REG 0x6e0 #define HPIPE_CFG_PRE_CURSOR_PRESET8_OFFSET 0 -#define HPIPE_CFG_PRE_CURSOR_PRESET8_MASK (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET8_OFFSET) +#define HPIPE_CFG_PRE_CURSOR_PRESET8_MASK \ + (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET8_OFFSET) #define HPIPE_CFG_POST_CURSOR_PRESET8_OFFSET 6 -#define HPIPE_CFG_POST_CURSOR_PRESET8_MASK (0x3f << HPIPE_CFG_POST_CURSOR_PRESET8_OFFSET) +#define HPIPE_CFG_POST_CURSOR_PRESET8_MASK \ + (0x3f << HPIPE_CFG_POST_CURSOR_PRESET8_OFFSET) #define HPIPE_LANE_PRESET_CFG15_REG 0x6e4 #define HPIPE_CFG_PRE_CURSOR_PRESET9_OFFSET 0 -#define HPIPE_CFG_PRE_CURSOR_PRESET9_MASK (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET9_OFFSET) +#define HPIPE_CFG_PRE_CURSOR_PRESET9_MASK \ + (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET9_OFFSET) #define HPIPE_CFG_POST_CURSOR_PRESET9_OFFSET 6 -#define HPIPE_CFG_POST_CURSOR_PRESET9_MASK (0x3f << HPIPE_CFG_POST_CURSOR_PRESET9_OFFSET) +#define HPIPE_CFG_POST_CURSOR_PRESET9_MASK \ + (0x3f << HPIPE_CFG_POST_CURSOR_PRESET9_OFFSET) #define HPIPE_LANE_PRESET_CFG16_REG 0x6e8 #define HPIPE_CFG_PRE_CURSOR_PRESET10_OFFSET 0 -#define HPIPE_CFG_PRE_CURSOR_PRESET10_MASK (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET10_OFFSET) +#define HPIPE_CFG_PRE_CURSOR_PRESET10_MASK \ + (0x3f << HPIPE_CFG_PRE_CURSOR_PRESET10_OFFSET) #define HPIPE_CFG_POST_CURSOR_PRESET10_OFFSET 6 -#define HPIPE_CFG_POST_CURSOR_PRESET10_MASK (0x3f << HPIPE_CFG_POST_CURSOR_PRESET10_OFFSET) +#define HPIPE_CFG_POST_CURSOR_PRESET10_MASK \ + (0x3f << HPIPE_CFG_POST_CURSOR_PRESET10_OFFSET) #define HPIPE_LANE_EQ_REMOTE_SETTING_REG 0x6f8 #define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET 0 -#define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK (0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET) +#define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK \ + (0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET) #define HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET 1 -#define HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK (0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET) +#define HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK \ + (0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET) #define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET 2 -#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK (0xf << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET) +#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK \ + (0xf << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET) #define HPIPE_RST_CLK_CTRL_REG 0x704 #define HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET 0 -#define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK (0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET) +#define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK \ + (0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET) #define HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET 2 -#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK (0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET) +#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK \ + (0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET) #define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET 3 -#define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK (0x1 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET) +#define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK \ + (0x1 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET) #define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET 9 -#define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK (0x1 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET) +#define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK \ + (0x1 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET) -#define HPIPE_CLK_SRC_LO_REG 0x70c +#define HPIPE_CLK_SRC_LO_REG 0x70c #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET 1 -#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK (0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET) +#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK \ + (0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET) #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET 2 -#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK (0x3 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET) -#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET 5 -#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK (0x7 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET) +#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK \ + (0x3 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET) +#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET 5 +#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK \ + (0x7 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET) #define HPIPE_CLK_SRC_HI_REG 0x710 #define HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET 0 -#define HPIPE_CLK_SRC_HI_LANE_STRT_MASK (0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET) +#define HPIPE_CLK_SRC_HI_LANE_STRT_MASK \ + (0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET) #define HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET 1 -#define HPIPE_CLK_SRC_HI_LANE_BREAK_MASK (0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET) +#define HPIPE_CLK_SRC_HI_LANE_BREAK_MASK \ + (0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET) #define HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET 2 -#define HPIPE_CLK_SRC_HI_LANE_MASTER_MASK (0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET) +#define HPIPE_CLK_SRC_HI_LANE_MASTER_MASK \ + (0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET) #define HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET 7 -#define HPIPE_CLK_SRC_HI_MODE_PIPE_MASK (0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET) +#define HPIPE_CLK_SRC_HI_MODE_PIPE_MASK \ + (0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET) -#define HPIPE_GLOBAL_PM_CTRL 0x740 +#define HPIPE_GLOBAL_PM_CTRL 0x740 #define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET 0 -#define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK (0xFF << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET) +#define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK \ + (0xFF << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET) #endif /* _COMPHY_H_ */ diff --git a/drivers/marvell/comphy/comphy-cp110.h b/drivers/marvell/comphy/comphy-cp110.h index df9a6e65..6aa088ab 100644 --- a/drivers/marvell/comphy/comphy-cp110.h +++ b/drivers/marvell/comphy/comphy-cp110.h @@ -5,6 +5,8 @@ * https://spdx.org/licenses */ +/* Marvell CP110 SoC COMPHY unit driver */ + #ifndef _PHY_COMPHY_CP110_H #define _PHY_COMPHY_CP110_H @@ -18,23 +20,30 @@ /* Comphy registers */ #define COMMON_PHY_CFG1_REG 0x0 #define COMMON_PHY_CFG1_PWR_UP_OFFSET 1 -#define COMMON_PHY_CFG1_PWR_UP_MASK (0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET) +#define COMMON_PHY_CFG1_PWR_UP_MASK \ + (0x1 << COMMON_PHY_CFG1_PWR_UP_OFFSET) #define COMMON_PHY_CFG1_PIPE_SELECT_OFFSET 2 -#define COMMON_PHY_CFG1_PIPE_SELECT_MASK (0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET) +#define COMMON_PHY_CFG1_PIPE_SELECT_MASK \ + (0x1 << COMMON_PHY_CFG1_PIPE_SELECT_OFFSET) #define COMMON_PHY_CFG1_CORE_RSTN_OFFSET 13 -#define COMMON_PHY_CFG1_CORE_RSTN_MASK (0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET) +#define COMMON_PHY_CFG1_CORE_RSTN_MASK \ + (0x1 << COMMON_PHY_CFG1_CORE_RSTN_OFFSET) #define COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET 14 -#define COMMON_PHY_CFG1_PWR_ON_RESET_MASK (0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET) +#define COMMON_PHY_CFG1_PWR_ON_RESET_MASK \ + (0x1 << COMMON_PHY_CFG1_PWR_ON_RESET_OFFSET) #define COMMON_PHY_PHY_MODE_OFFSET 15 -#define COMMON_PHY_PHY_MODE_MASK (0x1 << COMMON_PHY_PHY_MODE_OFFSET) +#define COMMON_PHY_PHY_MODE_MASK \ + (0x1 << COMMON_PHY_PHY_MODE_OFFSET) #define COMMON_PHY_CFG6_REG 0x14 #define COMMON_PHY_CFG6_IF_40_SEL_OFFSET 18 -#define COMMON_PHY_CFG6_IF_40_SEL_MASK (0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET) +#define COMMON_PHY_CFG6_IF_40_SEL_MASK \ + (0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET) #define COMMON_PHY_CFG6_REG 0x14 #define COMMON_PHY_CFG6_IF_40_SEL_OFFSET 18 -#define COMMON_PHY_CFG6_IF_40_SEL_MASK (0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET) +#define COMMON_PHY_CFG6_IF_40_SEL_MASK \ + (0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET) #define COMMON_SELECTOR_PHY_REG_OFFSET 0x140 #define COMMON_SELECTOR_PIPE_REG_OFFSET 0x144 @@ -62,65 +71,87 @@ #define COMMON_PHY_SD_CTRL1_COMPHY_0_3_PORT_MASK 0xFFFF #define COMMON_PHY_SD_CTRL1_COMPHY_0_1_PORT_MASK 0xFF #define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET 24 -#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET) +#define COMMON_PHY_SD_CTRL1_PCIE_X4_EN_MASK \ + (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X4_EN_OFFSET) #define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET 25 -#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET) +#define COMMON_PHY_SD_CTRL1_PCIE_X2_EN_MASK \ + (0x1 << COMMON_PHY_SD_CTRL1_PCIE_X2_EN_OFFSET) #define COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET 26 -#define COMMON_PHY_SD_CTRL1_RXAUI1_MASK (0x1 << COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET) +#define COMMON_PHY_SD_CTRL1_RXAUI1_MASK \ + (0x1 << COMMON_PHY_SD_CTRL1_RXAUI1_OFFSET) #define COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET 27 -#define COMMON_PHY_SD_CTRL1_RXAUI0_MASK (0x1 << COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET) +#define COMMON_PHY_SD_CTRL1_RXAUI0_MASK \ + (0x1 << COMMON_PHY_SD_CTRL1_RXAUI0_OFFSET) /* DFX register */ #define DFX_BASE (0x400000) #define DFX_DEV_GEN_CTRL12_REG (0x280) #define DFX_DEV_GEN_PCIE_CLK_SRC_MUX (0x3) #define DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET 7 -#define DFX_DEV_GEN_PCIE_CLK_SRC_MASK (0x3 << DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET) +#define DFX_DEV_GEN_PCIE_CLK_SRC_MASK \ + (0x3 << DFX_DEV_GEN_PCIE_CLK_SRC_OFFSET) /* SerDes IP registers */ #define SD_EXTERNAL_CONFIG0_REG 0 #define SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET 1 -#define SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK (1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET) +#define SD_EXTERNAL_CONFIG0_SD_PU_PLL_MASK \ + (1 << SD_EXTERNAL_CONFIG0_SD_PU_PLL_OFFSET) #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET 3 -#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET) +#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_MASK \ + (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_RX_OFFSET) #define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET 7 -#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET) +#define SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_MASK \ + (0xf << SD_EXTERNAL_CONFIG0_SD_PHY_GEN_TX_OFFSET) #define SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET 11 -#define SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK (1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET) +#define SD_EXTERNAL_CONFIG0_SD_PU_RX_MASK \ + (1 << SD_EXTERNAL_CONFIG0_SD_PU_RX_OFFSET) #define SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET 12 -#define SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK (1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET) +#define SD_EXTERNAL_CONFIG0_SD_PU_TX_MASK \ + (1 << SD_EXTERNAL_CONFIG0_SD_PU_TX_OFFSET) #define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET 14 -#define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK (1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET) +#define SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_MASK \ + (1 << SD_EXTERNAL_CONFIG0_HALF_BUS_MODE_OFFSET) #define SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET 15 -#define SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK (0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET) +#define SD_EXTERNAL_CONFIG0_MEDIA_MODE_MASK \ + (0x1 << SD_EXTERNAL_CONFIG0_MEDIA_MODE_OFFSET) #define SD_EXTERNAL_CONFIG1_REG 0x4 #define SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET 3 -#define SD_EXTERNAL_CONFIG1_RESET_IN_MASK (0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET) +#define SD_EXTERNAL_CONFIG1_RESET_IN_MASK \ + (0x1 << SD_EXTERNAL_CONFIG1_RESET_IN_OFFSET) #define SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET 4 -#define SD_EXTERNAL_CONFIG1_RX_INIT_MASK (0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET) +#define SD_EXTERNAL_CONFIG1_RX_INIT_MASK \ + (0x1 << SD_EXTERNAL_CONFIG1_RX_INIT_OFFSET) #define SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET 5 -#define SD_EXTERNAL_CONFIG1_RESET_CORE_MASK (0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET) +#define SD_EXTERNAL_CONFIG1_RESET_CORE_MASK \ + (0x1 << SD_EXTERNAL_CONFIG1_RESET_CORE_OFFSET) #define SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET 6 -#define SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK (0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET) +#define SD_EXTERNAL_CONFIG1_RF_RESET_IN_MASK \ + (0x1 << SD_EXTERNAL_CONFIG1_RF_RESET_IN_OFFSET) #define SD_EXTERNAL_CONFIG2_REG 0x8 #define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET 4 -#define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK (0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET) +#define SD_EXTERNAL_CONFIG2_PIN_DFE_EN_MASK \ + (0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET) #define SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET 7 -#define SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK (0x1 << SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET) +#define SD_EXTERNAL_CONFIG2_SSC_ENABLE_MASK \ + (0x1 << SD_EXTERNAL_CONFIG2_SSC_ENABLE_OFFSET) #define SD_EXTERNAL_STATUS_REG 0xc #define SD_EXTERNAL_STATUS_START_RX_TRAINING_OFFSET 7 -#define SD_EXTERNAL_STATUS_START_RX_TRAINING_MASK (1 << SD_EXTERNAL_STATUS_START_RX_TRAINING_OFFSET) +#define SD_EXTERNAL_STATUS_START_RX_TRAINING_MASK \ + (1 << SD_EXTERNAL_STATUS_START_RX_TRAINING_OFFSET) #define SD_EXTERNAL_STATUS0_REG 0x18 #define SD_EXTERNAL_STATUS0_PLL_TX_OFFSET 2 -#define SD_EXTERNAL_STATUS0_PLL_TX_MASK (0x1 << SD_EXTERNAL_STATUS0_PLL_TX_OFFSET) +#define SD_EXTERNAL_STATUS0_PLL_TX_MASK \ + (0x1 << SD_EXTERNAL_STATUS0_PLL_TX_OFFSET) #define SD_EXTERNAL_STATUS0_PLL_RX_OFFSET 3 -#define SD_EXTERNAL_STATUS0_PLL_RX_MASK (0x1 << SD_EXTERNAL_STATUS0_PLL_RX_OFFSET) +#define SD_EXTERNAL_STATUS0_PLL_RX_MASK \ + (0x1 << SD_EXTERNAL_STATUS0_PLL_RX_OFFSET) #define SD_EXTERNAL_STATUS0_RX_INIT_OFFSET 4 -#define SD_EXTERNAL_STATUS0_RX_INIT_MASK (0x1 << SD_EXTERNAL_STATUS0_RX_INIT_OFFSET) +#define SD_EXTERNAL_STATUS0_RX_INIT_MASK \ + (0x1 << SD_EXTERNAL_STATUS0_RX_INIT_OFFSET) #define SD_EXTERNAL_STATAUS1_REG 0x1c #define SD_EXTERNAL_STATAUS1_REG_RX_TRAIN_COMP_OFFSET 0 @@ -133,31 +164,40 @@ /* HPIPE registers */ #define HPIPE_PWR_PLL_REG 0x4 #define HPIPE_PWR_PLL_REF_FREQ_OFFSET 0 -#define HPIPE_PWR_PLL_REF_FREQ_MASK (0x1f << HPIPE_PWR_PLL_REF_FREQ_OFFSET) +#define HPIPE_PWR_PLL_REF_FREQ_MASK \ + (0x1f << HPIPE_PWR_PLL_REF_FREQ_OFFSET) #define HPIPE_PWR_PLL_PHY_MODE_OFFSET 5 -#define HPIPE_PWR_PLL_PHY_MODE_MASK (0x7 << HPIPE_PWR_PLL_PHY_MODE_OFFSET) +#define HPIPE_PWR_PLL_PHY_MODE_MASK \ + (0x7 << HPIPE_PWR_PLL_PHY_MODE_OFFSET) #define HPIPE_CAL_REG1_REG 0xc #define HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET 10 -#define HPIPE_CAL_REG_1_EXT_TXIMP_MASK (0x1f << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET) +#define HPIPE_CAL_REG_1_EXT_TXIMP_MASK \ + (0x1f << HPIPE_CAL_REG_1_EXT_TXIMP_OFFSET) #define HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET 15 -#define HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK (0x1 << HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET) +#define HPIPE_CAL_REG_1_EXT_TXIMP_EN_MASK \ + (0x1 << HPIPE_CAL_REG_1_EXT_TXIMP_EN_OFFSET) -#define HPIPE_SQUELCH_FFE_SETTING_REG 0x18 +#define HPIPE_SQUELCH_FFE_SETTING_REG 0x18 #define HPIPE_SQUELCH_THRESH_IN_OFFSET 8 -#define HPIPE_SQUELCH_THRESH_IN_MASK (0xf << HPIPE_SQUELCH_THRESH_IN_OFFSET) +#define HPIPE_SQUELCH_THRESH_IN_MASK \ + (0xf << HPIPE_SQUELCH_THRESH_IN_OFFSET) #define HPIPE_SQUELCH_DETECTED_OFFSET 14 -#define HPIPE_SQUELCH_DETECTED_MASK (0x1 << HPIPE_SQUELCH_DETECTED_OFFSET) +#define HPIPE_SQUELCH_DETECTED_MASK \ + (0x1 << HPIPE_SQUELCH_DETECTED_OFFSET) #define HPIPE_DFE_REG0 0x1c #define HPIPE_DFE_RES_FORCE_OFFSET 15 -#define HPIPE_DFE_RES_FORCE_MASK (0x1 << HPIPE_DFE_RES_FORCE_OFFSET) +#define HPIPE_DFE_RES_FORCE_MASK \ + (0x1 << HPIPE_DFE_RES_FORCE_OFFSET) #define HPIPE_DFE_F3_F5_REG 0x28 #define HPIPE_DFE_F3_F5_DFE_EN_OFFSET 14 -#define HPIPE_DFE_F3_F5_DFE_EN_MASK (0x1 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET) +#define HPIPE_DFE_F3_F5_DFE_EN_MASK \ + (0x1 << HPIPE_DFE_F3_F5_DFE_EN_OFFSET) #define HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET 15 -#define HPIPE_DFE_F3_F5_DFE_CTRL_MASK (0x1 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET) +#define HPIPE_DFE_F3_F5_DFE_CTRL_MASK \ + (0x1 << HPIPE_DFE_F3_F5_DFE_CTRL_OFFSET) #define HPIPE_ADAPTED_DFE_COEFFICIENT_1_REG 0x30 #define HPIPE_ADAPTED_DFE_RES_OFFSET 13 @@ -165,37 +205,50 @@ #define HPIPE_G1_SET_0_REG 0x34 #define HPIPE_G1_SET_0_G1_TX_AMP_OFFSET 1 -#define HPIPE_G1_SET_0_G1_TX_AMP_MASK (0x1f << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET) +#define HPIPE_G1_SET_0_G1_TX_AMP_MASK \ + (0x1f << HPIPE_G1_SET_0_G1_TX_AMP_OFFSET) #define HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET 6 -#define HPIPE_G1_SET_0_G1_TX_AMP_ADJ_MASK (0x1 << HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET) +#define HPIPE_G1_SET_0_G1_TX_AMP_ADJ_MASK \ + (0x1 << HPIPE_G1_SET_0_G1_TX_AMP_ADJ_OFFSET) #define HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET 7 -#define HPIPE_G1_SET_0_G1_TX_EMPH1_MASK (0xf << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET) +#define HPIPE_G1_SET_0_G1_TX_EMPH1_MASK \ + (0xf << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET) #define HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET 11 -#define HPIPE_G1_SET_0_G1_TX_EMPH1_EN_MASK (0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET) +#define HPIPE_G1_SET_0_G1_TX_EMPH1_EN_MASK \ + (0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_EN_OFFSET) #define HPIPE_G1_SET_1_REG 0x38 #define HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET 0 -#define HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET) +#define HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK \ + (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET) #define HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET 3 #define HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET) #define HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET 6 -#define HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK (0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET) +#define HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK \ + (0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET) #define HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET 8 -#define HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK (0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET) +#define HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK \ + (0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFF_OFFSET) #define HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET 10 -#define HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK (0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET) +#define HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK \ + (0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET) #define HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET 11 -#define HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK (0x3 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET) +#define HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_MASK \ + (0x3 << HPIPE_G1_SET_1_G1_RX_DIGCK_DIV_OFFSET) #define HPIPE_G2_SET_0_REG 0x3c #define HPIPE_G2_SET_0_G2_TX_AMP_OFFSET 1 -#define HPIPE_G2_SET_0_G2_TX_AMP_MASK (0x1f << HPIPE_G2_SET_0_G2_TX_AMP_OFFSET) +#define HPIPE_G2_SET_0_G2_TX_AMP_MASK \ + (0x1f << HPIPE_G2_SET_0_G2_TX_AMP_OFFSET) #define HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET 6 -#define HPIPE_G2_SET_0_G2_TX_AMP_ADJ_MASK (0x1 << HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET) +#define HPIPE_G2_SET_0_G2_TX_AMP_ADJ_MASK \ + (0x1 << HPIPE_G2_SET_0_G2_TX_AMP_ADJ_OFFSET) #define HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET 7 -#define HPIPE_G2_SET_0_G2_TX_EMPH1_MASK (0xf << HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET) +#define HPIPE_G2_SET_0_G2_TX_EMPH1_MASK \ + (0xf << HPIPE_G2_SET_0_G2_TX_EMPH1_OFFSET) #define HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET 11 -#define HPIPE_G2_SET_0_G2_TX_EMPH1_EN_MASK (0x1 << HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET) +#define HPIPE_G2_SET_0_G2_TX_EMPH1_EN_MASK \ + (0x1 << HPIPE_G2_SET_0_G2_TX_EMPH1_EN_OFFSET) #define HPIPE_G2_SET_1_REG 0x40 #define HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET 0 @@ -203,55 +256,76 @@ #define HPIPE_G2_SET_1_G2_RX_SELMUPF_OFFSET 3 #define HPIPE_G2_SET_1_G2_RX_SELMUPF_MASK (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPF_OFFSET) #define HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET 6 -#define HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET) +#define HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK \ + (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET) #define HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET 8 -#define HPIPE_G2_SET_1_G2_RX_SELMUFF_MASK (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET) +#define HPIPE_G2_SET_1_G2_RX_SELMUFF_MASK \ + (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFF_OFFSET) #define HPIPE_G2_SET_1_G2_RX_DFE_EN_OFFSET 10 -#define HPIPE_G2_SET_1_G2_RX_DFE_EN_MASK (0x1 << HPIPE_G2_SET_1_G2_RX_DFE_EN_OFFSET) +#define HPIPE_G2_SET_1_G2_RX_DFE_EN_MASK \ + (0x1 << HPIPE_G2_SET_1_G2_RX_DFE_EN_OFFSET) #define HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET 11 -#define HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_MASK (0x3 << HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET) +#define HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_MASK \ + (0x3 << HPIPE_G2_SET_1_G2_RX_DIGCK_DIV_OFFSET) #define HPIPE_G3_SET_0_REG 0x44 #define HPIPE_G3_SET_0_G3_TX_AMP_OFFSET 1 -#define HPIPE_G3_SET_0_G3_TX_AMP_MASK (0x1f << HPIPE_G3_SET_0_G3_TX_AMP_OFFSET) +#define HPIPE_G3_SET_0_G3_TX_AMP_MASK \ + (0x1f << HPIPE_G3_SET_0_G3_TX_AMP_OFFSET) #define HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET 6 -#define HPIPE_G3_SET_0_G3_TX_AMP_ADJ_MASK (0x1 << HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET) +#define HPIPE_G3_SET_0_G3_TX_AMP_ADJ_MASK \ + (0x1 << HPIPE_G3_SET_0_G3_TX_AMP_ADJ_OFFSET) #define HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET 7 -#define HPIPE_G3_SET_0_G3_TX_EMPH1_MASK (0xf << HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET) +#define HPIPE_G3_SET_0_G3_TX_EMPH1_MASK \ + (0xf << HPIPE_G3_SET_0_G3_TX_EMPH1_OFFSET) #define HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET 11 -#define HPIPE_G3_SET_0_G3_TX_EMPH1_EN_MASK (0x1 << HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET) +#define HPIPE_G3_SET_0_G3_TX_EMPH1_EN_MASK \ + (0x1 << HPIPE_G3_SET_0_G3_TX_EMPH1_EN_OFFSET) #define HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET 12 -#define HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_MASK (0x7 << HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET) +#define HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_MASK \ + (0x7 << HPIPE_G3_SET_0_G3_TX_SLEW_RATE_SEL_OFFSET) #define HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET 15 -#define HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_MASK (0x1 << HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET) +#define HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_MASK \ + (0x1 << HPIPE_G3_SET_0_G3_TX_SLEW_CTRL_EN_OFFSET) #define HPIPE_G3_SET_1_REG 0x48 #define HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET 0 -#define HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK (0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET) +#define HPIPE_G3_SET_1_G3_RX_SELMUPI_MASK \ + (0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPI_OFFSET) #define HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET 3 -#define HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK (0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET) +#define HPIPE_G3_SET_1_G3_RX_SELMUPF_MASK \ + (0x7 << HPIPE_G3_SET_1_G3_RX_SELMUPF_OFFSET) #define HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET 6 -#define HPIPE_G3_SET_1_G3_RX_SELMUFI_MASK (0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET) +#define HPIPE_G3_SET_1_G3_RX_SELMUFI_MASK \ + (0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFI_OFFSET) #define HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET 8 -#define HPIPE_G3_SET_1_G3_RX_SELMUFF_MASK (0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET) +#define HPIPE_G3_SET_1_G3_RX_SELMUFF_MASK \ + (0x3 << HPIPE_G3_SET_1_G3_RX_SELMUFF_OFFSET) #define HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET 10 -#define HPIPE_G3_SET_1_G3_RX_DFE_EN_MASK (0x1 << HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET) +#define HPIPE_G3_SET_1_G3_RX_DFE_EN_MASK \ + (0x1 << HPIPE_G3_SET_1_G3_RX_DFE_EN_OFFSET) #define HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET 11 -#define HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_MASK (0x3 << HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET) +#define HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_MASK \ + (0x3 << HPIPE_G3_SET_1_G3_RX_DIGCK_DIV_OFFSET) #define HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET 13 -#define HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK (0x1 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET) +#define HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_MASK \ + (0x1 << HPIPE_G3_SET_1_G3_SAMPLER_INPAIRX2_EN_OFFSET) #define HPIPE_PHY_TEST_CONTROL_REG 0x54 #define HPIPE_PHY_TEST_PATTERN_SEL_OFFSET 4 -#define HPIPE_PHY_TEST_PATTERN_SEL_MASK (0xf << HPIPE_PHY_TEST_PATTERN_SEL_OFFSET) +#define HPIPE_PHY_TEST_PATTERN_SEL_MASK \ + (0xf << HPIPE_PHY_TEST_PATTERN_SEL_OFFSET) #define HPIPE_PHY_TEST_RESET_OFFSET 14 -#define HPIPE_PHY_TEST_RESET_MASK (0x1 << HPIPE_PHY_TEST_RESET_OFFSET) +#define HPIPE_PHY_TEST_RESET_MASK \ + (0x1 << HPIPE_PHY_TEST_RESET_OFFSET) #define HPIPE_PHY_TEST_EN_OFFSET 15 -#define HPIPE_PHY_TEST_EN_MASK (0x1 << HPIPE_PHY_TEST_EN_OFFSET) +#define HPIPE_PHY_TEST_EN_MASK \ + (0x1 << HPIPE_PHY_TEST_EN_OFFSET) #define HPIPE_PHY_TEST_DATA_REG 0x6c #define HPIPE_PHY_TEST_DATA_OFFSET 0 -#define HPIPE_PHY_TEST_DATA_MASK (0xffff << HPIPE_PHY_TEST_DATA_OFFSET) +#define HPIPE_PHY_TEST_DATA_MASK \ + (0xffff << HPIPE_PHY_TEST_DATA_OFFSET) #define HPIPE_PHY_TEST_PRBS_ERROR_COUNTER_1_REG 0x80 @@ -263,25 +337,33 @@ #define HPIPE_LOOPBACK_REG 0x8c #define HPIPE_LOOPBACK_SEL_OFFSET 1 -#define HPIPE_LOOPBACK_SEL_MASK (0x7 << HPIPE_LOOPBACK_SEL_OFFSET) +#define HPIPE_LOOPBACK_SEL_MASK \ + (0x7 << HPIPE_LOOPBACK_SEL_OFFSET) #define HPIPE_CDR_LOCK_OFFSET 7 -#define HPIPE_CDR_LOCK_MASK (0x1 << HPIPE_CDR_LOCK_OFFSET) +#define HPIPE_CDR_LOCK_MASK \ + (0x1 << HPIPE_CDR_LOCK_OFFSET) #define HPIPE_CDR_LOCK_DET_EN_OFFSET 8 -#define HPIPE_CDR_LOCK_DET_EN_MASK (0x1 << HPIPE_CDR_LOCK_DET_EN_OFFSET) +#define HPIPE_CDR_LOCK_DET_EN_MASK \ + (0x1 << HPIPE_CDR_LOCK_DET_EN_OFFSET) #define HPIPE_INTERFACE_REG 0x94 #define HPIPE_INTERFACE_GEN_MAX_OFFSET 10 -#define HPIPE_INTERFACE_GEN_MAX_MASK (0x3 << HPIPE_INTERFACE_GEN_MAX_OFFSET) +#define HPIPE_INTERFACE_GEN_MAX_MASK \ + (0x3 << HPIPE_INTERFACE_GEN_MAX_OFFSET) #define HPIPE_INTERFACE_DET_BYPASS_OFFSET 12 -#define HPIPE_INTERFACE_DET_BYPASS_MASK (0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET) +#define HPIPE_INTERFACE_DET_BYPASS_MASK \ + (0x1 << HPIPE_INTERFACE_DET_BYPASS_OFFSET) #define HPIPE_INTERFACE_LINK_TRAIN_OFFSET 14 -#define HPIPE_INTERFACE_LINK_TRAIN_MASK (0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET) +#define HPIPE_INTERFACE_LINK_TRAIN_MASK \ + (0x1 << HPIPE_INTERFACE_LINK_TRAIN_OFFSET) #define HPIPE_G1_SET_2_REG 0xf4 #define HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET 0 -#define HPIPE_G1_SET_2_G1_TX_EMPH0_MASK (0xf << HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET) +#define HPIPE_G1_SET_2_G1_TX_EMPH0_MASK \ + (0xf << HPIPE_G1_SET_2_G1_TX_EMPH0_OFFSET) #define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET 4 -#define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_MASK (0x1 << HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET) +#define HPIPE_G1_SET_2_G1_TX_EMPH0_EN_MASK \ + (0x1 << HPIPE_G1_SET_2_G1_TX_EMPH0_EN_OFFSET) #define HPIPE_G2_SET_2_REG 0xf8 #define HPIPE_G2_SET_2_G2_TX_EMPH0_OFFSET 0 @@ -289,7 +371,8 @@ #define HPIPE_G2_SET_2_G2_TX_EMPH0_EN_OFFSET 4 #define HPIPE_G2_SET_2_G2_TX_EMPH0_EN_MASK (0x1 << HPIPE_G2_SET_2_G2_TX_EMPH0_EN_OFFSET) #define HPIPE_G2_TX_SSC_AMP_OFFSET 9 -#define HPIPE_G2_TX_SSC_AMP_MASK (0x7f << HPIPE_G2_TX_SSC_AMP_OFFSET) +#define HPIPE_G2_TX_SSC_AMP_MASK \ + (0x7f << HPIPE_G2_TX_SSC_AMP_OFFSET) #define HPIPE_G3_SET_2_REG 0xfc #define HPIPE_G3_SET_2_G3_TX_EMPH0_OFFSET 0 @@ -301,57 +384,76 @@ #define HPIPE_VDD_CAL_0_REG 0x108 #define HPIPE_CAL_VDD_CONT_MODE_OFFSET 15 -#define HPIPE_CAL_VDD_CONT_MODE_MASK (0x1 << HPIPE_CAL_VDD_CONT_MODE_OFFSET) +#define HPIPE_CAL_VDD_CONT_MODE_MASK \ + (0x1 << HPIPE_CAL_VDD_CONT_MODE_OFFSET) #define HPIPE_VDD_CAL_CTRL_REG 0x114 #define HPIPE_EXT_SELLV_RXSAMPL_OFFSET 5 -#define HPIPE_EXT_SELLV_RXSAMPL_MASK (0x1f << HPIPE_EXT_SELLV_RXSAMPL_OFFSET) +#define HPIPE_EXT_SELLV_RXSAMPL_MASK \ + (0x1f << HPIPE_EXT_SELLV_RXSAMPL_OFFSET) -#define HPIPE_PCIE_REG0 0x120 +#define HPIPE_PCIE_REG0 0x120 #define HPIPE_PCIE_IDLE_SYNC_OFFSET 12 -#define HPIPE_PCIE_IDLE_SYNC_MASK (0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET) +#define HPIPE_PCIE_IDLE_SYNC_MASK \ + (0x1 << HPIPE_PCIE_IDLE_SYNC_OFFSET) #define HPIPE_PCIE_SEL_BITS_OFFSET 13 -#define HPIPE_PCIE_SEL_BITS_MASK (0x3 << HPIPE_PCIE_SEL_BITS_OFFSET) +#define HPIPE_PCIE_SEL_BITS_MASK \ + (0x3 << HPIPE_PCIE_SEL_BITS_OFFSET) #define HPIPE_LANE_ALIGN_REG 0x124 #define HPIPE_LANE_ALIGN_OFF_OFFSET 12 -#define HPIPE_LANE_ALIGN_OFF_MASK (0x1 << HPIPE_LANE_ALIGN_OFF_OFFSET) +#define HPIPE_LANE_ALIGN_OFF_MASK \ + (0x1 << HPIPE_LANE_ALIGN_OFF_OFFSET) #define HPIPE_MISC_REG 0x13C #define HPIPE_MISC_CLK100M_125M_OFFSET 4 -#define HPIPE_MISC_CLK100M_125M_MASK (0x1 << HPIPE_MISC_CLK100M_125M_OFFSET) +#define HPIPE_MISC_CLK100M_125M_MASK \ + (0x1 << HPIPE_MISC_CLK100M_125M_OFFSET) #define HPIPE_MISC_ICP_FORCE_OFFSET 5 -#define HPIPE_MISC_ICP_FORCE_MASK (0x1 << HPIPE_MISC_ICP_FORCE_OFFSET) +#define HPIPE_MISC_ICP_FORCE_MASK \ + (0x1 << HPIPE_MISC_ICP_FORCE_OFFSET) #define HPIPE_MISC_TXDCLK_2X_OFFSET 6 -#define HPIPE_MISC_TXDCLK_2X_MASK (0x1 << HPIPE_MISC_TXDCLK_2X_OFFSET) +#define HPIPE_MISC_TXDCLK_2X_MASK \ + (0x1 << HPIPE_MISC_TXDCLK_2X_OFFSET) #define HPIPE_MISC_CLK500_EN_OFFSET 7 -#define HPIPE_MISC_CLK500_EN_MASK (0x1 << HPIPE_MISC_CLK500_EN_OFFSET) +#define HPIPE_MISC_CLK500_EN_MASK \ + (0x1 << HPIPE_MISC_CLK500_EN_OFFSET) #define HPIPE_MISC_REFCLK_SEL_OFFSET 10 -#define HPIPE_MISC_REFCLK_SEL_MASK (0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET) +#define HPIPE_MISC_REFCLK_SEL_MASK \ + (0x1 << HPIPE_MISC_REFCLK_SEL_OFFSET) #define HPIPE_RX_CONTROL_1_REG 0x140 #define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET 11 -#define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK (0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET) +#define HPIPE_RX_CONTROL_1_RXCLK2X_SEL_MASK \ + (0x1 << HPIPE_RX_CONTROL_1_RXCLK2X_SEL_OFFSET) #define HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET 12 -#define HPIPE_RX_CONTROL_1_CLK8T_EN_MASK (0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET) +#define HPIPE_RX_CONTROL_1_CLK8T_EN_MASK \ + (0x1 << HPIPE_RX_CONTROL_1_CLK8T_EN_OFFSET) #define HPIPE_PWR_CTR_REG 0x148 #define HPIPE_PWR_CTR_RST_DFE_OFFSET 0 -#define HPIPE_PWR_CTR_RST_DFE_MASK (0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET) +#define HPIPE_PWR_CTR_RST_DFE_MASK \ + (0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET) #define HPIPE_PWR_CTR_SFT_RST_OFFSET 10 -#define HPIPE_PWR_CTR_SFT_RST_MASK (0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET) +#define HPIPE_PWR_CTR_SFT_RST_MASK \ + (0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET) #define HPIPE_SPD_DIV_FORCE_REG 0x154 #define HPIPE_TXDIGCK_DIV_FORCE_OFFSET 7 -#define HPIPE_TXDIGCK_DIV_FORCE_MASK (0x1 << HPIPE_TXDIGCK_DIV_FORCE_OFFSET) +#define HPIPE_TXDIGCK_DIV_FORCE_MASK \ + (0x1 << HPIPE_TXDIGCK_DIV_FORCE_OFFSET) #define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET 8 -#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK (0x3 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET) +#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_MASK \ + (0x3 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_OFFSET) #define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET 10 -#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_MASK (0x1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET) +#define HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_MASK \ + (0x1 << HPIPE_SPD_DIV_FORCE_RX_SPD_DIV_FORCE_OFFSET) #define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET 13 -#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_MASK (0x3 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET) +#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_MASK \ + (0x3 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_OFFSET) #define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET 15 -#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_MASK (0x1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET) +#define HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_MASK \ + (0x1 << HPIPE_SPD_DIV_FORCE_TX_SPD_DIV_FORCE_OFFSET) /* HPIPE_RX_CLK_ALIGN90_AND_TX_IDLE_CALIBRATION_CTRL_REG */ #define HPIPE_RX_CLK_ALIGN90_AND_TX_IDLE_CALIB_CTRL_REG 0x168 @@ -362,39 +464,53 @@ #define HPIPE_SAMPLER_N_PROC_CALIB_CTRL_REG 0x16C #define HPIPE_RX_SAMPLER_OS_GAIN_OFFSET 6 -#define HPIPE_RX_SAMPLER_OS_GAIN_MASK (0x3 << HPIPE_RX_SAMPLER_OS_GAIN_OFFSET) +#define HPIPE_RX_SAMPLER_OS_GAIN_MASK \ + (0x3 << HPIPE_RX_SAMPLER_OS_GAIN_OFFSET) #define HPIPE_SMAPLER_OFFSET 12 -#define HPIPE_SMAPLER_MASK (0x1 << HPIPE_SMAPLER_OFFSET) +#define HPIPE_SMAPLER_MASK \ + (0x1 << HPIPE_SMAPLER_OFFSET) #define HPIPE_TX_REG1_REG 0x174 #define HPIPE_TX_REG1_TX_EMPH_RES_OFFSET 5 -#define HPIPE_TX_REG1_TX_EMPH_RES_MASK (0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET) +#define HPIPE_TX_REG1_TX_EMPH_RES_MASK \ + (0x3 << HPIPE_TX_REG1_TX_EMPH_RES_OFFSET) #define HPIPE_TX_REG1_SLC_EN_OFFSET 10 -#define HPIPE_TX_REG1_SLC_EN_MASK (0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET) +#define HPIPE_TX_REG1_SLC_EN_MASK \ + (0x3f << HPIPE_TX_REG1_SLC_EN_OFFSET) #define HPIPE_PWR_CTR_DTL_REG 0x184 #define HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET 0 -#define HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK (0x1 << HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET) +#define HPIPE_PWR_CTR_DTL_SQ_DET_EN_MASK \ + (0x1 << HPIPE_PWR_CTR_DTL_SQ_DET_EN_OFFSET) #define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET 1 -#define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK (0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET) +#define HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_MASK \ + (0x1 << HPIPE_PWR_CTR_DTL_SQ_PLOOP_EN_OFFSET) #define HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET 2 -#define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK (0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET) +#define HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK \ + (0x1 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET) #define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET 4 -#define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK (0x7 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET) +#define HPIPE_PWR_CTR_DTL_CLAMPING_SEL_MASK \ + (0x7 << HPIPE_PWR_CTR_DTL_CLAMPING_SEL_OFFSET) #define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET 10 -#define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK (0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET) +#define HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_MASK \ + (0x1 << HPIPE_PWR_CTR_DTL_INTPCLK_DIV_FORCE_OFFSET) #define HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET 12 -#define HPIPE_PWR_CTR_DTL_CLK_MODE_MASK (0x3 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET) +#define HPIPE_PWR_CTR_DTL_CLK_MODE_MASK \ + (0x3 << HPIPE_PWR_CTR_DTL_CLK_MODE_OFFSET) #define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET 14 -#define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK (1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET) +#define HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_MASK \ + (1 << HPIPE_PWR_CTR_DTL_CLK_MODE_FORCE_OFFSET) #define HPIPE_PHASE_CONTROL_REG 0x188 #define HPIPE_OS_PH_OFFSET_OFFSET 0 -#define HPIPE_OS_PH_OFFSET_MASK (0x7f << HPIPE_OS_PH_OFFSET_OFFSET) +#define HPIPE_OS_PH_OFFSET_MASK \ + (0x7f << HPIPE_OS_PH_OFFSET_OFFSET) #define HPIPE_OS_PH_OFFSET_FORCE_OFFSET 7 -#define HPIPE_OS_PH_OFFSET_FORCE_MASK (0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET) +#define HPIPE_OS_PH_OFFSET_FORCE_MASK \ + (0x1 << HPIPE_OS_PH_OFFSET_FORCE_OFFSET) #define HPIPE_OS_PH_VALID_OFFSET 8 -#define HPIPE_OS_PH_VALID_MASK (0x1 << HPIPE_OS_PH_VALID_OFFSET) +#define HPIPE_OS_PH_VALID_MASK \ + (0x1 << HPIPE_OS_PH_VALID_OFFSET) #define HPIPE_DATA_PHASE_OFF_CTRL_REG 0x1A0 #define HPIPE_DATA_PHASE_ADAPTED_OS_PH_OFFSET 9 @@ -408,23 +524,29 @@ #define HPIPE_SQ_GLITCH_FILTER_CTRL 0x1c8 #define HPIPE_SQ_DEGLITCH_WIDTH_P_OFFSET 0 -#define HPIPE_SQ_DEGLITCH_WIDTH_P_MASK (0xf << HPIPE_SQ_DEGLITCH_WIDTH_P_OFFSET) +#define HPIPE_SQ_DEGLITCH_WIDTH_P_MASK \ + (0xf << HPIPE_SQ_DEGLITCH_WIDTH_P_OFFSET) #define HPIPE_SQ_DEGLITCH_WIDTH_N_OFFSET 4 -#define HPIPE_SQ_DEGLITCH_WIDTH_N_MASK (0xf << HPIPE_SQ_DEGLITCH_WIDTH_N_OFFSET) +#define HPIPE_SQ_DEGLITCH_WIDTH_N_MASK \ + (0xf << HPIPE_SQ_DEGLITCH_WIDTH_N_OFFSET) #define HPIPE_SQ_DEGLITCH_EN_OFFSET 8 -#define HPIPE_SQ_DEGLITCH_EN_MASK (0x1 << HPIPE_SQ_DEGLITCH_EN_OFFSET) +#define HPIPE_SQ_DEGLITCH_EN_MASK \ + (0x1 << HPIPE_SQ_DEGLITCH_EN_OFFSET) #define HPIPE_FRAME_DETECT_CTRL_0_REG 0x214 #define HPIPE_TRAIN_PAT_NUM_OFFSET 0x7 -#define HPIPE_TRAIN_PAT_NUM_MASK (0x1FF << HPIPE_TRAIN_PAT_NUM_OFFSET) +#define HPIPE_TRAIN_PAT_NUM_MASK \ + (0x1FF << HPIPE_TRAIN_PAT_NUM_OFFSET) #define HPIPE_FRAME_DETECT_CTRL_3_REG 0x220 #define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET 12 -#define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK (0x1 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET) +#define HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_MASK \ + (0x1 << HPIPE_PATTERN_LOCK_LOST_TIMEOUT_EN_OFFSET) #define HPIPE_DME_REG 0x228 #define HPIPE_DME_ETHERNET_MODE_OFFSET 7 -#define HPIPE_DME_ETHERNET_MODE_MASK (0x1 << HPIPE_DME_ETHERNET_MODE_OFFSET) +#define HPIPE_DME_ETHERNET_MODE_MASK \ + (0x1 << HPIPE_DME_ETHERNET_MODE_OFFSET) #define HPIPE_TRX_TRAIN_CTRL_0_REG 0x22c #define HPIPE_TRX_TX_F0T_EO_BASED_OFFSET 14 @@ -442,31 +564,41 @@ #define HPIPE_TX_TRAIN_CTRL_0_REG 0x268 #define HPIPE_TX_TRAIN_P2P_HOLD_OFFSET 15 -#define HPIPE_TX_TRAIN_P2P_HOLD_MASK (0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET) +#define HPIPE_TX_TRAIN_P2P_HOLD_MASK \ + (0x1 << HPIPE_TX_TRAIN_P2P_HOLD_OFFSET) #define HPIPE_TX_TRAIN_CTRL_REG 0x26C #define HPIPE_TX_TRAIN_CTRL_G1_OFFSET 0 -#define HPIPE_TX_TRAIN_CTRL_G1_MASK (0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET) +#define HPIPE_TX_TRAIN_CTRL_G1_MASK \ + (0x1 << HPIPE_TX_TRAIN_CTRL_G1_OFFSET) #define HPIPE_TX_TRAIN_CTRL_GN1_OFFSET 1 -#define HPIPE_TX_TRAIN_CTRL_GN1_MASK (0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET) +#define HPIPE_TX_TRAIN_CTRL_GN1_MASK \ + (0x1 << HPIPE_TX_TRAIN_CTRL_GN1_OFFSET) #define HPIPE_TX_TRAIN_CTRL_G0_OFFSET 2 -#define HPIPE_TX_TRAIN_CTRL_G0_MASK (0x1 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET) +#define HPIPE_TX_TRAIN_CTRL_G0_MASK \ + (0x1 << HPIPE_TX_TRAIN_CTRL_G0_OFFSET) #define HPIPE_TX_TRAIN_CTRL_4_REG 0x278 #define HPIPE_TRX_TRAIN_TIMER_OFFSET 0 -#define HPIPE_TRX_TRAIN_TIMER_MASK (0x3FF << HPIPE_TRX_TRAIN_TIMER_OFFSET) +#define HPIPE_TRX_TRAIN_TIMER_MASK \ + (0x3FF << HPIPE_TRX_TRAIN_TIMER_OFFSET) #define HPIPE_TX_TRAIN_CTRL_5_REG 0x2A4 #define HPIPE_RX_TRAIN_TIMER_OFFSET 0 -#define HPIPE_RX_TRAIN_TIMER_MASK (0x3ff << HPIPE_RX_TRAIN_TIMER_OFFSET) +#define HPIPE_RX_TRAIN_TIMER_MASK \ + (0x3ff << HPIPE_RX_TRAIN_TIMER_OFFSET) #define HPIPE_TX_TRAIN_START_SQ_EN_OFFSET 11 -#define HPIPE_TX_TRAIN_START_SQ_EN_MASK (0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET) +#define HPIPE_TX_TRAIN_START_SQ_EN_MASK \ + (0x1 << HPIPE_TX_TRAIN_START_SQ_EN_OFFSET) #define HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET 12 -#define HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK (0x1 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET) +#define HPIPE_TX_TRAIN_START_FRM_DET_EN_MASK \ + (0x1 << HPIPE_TX_TRAIN_START_FRM_DET_EN_OFFSET) #define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET 13 -#define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK (0x1 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET) +#define HPIPE_TX_TRAIN_START_FRM_LOCK_EN_MASK \ + (0x1 << HPIPE_TX_TRAIN_START_FRM_LOCK_EN_OFFSET) #define HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET 14 -#define HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK (0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET) +#define HPIPE_TX_TRAIN_WAIT_TIME_EN_MASK \ + (0x1 << HPIPE_TX_TRAIN_WAIT_TIME_EN_OFFSET) #define HPIPE_INTERRUPT_1_REGISTER 0x2AC #define HPIPE_TRX_TRAIN_FAILED_OFFSET 6 @@ -482,69 +614,94 @@ #define HPIPE_TX_TRAIN_REG 0x31C #define HPIPE_TX_TRAIN_CHK_INIT_OFFSET 4 -#define HPIPE_TX_TRAIN_CHK_INIT_MASK (0x1 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET) +#define HPIPE_TX_TRAIN_CHK_INIT_MASK \ + (0x1 << HPIPE_TX_TRAIN_CHK_INIT_OFFSET) #define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET 7 -#define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK (0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET) +#define HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_MASK \ + (0x1 << HPIPE_TX_TRAIN_COE_FM_PIN_PCIE3_OFFSET) #define HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET 8 -#define HPIPE_TX_TRAIN_16BIT_AUTO_EN_MASK (0x1 << HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET) +#define HPIPE_TX_TRAIN_16BIT_AUTO_EN_MASK \ + (0x1 << HPIPE_TX_TRAIN_16BIT_AUTO_EN_OFFSET) #define HPIPE_TX_TRAIN_PAT_SEL_OFFSET 9 -#define HPIPE_TX_TRAIN_PAT_SEL_MASK (0x1 << HPIPE_TX_TRAIN_PAT_SEL_OFFSET) +#define HPIPE_TX_TRAIN_PAT_SEL_MASK \ + (0x1 << HPIPE_TX_TRAIN_PAT_SEL_OFFSET) -#define HPIPE_SAVED_DFE_VALUES_REG 0x328 -#define HPIPE_SAVED_DFE_VALUES_SAV_F0D_OFFSET 10 -#define HPIPE_SAVED_DFE_VALUES_SAV_F0D_MASK (0x3f << HPIPE_SAVED_DFE_VALUES_SAV_F0D_OFFSET) +#define HPIPE_SAVED_DFE_VALUES_REG 0x328 +#define HPIPE_SAVED_DFE_VALUES_SAV_F0D_OFFSET 10 +#define HPIPE_SAVED_DFE_VALUES_SAV_F0D_MASK \ + (0x3f << HPIPE_SAVED_DFE_VALUES_SAV_F0D_OFFSET) #define HPIPE_CDR_CONTROL_REG 0x418 #define HPIPE_CDR_RX_MAX_DFE_ADAPT_0_OFFSET 14 -#define HPIPE_CDR_RX_MAX_DFE_ADAPT_0_MASK (0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_0_OFFSET) +#define HPIPE_CDR_RX_MAX_DFE_ADAPT_0_MASK \ + (0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_0_OFFSET) #define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET 12 -#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK (0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET) +#define HPIPE_CDR_RX_MAX_DFE_ADAPT_1_MASK \ + (0x3 << HPIPE_CDR_RX_MAX_DFE_ADAPT_1_OFFSET) #define HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET 9 -#define HPIPE_CDR_MAX_DFE_ADAPT_0_MASK (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET) +#define HPIPE_CDR_MAX_DFE_ADAPT_0_MASK \ + (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_0_OFFSET) #define HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET 6 -#define HPIPE_CDR_MAX_DFE_ADAPT_1_MASK (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET) +#define HPIPE_CDR_MAX_DFE_ADAPT_1_MASK \ + (0x7 << HPIPE_CDR_MAX_DFE_ADAPT_1_OFFSET) #define HPIPE_TX_TRAIN_CTRL_11_REG 0x438 #define HPIPE_TX_STATUS_CHECK_MODE_OFFSET 6 -#define HPIPE_TX_TX_STATUS_CHECK_MODE_MASK (0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET) +#define HPIPE_TX_TX_STATUS_CHECK_MODE_MASK \ + (0x1 << HPIPE_TX_STATUS_CHECK_MODE_OFFSET) #define HPIPE_TX_NUM_OF_PRESET_OFFSET 10 -#define HPIPE_TX_NUM_OF_PRESET_MASK (0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET) +#define HPIPE_TX_NUM_OF_PRESET_MASK \ + (0x7 << HPIPE_TX_NUM_OF_PRESET_OFFSET) #define HPIPE_TX_SWEEP_PRESET_EN_OFFSET 15 -#define HPIPE_TX_SWEEP_PRESET_EN_MASK (0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET) +#define HPIPE_TX_SWEEP_PRESET_EN_MASK \ + (0x1 << HPIPE_TX_SWEEP_PRESET_EN_OFFSET) #define HPIPE_G1_SETTINGS_3_REG 0x440 #define HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET 0 -#define HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK (0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET) +#define HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_MASK \ + (0xf << HPIPE_G1_SETTINGS_3_G1_FFE_CAP_SEL_OFFSET) #define HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET 4 -#define HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK (0x7 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET) +#define HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_MASK \ + (0x7 << HPIPE_G1_SETTINGS_3_G1_FFE_RES_SEL_OFFSET) #define HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET 7 -#define HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK (0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET) +#define HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_MASK \ + (0x1 << HPIPE_G1_SETTINGS_3_G1_FFE_SETTING_FORCE_OFFSET) #define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET 9 -#define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK (0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET) +#define HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_MASK \ + (0x1 << HPIPE_G1_SETTINGS_3_G1_FBCK_SEL_OFFSET) #define HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET 12 -#define HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_MASK (0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET) +#define HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_MASK \ + (0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_DEG_RES_LEVEL_OFFSET) #define HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET 14 -#define HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_MASK (0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET) +#define HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_MASK \ + (0x3 << HPIPE_G1_SETTINGS_3_G1_FFE_LOAD_RES_LEVEL_OFFSET) #define HPIPE_G1_SETTINGS_4_REG 0x444 #define HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET 8 -#define HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK (0x3 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET) +#define HPIPE_G1_SETTINGS_4_G1_DFE_RES_MASK \ + (0x3 << HPIPE_G1_SETTINGS_4_G1_DFE_RES_OFFSET) #define HPIPE_G2_SETTINGS_4_REG 0x44c #define HPIPE_G2_DFE_RES_OFFSET 8 -#define HPIPE_G2_DFE_RES_MASK (0x3 << HPIPE_G2_DFE_RES_OFFSET) +#define HPIPE_G2_DFE_RES_MASK \ + (0x3 << HPIPE_G2_DFE_RES_OFFSET) #define HPIPE_G3_SETTING_3_REG 0x450 #define HPIPE_G3_FFE_CAP_SEL_OFFSET 0 -#define HPIPE_G3_FFE_CAP_SEL_MASK (0xf << HPIPE_G3_FFE_CAP_SEL_OFFSET) +#define HPIPE_G3_FFE_CAP_SEL_MASK \ + (0xf << HPIPE_G3_FFE_CAP_SEL_OFFSET) #define HPIPE_G3_FFE_RES_SEL_OFFSET 4 -#define HPIPE_G3_FFE_RES_SEL_MASK (0x7 << HPIPE_G3_FFE_RES_SEL_OFFSET) +#define HPIPE_G3_FFE_RES_SEL_MASK \ + (0x7 << HPIPE_G3_FFE_RES_SEL_OFFSET) #define HPIPE_G3_FFE_SETTING_FORCE_OFFSET 7 -#define HPIPE_G3_FFE_SETTING_FORCE_MASK (0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET) +#define HPIPE_G3_FFE_SETTING_FORCE_MASK \ + (0x1 << HPIPE_G3_FFE_SETTING_FORCE_OFFSET) #define HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET 12 -#define HPIPE_G3_FFE_DEG_RES_LEVEL_MASK (0x3 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET) +#define HPIPE_G3_FFE_DEG_RES_LEVEL_MASK \ + (0x3 << HPIPE_G3_FFE_DEG_RES_LEVEL_OFFSET) #define HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET 14 -#define HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK (0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET) +#define HPIPE_G3_FFE_LOAD_RES_LEVEL_MASK \ + (0x3 << HPIPE_G3_FFE_LOAD_RES_LEVEL_OFFSET) #define HPIPE_G3_SETTING_4_REG 0x454 #define HPIPE_G3_DFE_RES_OFFSET 8 @@ -552,98 +709,128 @@ #define HPIPE_TX_PRESET_INDEX_REG 0x468 #define HPIPE_TX_PRESET_INDEX_OFFSET 0 -#define HPIPE_TX_PRESET_INDEX_MASK (0xf << HPIPE_TX_PRESET_INDEX_OFFSET) +#define HPIPE_TX_PRESET_INDEX_MASK \ + (0xf << HPIPE_TX_PRESET_INDEX_OFFSET) #define HPIPE_DFE_CONTROL_REG 0x470 #define HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET 14 -#define HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK (0x3 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET) +#define HPIPE_DFE_TX_MAX_DFE_ADAPT_MASK \ + (0x3 << HPIPE_DFE_TX_MAX_DFE_ADAPT_OFFSET) #define HPIPE_DFE_CTRL_28_REG 0x49C #define HPIPE_DFE_CTRL_28_PIPE4_OFFSET 7 -#define HPIPE_DFE_CTRL_28_PIPE4_MASK (0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET) +#define HPIPE_DFE_CTRL_28_PIPE4_MASK \ + (0x1 << HPIPE_DFE_CTRL_28_PIPE4_OFFSET) #define HPIPE_G1_SETTING_5_REG 0x538 #define HPIPE_G1_SETTING_5_G1_ICP_OFFSET 0 -#define HPIPE_G1_SETTING_5_G1_ICP_MASK (0xf << HPIPE_G1_SETTING_5_G1_ICP_OFFSET) +#define HPIPE_G1_SETTING_5_G1_ICP_MASK \ + (0xf << HPIPE_G1_SETTING_5_G1_ICP_OFFSET) #define HPIPE_G3_SETTING_5_REG 0x548 #define HPIPE_G3_SETTING_5_G3_ICP_OFFSET 0 -#define HPIPE_G3_SETTING_5_G3_ICP_MASK (0xf << HPIPE_G3_SETTING_5_G3_ICP_OFFSET) +#define HPIPE_G3_SETTING_5_G3_ICP_MASK \ + (0xf << HPIPE_G3_SETTING_5_G3_ICP_OFFSET) #define HPIPE_LANE_CONFIG0_REG 0x600 #define HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET 0 -#define HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK (0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET) +#define HPIPE_LANE_CONFIG0_TXDEEMPH0_MASK \ + (0x1 << HPIPE_LANE_CONFIG0_TXDEEMPH0_OFFSET) #define HPIPE_LANE_STATUS1_REG 0x60C #define HPIPE_LANE_STATUS1_PCLK_EN_OFFSET 0 -#define HPIPE_LANE_STATUS1_PCLK_EN_MASK (0x1 << HPIPE_LANE_STATUS1_PCLK_EN_OFFSET) +#define HPIPE_LANE_STATUS1_PCLK_EN_MASK \ + (0x1 << HPIPE_LANE_STATUS1_PCLK_EN_OFFSET) -#define HPIPE_LANE_CFG4_REG 0x620 +#define HPIPE_LANE_CFG4_REG 0x620 #define HPIPE_LANE_CFG4_DFE_CTRL_OFFSET 0 -#define HPIPE_LANE_CFG4_DFE_CTRL_MASK (0x7 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET) +#define HPIPE_LANE_CFG4_DFE_CTRL_MASK \ + (0x7 << HPIPE_LANE_CFG4_DFE_CTRL_OFFSET) #define HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET 3 -#define HPIPE_LANE_CFG4_DFE_EN_SEL_MASK (0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET) +#define HPIPE_LANE_CFG4_DFE_EN_SEL_MASK \ + (0x1 << HPIPE_LANE_CFG4_DFE_EN_SEL_OFFSET) #define HPIPE_LANE_CFG4_DFE_OVER_OFFSET 6 -#define HPIPE_LANE_CFG4_DFE_OVER_MASK (0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET) +#define HPIPE_LANE_CFG4_DFE_OVER_MASK \ + (0x1 << HPIPE_LANE_CFG4_DFE_OVER_OFFSET) #define HPIPE_LANE_CFG4_SSC_CTRL_OFFSET 7 -#define HPIPE_LANE_CFG4_SSC_CTRL_MASK (0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET) +#define HPIPE_LANE_CFG4_SSC_CTRL_MASK \ + (0x1 << HPIPE_LANE_CFG4_SSC_CTRL_OFFSET) #define HPIPE_LANE_EQ_REMOTE_SETTING_REG 0x6f8 #define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET 0 -#define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK (0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET) +#define HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_MASK \ + (0x1 << HPIPE_LANE_CFG_FOM_DIRN_OVERRIDE_OFFSET) #define HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET 1 -#define HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK (0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET) +#define HPIPE_LANE_CFG_FOM_ONLY_MODE_MASK \ + (0x1 << HPIPE_LANE_CFG_FOM_ONLY_MODE_OFFFSET) #define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET 2 -#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK (0xf << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET) +#define HPIPE_LANE_CFG_FOM_PRESET_VECTOR_MASK \ + (0xf << HPIPE_LANE_CFG_FOM_PRESET_VECTOR_OFFSET) #define HPIPE_LANE_EQU_CONFIG_0_REG 0x69C #define HPIPE_CFG_PHY_RC_EP_OFFSET 12 -#define HPIPE_CFG_PHY_RC_EP_MASK (0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET) +#define HPIPE_CFG_PHY_RC_EP_MASK \ + (0x1 << HPIPE_CFG_PHY_RC_EP_OFFSET) #define HPIPE_LANE_EQ_CFG1_REG 0x6a0 #define HPIPE_CFG_UPDATE_POLARITY_OFFSET 12 -#define HPIPE_CFG_UPDATE_POLARITY_MASK (0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET) +#define HPIPE_CFG_UPDATE_POLARITY_MASK \ + (0x1 << HPIPE_CFG_UPDATE_POLARITY_OFFSET) #define HPIPE_LANE_EQ_CFG2_REG 0x6a4 #define HPIPE_CFG_EQ_BUNDLE_DIS_OFFSET 14 -#define HPIPE_CFG_EQ_BUNDLE_DIS_MASK (0x1 << HPIPE_CFG_EQ_BUNDLE_DIS_OFFSET) +#define HPIPE_CFG_EQ_BUNDLE_DIS_MASK \ + (0x1 << HPIPE_CFG_EQ_BUNDLE_DIS_OFFSET) #define HPIPE_RST_CLK_CTRL_REG 0x704 #define HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET 0 -#define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK (0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET) +#define HPIPE_RST_CLK_CTRL_PIPE_RST_MASK \ + (0x1 << HPIPE_RST_CLK_CTRL_PIPE_RST_OFFSET) #define HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET 2 -#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK (0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET) +#define HPIPE_RST_CLK_CTRL_FIXED_PCLK_MASK \ + (0x1 << HPIPE_RST_CLK_CTRL_FIXED_PCLK_OFFSET) #define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET 3 -#define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK (0x1 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET) +#define HPIPE_RST_CLK_CTRL_PIPE_WIDTH_MASK \ + (0x1 << HPIPE_RST_CLK_CTRL_PIPE_WIDTH_OFFSET) #define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET 9 -#define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK (0x1 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET) +#define HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_MASK \ + (0x1 << HPIPE_RST_CLK_CTRL_CORE_FREQ_SEL_OFFSET) #define HPIPE_TST_MODE_CTRL_REG 0x708 #define HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET 2 -#define HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK (0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET) +#define HPIPE_TST_MODE_CTRL_MODE_MARGIN_MASK \ + (0x1 << HPIPE_TST_MODE_CTRL_MODE_MARGIN_OFFSET) -#define HPIPE_CLK_SRC_LO_REG 0x70c +#define HPIPE_CLK_SRC_LO_REG 0x70c #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET 1 -#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK (0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET) +#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_MASK \ + (0x1 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SEL_OFFSET) #define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET 2 -#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK (0x3 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET) -#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET 5 -#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK (0x7 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET) +#define HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_MASK \ + (0x3 << HPIPE_CLK_SRC_LO_BUNDLE_PERIOD_SCALE_OFFSET) +#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET 5 +#define HPIPE_CLK_SRC_LO_PLL_RDY_DL_MASK \ + (0x7 << HPIPE_CLK_SRC_LO_PLL_RDY_DL_OFFSET) #define HPIPE_CLK_SRC_HI_REG 0x710 #define HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET 0 -#define HPIPE_CLK_SRC_HI_LANE_STRT_MASK (0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET) +#define HPIPE_CLK_SRC_HI_LANE_STRT_MASK \ + (0x1 << HPIPE_CLK_SRC_HI_LANE_STRT_OFFSET) #define HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET 1 -#define HPIPE_CLK_SRC_HI_LANE_BREAK_MASK (0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET) +#define HPIPE_CLK_SRC_HI_LANE_BREAK_MASK \ + (0x1 << HPIPE_CLK_SRC_HI_LANE_BREAK_OFFSET) #define HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET 2 -#define HPIPE_CLK_SRC_HI_LANE_MASTER_MASK (0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET) +#define HPIPE_CLK_SRC_HI_LANE_MASTER_MASK \ + (0x1 << HPIPE_CLK_SRC_HI_LANE_MASTER_OFFSET) #define HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET 7 -#define HPIPE_CLK_SRC_HI_MODE_PIPE_MASK (0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET) +#define HPIPE_CLK_SRC_HI_MODE_PIPE_MASK \ + (0x1 << HPIPE_CLK_SRC_HI_MODE_PIPE_OFFSET) -#define HPIPE_GLOBAL_MISC_CTRL 0x718 -#define HPIPE_GLOBAL_PM_CTRL 0x740 +#define HPIPE_GLOBAL_MISC_CTRL 0x718 +#define HPIPE_GLOBAL_PM_CTRL 0x740 #define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET 0 -#define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK (0xFF << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET) +#define HPIPE_GLOBAL_PM_RXDLOZ_WAIT_MASK \ + (0xFF << HPIPE_GLOBAL_PM_RXDLOZ_WAIT_OFFSET) /* General defines */ #define PLL_LOCK_TIMEOUT 15000 diff --git a/drivers/marvell/comphy/phy-comphy-cp110.c b/drivers/marvell/comphy/phy-comphy-cp110.c index 9686d00c..6e7be7f3 100644 --- a/drivers/marvell/comphy/phy-comphy-cp110.c +++ b/drivers/marvell/comphy/phy-comphy-cp110.c @@ -5,12 +5,14 @@ * https://spdx.org/licenses */ +/* Marvell CP110 SoC COMPHY unit driver */ + #include <ap_setup.h> #include <debug.h> #include <delay_timer.h> #include <errno.h> #include <mmio.h> -#include <plat_def.h> +#include <mvebu_def.h> #include <spinlock.h> #include "mvebu.h" #include "comphy-cp110.h" @@ -41,35 +43,45 @@ #define COMPHY_INVERT_OFFSET 0 #define COMPHY_INVERT_LEN 2 -#define COMPHY_INVERT_MASK COMPHY_MASK(COMPHY_INVERT_OFFSET, COMPHY_INVERT_LEN) +#define COMPHY_INVERT_MASK COMPHY_MASK(COMPHY_INVERT_OFFSET, \ + COMPHY_INVERT_LEN) #define COMPHY_SPEED_OFFSET (COMPHY_INVERT_OFFSET + COMPHY_INVERT_LEN) #define COMPHY_SPEED_LEN 6 -#define COMPHY_SPEED_MASK COMPHY_MASK(COMPHY_SPEED_OFFSET, COMPHY_SPEED_LEN) +#define COMPHY_SPEED_MASK COMPHY_MASK(COMPHY_SPEED_OFFSET, \ + COMPHY_SPEED_LEN) #define COMPHY_UNIT_ID_OFFSET (COMPHY_SPEED_OFFSET + COMPHY_SPEED_LEN) #define COMPHY_UNIT_ID_LEN 4 -#define COMPHY_UNIT_ID_MASK COMPHY_MASK(COMPHY_UNIT_ID_OFFSET, COMPHY_UNIT_ID_LEN) +#define COMPHY_UNIT_ID_MASK COMPHY_MASK(COMPHY_UNIT_ID_OFFSET, \ + COMPHY_UNIT_ID_LEN) #define COMPHY_MODE_OFFSET (COMPHY_UNIT_ID_OFFSET + COMPHY_UNIT_ID_LEN) #define COMPHY_MODE_LEN 5 #define COMPHY_MODE_MASK COMPHY_MASK(COMPHY_MODE_OFFSET, COMPHY_MODE_LEN) #define COMPHY_CLK_SRC_OFFSET (COMPHY_MODE_OFFSET + COMPHY_MODE_LEN) #define COMPHY_CLK_SRC_LEN 1 -#define COMPHY_CLK_SRC_MASK COMPHY_MASK(COMPHY_CLK_SRC_OFFSET, COMPHY_CLK_SRC_LEN) +#define COMPHY_CLK_SRC_MASK COMPHY_MASK(COMPHY_CLK_SRC_OFFSET, \ + COMPHY_CLK_SRC_LEN) #define COMPHY_PCI_WIDTH_OFFSET (COMPHY_CLK_SRC_OFFSET + COMPHY_CLK_SRC_LEN) #define COMPHY_PCI_WIDTH_LEN 3 -#define COMPHY_PCI_WIDTH_MASK COMPHY_MASK(COMPHY_PCI_WIDTH_OFFSET, COMPHY_PCI_WIDTH_LEN) +#define COMPHY_PCI_WIDTH_MASK COMPHY_MASK(COMPHY_PCI_WIDTH_OFFSET, \ + COMPHY_PCI_WIDTH_LEN) #define COMPHY_MASK(offset, len) (((1 << (len)) - 1) << (offset)) /* Macro which extracts mode from lane description */ -#define COMPHY_GET_MODE(x) (((x) & COMPHY_MODE_MASK) >> COMPHY_MODE_OFFSET) +#define COMPHY_GET_MODE(x) (((x) & COMPHY_MODE_MASK) >> \ + COMPHY_MODE_OFFSET) /* Macro which extracts unit index from lane description */ -#define COMPHY_GET_ID(x) (((x) & COMPHY_UNIT_ID_MASK) >> COMPHY_UNIT_ID_OFFSET) +#define COMPHY_GET_ID(x) (((x) & COMPHY_UNIT_ID_MASK) >> \ + COMPHY_UNIT_ID_OFFSET) /* Macro which extracts speed from lane description */ -#define COMPHY_GET_SPEED(x) (((x) & COMPHY_SPEED_MASK) >> COMPHY_SPEED_OFFSET) +#define COMPHY_GET_SPEED(x) (((x) & COMPHY_SPEED_MASK) >> \ + COMPHY_SPEED_OFFSET) /* Macro which extracts clock source indication from lane description */ -#define COMPHY_GET_CLK_SRC(x) (((x) & COMPHY_CLK_SRC_MASK) >> COMPHY_CLK_SRC_OFFSET) +#define COMPHY_GET_CLK_SRC(x) (((x) & COMPHY_CLK_SRC_MASK) >> \ + COMPHY_CLK_SRC_OFFSET) /* Macro which extracts pcie width indication from lane description */ -#define COMPHY_GET_PCIE_WIDTH(x) (((x) & COMPHY_PCI_WIDTH_MASK) >> COMPHY_PCI_WIDTH_OFFSET) +#define COMPHY_GET_PCIE_WIDTH(x) (((x) & COMPHY_PCI_WIDTH_MASK) >> \ + COMPHY_PCI_WIDTH_OFFSET) #define COMPHY_SATA_MODE 0x1 #define COMPHY_SGMII_MODE 0x2 /* SGMII 1G */ @@ -101,7 +113,7 @@ #define COMPHY_PIPE_FROM_COMPHY_ADDR(x) ((x & ~0xffffff) + 0x120000) -/* System controler registers */ +/* System controller registers */ #define PCIE_MAC_RESET_MASK_PORT0 BIT(13) #define PCIE_MAC_RESET_MASK_PORT1 BIT(11) #define PCIE_MAC_RESET_MASK_PORT2 BIT(12) @@ -110,9 +122,11 @@ /* DFX register spaces */ #define SAR_RST_PCIE0_CLOCK_CONFIG_CP1_OFFSET (0) -#define SAR_RST_PCIE0_CLOCK_CONFIG_CP1_MASK (0x1 << SAR_RST_PCIE0_CLOCK_CONFIG_CP1_OFFSET) +#define SAR_RST_PCIE0_CLOCK_CONFIG_CP1_MASK (0x1 << \ + SAR_RST_PCIE0_CLOCK_CONFIG_CP1_OFFSET) #define SAR_RST_PCIE1_CLOCK_CONFIG_CP1_OFFSET (1) -#define SAR_RST_PCIE1_CLOCK_CONFIG_CP1_MASK (0x1 << SAR_RST_PCIE1_CLOCK_CONFIG_CP1_OFFSET) +#define SAR_RST_PCIE1_CLOCK_CONFIG_CP1_MASK (0x1 << \ + SAR_RST_PCIE1_CLOCK_CONFIG_CP1_OFFSET) #define SAR_STATUS_0_REG 200 #define DFX_FROM_COMPHY_ADDR(x) ((x & ~0xffffff) + DFX_BASE) @@ -170,8 +184,11 @@ static void mvebu_cp110_get_ap_and_cp_nr(uint8_t *ap_nr, uint8_t *cp_nr, uint64_ (unsigned long)MVEBU_CP_OFFSET); } -static inline uint32_t polling_with_timeout(uintptr_t addr, uint32_t val, - uint32_t mask, uint32_t usec_timout, enum reg_width_type type) +static inline uint32_t polling_with_timeout(uintptr_t addr, + uint32_t val, + uint32_t mask, + uint32_t usec_timeout, + enum reg_width_type type) { uint32_t data; @@ -181,9 +198,9 @@ static inline uint32_t polling_with_timeout(uintptr_t addr, uint32_t val, data = mmio_read_16(addr) & mask; else data = mmio_read_32(addr) & mask; - } while (data != val && --usec_timout > 0); + } while (data != val && --usec_timeout > 0); - if (usec_timout == 0) + if (usec_timeout == 0) return data; return 0; @@ -191,7 +208,7 @@ static inline uint32_t polling_with_timeout(uintptr_t addr, uint32_t val, static inline void reg_set(uintptr_t addr, uint32_t data, uint32_t mask) { - debug("<atf>: Write to address = %#010lx, data = %#010x (mask = %#010x) - ", + debug("<atf>: WR to addr = %#010lx, data = %#010x (mask = %#010x) - ", addr, data, mask); debug("old value = %#010x ==> ", mmio_read_32(addr)); mmio_clrsetbits_32(addr, mask, data); @@ -200,10 +217,12 @@ static inline void reg_set(uintptr_t addr, uint32_t data, uint32_t mask) } /* Clear PIPE selector - avoid collision with previous configuration */ -static void mvebu_cp110_comphy_clr_pipe_selector(uint64_t comphy_base, uint8_t comphy_index) +static void mvebu_cp110_comphy_clr_pipe_selector(uint64_t comphy_base, + uint8_t comphy_index) { uint32_t reg, mask, field; - uint32_t comphy_offset = COMMON_SELECTOR_COMPHYN_FIELD_WIDTH * comphy_index; + uint32_t comphy_offset = + COMMON_SELECTOR_COMPHYN_FIELD_WIDTH * comphy_index; mask = COMMON_SELECTOR_COMPHY_MASK << comphy_offset; reg = mmio_read_32(comphy_base + COMMON_SELECTOR_PIPE_REG_OFFSET); @@ -211,15 +230,18 @@ static void mvebu_cp110_comphy_clr_pipe_selector(uint64_t comphy_base, uint8_t c if (field) { reg &= ~mask; - mmio_write_32(comphy_base + COMMON_SELECTOR_PIPE_REG_OFFSET, reg); + mmio_write_32(comphy_base + COMMON_SELECTOR_PIPE_REG_OFFSET, + reg); } } /* Clear PHY selector - avoid collision with previous configuration */ -static void mvebu_cp110_comphy_clr_phy_selector(uint64_t comphy_base, uint8_t comphy_index) +static void mvebu_cp110_comphy_clr_phy_selector(uint64_t comphy_base, + uint8_t comphy_index) { uint32_t reg, mask, field; - uint32_t comphy_offset = COMMON_SELECTOR_COMPHYN_FIELD_WIDTH * comphy_index; + uint32_t comphy_offset = + COMMON_SELECTOR_COMPHYN_FIELD_WIDTH * comphy_index; mask = COMMON_SELECTOR_COMPHY_MASK << comphy_offset; reg = mmio_read_32(comphy_base + COMMON_SELECTOR_PHY_REG_OFFSET); @@ -232,7 +254,8 @@ static void mvebu_cp110_comphy_clr_phy_selector(uint64_t comphy_base, uint8_t co */ if (field) { reg &= ~mask; - mmio_write_32(comphy_base + COMMON_SELECTOR_PHY_REG_OFFSET, reg); + mmio_write_32(comphy_base + COMMON_SELECTOR_PHY_REG_OFFSET, + reg); } } @@ -241,7 +264,8 @@ static void mvebu_cp110_comphy_set_phy_selector(uint64_t comphy_base, uint8_t comphy_index, uint32_t comphy_mode) { uint32_t reg, mask; - uint32_t comphy_offset = COMMON_SELECTOR_COMPHYN_FIELD_WIDTH * comphy_index; + uint32_t comphy_offset = + COMMON_SELECTOR_COMPHYN_FIELD_WIDTH * comphy_index; int mode; /* If phy selector is used the pipe selector should be marked as @@ -270,7 +294,8 @@ static void mvebu_cp110_comphy_set_phy_selector(uint64_t comphy_base, /* For comphy 0,1, and 2: * Network selector value is always 1. */ - reg |= COMMON_SELECTOR_COMPHY0_1_2_NETWORK << comphy_offset; + reg |= COMMON_SELECTOR_COMPHY0_1_2_NETWORK << + comphy_offset; break; case(3): /* For comphy 3: @@ -278,28 +303,35 @@ static void mvebu_cp110_comphy_set_phy_selector(uint64_t comphy_base, * 0x2 = SGMII/HS-SGMII Port1 */ if (mode == COMPHY_RXAUI_MODE) - reg |= COMMON_SELECTOR_COMPHY3_RXAUI << comphy_offset; + reg |= COMMON_SELECTOR_COMPHY3_RXAUI << + comphy_offset; else - reg |= COMMON_SELECTOR_COMPHY3_SGMII << comphy_offset; + reg |= COMMON_SELECTOR_COMPHY3_SGMII << + comphy_offset; break; case(4): /* For comphy 4: * 0x1 = SGMII/HS-SGMII Port1, XFI1/SFI1 * 0x2 = SGMII/HS-SGMII Port0: XFI0/SFI0, RXAUI_Lane0 * - * We want to check if SGMII1/HS_SGMII1 is the requested mode in order to - * determine which value should be set (all other modes use the same value) - * so we need to strip the mode, and check the ID because we might handle - * SGMII0/HS_SGMII0 too. + * We want to check if SGMII1/HS_SGMII1 is the + * requested mode in order to determine which value + * should be set (all other modes use the same value) + * so we need to strip the mode, and check the ID + * because we might handle SGMII0/HS_SGMII0 too. */ - /* TODO: need to diffrenciate between CP110 and CP115 as SFI1/XFI1 - * availalbe only for CP115. + /* TODO: need to distinguish between CP110 and CP115 + * as SFI1/XFI1 available only for CP115. */ - if ((mode == COMPHY_SGMII_MODE || mode == COMPHY_HS_SGMII_MODE || - mode == COMPHY_SFI_MODE) && COMPHY_GET_ID(comphy_mode) == 1) - reg |= COMMON_SELECTOR_COMPHY4_PORT1 << comphy_offset; + if ((mode == COMPHY_SGMII_MODE || + mode == COMPHY_HS_SGMII_MODE || + mode == COMPHY_SFI_MODE) && + COMPHY_GET_ID(comphy_mode) == 1) + reg |= COMMON_SELECTOR_COMPHY4_PORT1 << + comphy_offset; else - reg |= COMMON_SELECTOR_COMPHY4_ALL_OTHERS << comphy_offset; + reg |= COMMON_SELECTOR_COMPHY4_ALL_OTHERS << + comphy_offset; break; case(5): /* For comphy 5: @@ -307,9 +339,11 @@ static void mvebu_cp110_comphy_set_phy_selector(uint64_t comphy_base, * 0x2 = RXAUI Lane1 */ if (mode == COMPHY_RXAUI_MODE) - reg |= COMMON_SELECTOR_COMPHY5_RXAUI << comphy_offset; + reg |= COMMON_SELECTOR_COMPHY5_RXAUI << + comphy_offset; else - reg |= COMMON_SELECTOR_COMPHY5_SGMII << comphy_offset; + reg |= COMMON_SELECTOR_COMPHY5_SGMII << + comphy_offset; break; } } @@ -378,13 +412,15 @@ int mvebu_cp110_comphy_is_pll_locked(uint64_t comphy_base, uint8_t comphy_index) debug_enter(); - sd_ip_addr = SD_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), comphy_index); + sd_ip_addr = SD_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), + comphy_index); addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; data = SD_EXTERNAL_STATUS0_PLL_TX_MASK & SD_EXTERNAL_STATUS0_PLL_RX_MASK; mask = data; - data = polling_with_timeout(addr, data, mask, PLL_LOCK_TIMEOUT, REG_32BIT); + data = polling_with_timeout(addr, data, mask, + PLL_LOCK_TIMEOUT, REG_32BIT); if (data != 0) { if (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK) ERROR("RX PLL is not locked\n"); @@ -422,10 +458,13 @@ static int mvebu_cp110_comphy_sata_power_on(uint64_t comphy_base, /* configure phy selector for SATA */ - mvebu_cp110_comphy_set_phy_selector(comphy_base, comphy_index, comphy_mode); + mvebu_cp110_comphy_set_phy_selector(comphy_base, + comphy_index, comphy_mode); - hpipe_addr = HPIPE_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), comphy_index); - sd_ip_addr = SD_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), comphy_index); + hpipe_addr = HPIPE_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), + comphy_index); + sd_ip_addr = SD_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), + comphy_index); comphy_addr = COMPHY_ADDR(comphy_base, comphy_index); debug(" add hpipe 0x%lx, sd 0x%lx, comphy 0x%lx\n", @@ -444,7 +483,8 @@ static int mvebu_cp110_comphy_sata_power_on(uint64_t comphy_base, /* Set select data width 40Bit - SATA mode only */ reg_set(comphy_addr + COMMON_PHY_CFG6_REG, - 0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET, COMMON_PHY_CFG6_IF_40_SEL_MASK); + 0x1 << COMMON_PHY_CFG6_IF_40_SEL_OFFSET, + COMMON_PHY_CFG6_IF_40_SEL_MASK); /* release from hard reset in SD external */ mask = SD_EXTERNAL_CONFIG1_RESET_IN_MASK; @@ -460,7 +500,8 @@ static int mvebu_cp110_comphy_sata_power_on(uint64_t comphy_base, /* Start comphy Configuration */ /* Set reference clock to comes from group 1 - choose 25Mhz */ reg_set(hpipe_addr + HPIPE_MISC_REG, - 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET, HPIPE_MISC_REFCLK_SEL_MASK); + 0x0 << HPIPE_MISC_REFCLK_SEL_OFFSET, + HPIPE_MISC_REFCLK_SEL_MASK); /* Reference frequency select set 1 (for SATA = 25Mhz) */ mask = HPIPE_PWR_PLL_REF_FREQ_MASK; data = 0x1 << HPIPE_PWR_PLL_REF_FREQ_OFFSET; @@ -470,7 +511,8 @@ static int mvebu_cp110_comphy_sata_power_on(uint64_t comphy_base, reg_set(hpipe_addr + HPIPE_PWR_PLL_REG, data, mask); /* Set max PHY generation setting - 6Gbps */ reg_set(hpipe_addr + HPIPE_INTERFACE_REG, - 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET, HPIPE_INTERFACE_GEN_MAX_MASK); + 0x2 << HPIPE_INTERFACE_GEN_MAX_OFFSET, + HPIPE_INTERFACE_GEN_MAX_MASK); /* Set select data width 40Bit (SEL_BITS[2:0]) */ reg_set(hpipe_addr + HPIPE_LOOPBACK_REG, 0x2 << HPIPE_LOOPBACK_SEL_OFFSET, HPIPE_LOOPBACK_SEL_MASK); @@ -671,14 +713,18 @@ static int mvebu_cp110_comphy_sata_power_on(uint64_t comphy_base, /* DFE reset sequence */ reg_set(hpipe_addr + HPIPE_PWR_CTR_REG, - 0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET, HPIPE_PWR_CTR_RST_DFE_MASK); + 0x1 << HPIPE_PWR_CTR_RST_DFE_OFFSET, + HPIPE_PWR_CTR_RST_DFE_MASK); reg_set(hpipe_addr + HPIPE_PWR_CTR_REG, - 0x0 << HPIPE_PWR_CTR_RST_DFE_OFFSET, HPIPE_PWR_CTR_RST_DFE_MASK); + 0x0 << HPIPE_PWR_CTR_RST_DFE_OFFSET, + HPIPE_PWR_CTR_RST_DFE_MASK); /* SW reset for interrupt logic */ reg_set(hpipe_addr + HPIPE_PWR_CTR_REG, - 0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET, HPIPE_PWR_CTR_SFT_RST_MASK); + 0x1 << HPIPE_PWR_CTR_SFT_RST_OFFSET, + HPIPE_PWR_CTR_SFT_RST_MASK); reg_set(hpipe_addr + HPIPE_PWR_CTR_REG, - 0x0 << HPIPE_PWR_CTR_SFT_RST_OFFSET, HPIPE_PWR_CTR_SFT_RST_MASK); + 0x0 << HPIPE_PWR_CTR_SFT_RST_OFFSET, + HPIPE_PWR_CTR_SFT_RST_MASK); debug_exit(); @@ -694,12 +740,15 @@ static int mvebu_cp110_comphy_sgmii_power_on(uint64_t comphy_base, debug_enter(); - hpipe_addr = HPIPE_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), comphy_index); - sd_ip_addr = SD_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), comphy_index); + hpipe_addr = HPIPE_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), + comphy_index); + sd_ip_addr = SD_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), + comphy_index); comphy_addr = COMPHY_ADDR(comphy_base, comphy_index); /* configure phy selector for SGMII */ - mvebu_cp110_comphy_set_phy_selector(comphy_base, comphy_index, comphy_mode); + mvebu_cp110_comphy_set_phy_selector(comphy_base, comphy_index, + comphy_mode); /* Confiugre the lane */ debug("stage: RFU configurations - hard reset comphy\n"); @@ -795,7 +844,8 @@ static int mvebu_cp110_comphy_sgmii_power_on(uint64_t comphy_base, debug("stage: Analog parameters from ETP(HW)\n"); reg_set(hpipe_addr + HPIPE_G1_SET_0_REG, - 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET, HPIPE_G1_SET_0_G1_TX_EMPH1_MASK); + 0x1 << HPIPE_G1_SET_0_G1_TX_EMPH1_OFFSET, + HPIPE_G1_SET_0_G1_TX_EMPH1_MASK); debug("stage: RFU configurations- Power Up PLL,Tx,Rx\n"); /* SERDES External Configuration */ @@ -883,12 +933,15 @@ static int mvebu_cp110_comphy_xfi_power_on(uint64_t comphy_base, return -EINVAL; } - hpipe_addr = HPIPE_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), comphy_index); - sd_ip_addr = SD_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), comphy_index); + hpipe_addr = HPIPE_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), + comphy_index); + sd_ip_addr = SD_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), + comphy_index); comphy_addr = COMPHY_ADDR(comphy_base, comphy_index); /* configure phy selector for XFI/SFI */ - mvebu_cp110_comphy_set_phy_selector(comphy_base, comphy_index, comphy_mode); + mvebu_cp110_comphy_set_phy_selector(comphy_base, comphy_index, + comphy_mode); debug("stage: RFU configurations - hard reset comphy\n"); /* RFU configurations - hard reset comphy */ @@ -1181,9 +1234,11 @@ static int mvebu_cp110_comphy_xfi_power_on(uint64_t comphy_base, /* check PLL rx & tx ready */ addr = sd_ip_addr + SD_EXTERNAL_STATUS0_REG; - data = SD_EXTERNAL_STATUS0_PLL_RX_MASK | SD_EXTERNAL_STATUS0_PLL_TX_MASK; + data = SD_EXTERNAL_STATUS0_PLL_RX_MASK | + SD_EXTERNAL_STATUS0_PLL_TX_MASK; mask = data; - data = polling_with_timeout(addr, data, mask, PLL_LOCK_TIMEOUT, REG_32BIT); + data = polling_with_timeout(addr, data, mask, + PLL_LOCK_TIMEOUT, REG_32BIT); if (data != 0) { if (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK) ERROR("RX PLL is not locked\n"); @@ -1240,7 +1295,7 @@ static int mvebu_cp110_comphy_pcie_power_on(uint64_t comphy_base, spin_lock(&cp110_mac_reset_lock); reg = mmio_read_32(SYS_CTRL_FROM_COMPHY_ADDR(comphy_base) + - SYS_CTRL_UINIT_SOFT_RESET_REG); + SYS_CTRL_UINIT_SOFT_RESET_REG); switch (comphy_index) { case COMPHY_LANE0: reg |= PCIE_MAC_RESET_MASK_PORT0; @@ -1259,7 +1314,7 @@ static int mvebu_cp110_comphy_pcie_power_on(uint64_t comphy_base, /* Configure PIPE selector for PCIE */ mvebu_cp110_comphy_set_pipe_selector(comphy_base, comphy_index, - comphy_mode); + comphy_mode); /* * Read SAR (Sample-At-Reset) configuration for the PCIe clock @@ -1388,7 +1443,7 @@ static int mvebu_cp110_comphy_pcie_power_on(uint64_t comphy_base, mask |= HPIPE_MISC_CLK100M_125M_MASK; data |= 0x1 << HPIPE_MISC_CLK100M_125M_OFFSET; } - /* Set PIN_TXDCLK_2X Clock Frequency Selection for outputs 500MHz clock */ + /* Set PIN_TXDCLK_2X Clock Freq. Selection for outputs 500MHz clock */ mask |= HPIPE_MISC_TXDCLK_2X_MASK; data |= 0x0 << HPIPE_MISC_TXDCLK_2X_OFFSET; /* Enable 500MHz Clock */ @@ -1634,9 +1689,10 @@ static int mvebu_cp110_comphy_pcie_power_on(uint64_t comphy_base, /* Release from PIPE soft reset * For PCIe by4 or by2: * release from soft reset all lanes - can't use - *read modify write + * read modify write */ - reg_set(HPIPE_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), 0) + + reg_set(HPIPE_ADDR( + COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), 0) + HPIPE_RST_CLK_CTRL_REG, 0x24, 0xffffffff); } else { start_lane = comphy_index; @@ -1677,7 +1733,8 @@ static int mvebu_cp110_comphy_pcie_power_on(uint64_t comphy_base, debug("stage: Check PLL\n"); /* Read lane status */ for (i = start_lane; i < end_lane; i++) { - addr = HPIPE_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), i) + + addr = HPIPE_ADDR( + COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), i) + HPIPE_LANE_STATUS1_REG; data = HPIPE_LANE_STATUS1_PCLK_EN_MASK; mask = data; @@ -1706,10 +1763,12 @@ static int mvebu_cp110_comphy_rxaui_power_on(uint64_t comphy_base, hpipe_addr = HPIPE_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), comphy_index); comphy_addr = COMPHY_ADDR(comphy_base, comphy_index); - sd_ip_addr = SD_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), comphy_index); + sd_ip_addr = SD_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), + comphy_index); /* configure phy selector for RXAUI */ - mvebu_cp110_comphy_set_phy_selector(comphy_base, comphy_index, comphy_mode); + mvebu_cp110_comphy_set_phy_selector(comphy_base, comphy_index, + comphy_mode); /* RFU configurations - hard reset comphy */ mask = COMMON_PHY_CFG1_PWR_UP_MASK; @@ -1790,8 +1849,8 @@ static int mvebu_cp110_comphy_rxaui_power_on(uint64_t comphy_base, 0x0 << HPIPE_PWR_CTR_DTL_FLOOP_EN_OFFSET, HPIPE_PWR_CTR_DTL_FLOOP_EN_MASK); - /* Set analog paramters from ETP(HW) */ - debug("stage: Analog paramters from ETP(HW)\n"); + /* Set analog parameters from ETP(HW) */ + debug("stage: Analog parameters from ETP(HW)\n"); /* SERDES External Configuration 2 */ reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG2_REG, 0x1 << SD_EXTERNAL_CONFIG2_PIN_DFE_EN_OFFSET, @@ -1843,7 +1902,7 @@ static int mvebu_cp110_comphy_rxaui_power_on(uint64_t comphy_base, if (data != 0) { debug("Read from reg = %lx - value = 0x%x\n", sd_ip_addr + SD_EXTERNAL_STATUS0_REG, data); - ERROR("SD_EXTERNAL_STATUS0_PLL_RX is %d, SD_EXTERNAL_STATUS0_PLL_TX is %d\n", + ERROR("SD_EXTERNAL_STATUS0_PLL_RX is %d, -\"-_PLL_TX is %d\n", (data & SD_EXTERNAL_STATUS0_PLL_RX_MASK), (data & SD_EXTERNAL_STATUS0_PLL_TX_MASK)); ret = -ETIMEDOUT; @@ -1890,7 +1949,7 @@ static int mvebu_cp110_comphy_usb3_power_on(uint64_t comphy_base, /* Configure PIPE selector for USB3 */ mvebu_cp110_comphy_set_pipe_selector(comphy_base, comphy_index, - comphy_mode); + comphy_mode); hpipe_addr = HPIPE_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), comphy_index); @@ -2265,7 +2324,8 @@ static int mvebu_cp110_comphy_ap_power_on(uint64_t comphy_base, uint8_t comphy_index) { uint32_t mask, data; - uintptr_t comphy_addr = comphy_addr = COMPHY_ADDR(comphy_base, comphy_index); + uintptr_t comphy_addr = comphy_addr = + COMPHY_ADDR(comphy_base, comphy_index); debug_enter(); debug("stage: RFU configurations - hard reset comphy\n"); @@ -2292,7 +2352,8 @@ int mvebu_cp110_comphy_digital_reset(uint64_t comphy_base, uintptr_t sd_ip_addr; uint32_t mask, data; - sd_ip_addr = SD_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), comphy_index); + sd_ip_addr = SD_ADDR(COMPHY_PIPE_FROM_COMPHY_ADDR(comphy_base), + comphy_index); switch (mode) { case (COMPHY_SGMII_MODE): @@ -2306,7 +2367,7 @@ int mvebu_cp110_comphy_digital_reset(uint64_t comphy_base, reg_set(sd_ip_addr + SD_EXTERNAL_CONFIG1_REG, data, mask); break; default: - ERROR("comphy%d: COMPHY_COMMAND_DIGITAL_PWR_ON/OFF is not supported\n", + ERROR("comphy%d: Digital PWR ON/OFF is not supported\n", comphy_index); return -EINVAL; } @@ -2323,25 +2384,37 @@ int mvebu_cp110_comphy_power_on(uint64_t comphy_base, uint8_t comphy_index, uint switch (mode) { case(COMPHY_SATA_MODE): - err = mvebu_cp110_comphy_sata_power_on(comphy_base, comphy_index, comphy_mode); + err = mvebu_cp110_comphy_sata_power_on(comphy_base, + comphy_index, + comphy_mode); break; case(COMPHY_SGMII_MODE): case(COMPHY_HS_SGMII_MODE): - err = mvebu_cp110_comphy_sgmii_power_on(comphy_base, comphy_index, comphy_mode); + err = mvebu_cp110_comphy_sgmii_power_on(comphy_base, + comphy_index, + comphy_mode); break; /* From comphy perspective, XFI and SFI are the same */ case (COMPHY_XFI_MODE): case (COMPHY_SFI_MODE): - err = mvebu_cp110_comphy_xfi_power_on(comphy_base, comphy_index, comphy_mode); + err = mvebu_cp110_comphy_xfi_power_on(comphy_base, + comphy_index, + comphy_mode); break; case (COMPHY_PCIE_MODE): - err = mvebu_cp110_comphy_pcie_power_on(comphy_base, comphy_index, comphy_mode); + err = mvebu_cp110_comphy_pcie_power_on(comphy_base, + comphy_index, + comphy_mode); break; case (COMPHY_RXAUI_MODE): - err = mvebu_cp110_comphy_rxaui_power_on(comphy_base, comphy_index, comphy_mode); + err = mvebu_cp110_comphy_rxaui_power_on(comphy_base, + comphy_index, + comphy_mode); case (COMPHY_USB3H_MODE): case (COMPHY_USB3D_MODE): - err = mvebu_cp110_comphy_usb3_power_on(comphy_base, comphy_index, comphy_mode); + err = mvebu_cp110_comphy_usb3_power_on(comphy_base, + comphy_index, + comphy_mode); break; case (COMPHY_AP_MODE): err = mvebu_cp110_comphy_ap_power_on(comphy_base, comphy_index); diff --git a/drivers/marvell/dw-pcie-ep.c b/drivers/marvell/dw-pcie-ep.c index 7aa7a754..373d1dbc 100644 --- a/drivers/marvell/dw-pcie-ep.c +++ b/drivers/marvell/dw-pcie-ep.c @@ -4,8 +4,9 @@ * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -#include <plat_def.h> + #include <mmio.h> +#include <mvebu_def.h> #define PCIE_CFG_VENDOR 0x0 #define PCIE_CFG_DEVICE 0x2 diff --git a/drivers/marvell/eawg.c b/drivers/marvell/eawg.c index 178fa4db..529867c4 100644 --- a/drivers/marvell/eawg.c +++ b/drivers/marvell/eawg.c @@ -8,8 +8,8 @@ #include <debug.h> #include <eawg.h> #include <mmio.h> +#include <mvebu_def.h> #include <stdio.h> -#include <plat_def.h> #define EAWG_BASE_REGS(ap) MVEBU_AR_RFU_BASE(ap) + 0x6000 #define EAWG_WRITE_ADDR_REG(ap) (EAWG_BASE_REGS(ap) + 0x0) diff --git a/drivers/marvell/gwin.c b/drivers/marvell/gwin.c index 07b34481..d09375d3 100644 --- a/drivers/marvell/gwin.c +++ b/drivers/marvell/gwin.c @@ -1,16 +1,18 @@ /* - * Copyright (C) 2017, 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ +/* GWIN unit device driver for Marvell AP810 SoC */ + +#include <armada_common.h> #include <debug.h> #include <gwin.h> #include <mmio.h> #include <mvebu.h> -#include <plat_config.h> -#include <plat_def.h> +#include <mvebu_def.h> #if LOG_LEVEL >= LOG_LEVEL_INFO #define DEBUG_ADDR_MAP @@ -20,7 +22,8 @@ #define WIN_ENABLE_BIT (0x1) #define WIN_TARGET_MASK (0xF) #define WIN_TARGET_SHIFT (0x8) -#define WIN_TARGET(tgt) (((tgt) & WIN_TARGET_MASK) << WIN_TARGET_SHIFT) +#define WIN_TARGET(tgt) (((tgt) & WIN_TARGET_MASK) \ + << WIN_TARGET_SHIFT) /* Bits[43:26] of the physical address are the window base, * which is aligned to 64MB @@ -30,9 +33,12 @@ #define GWIN_ALIGNMENT_64M (0x4000000) /* AP registers */ -#define GWIN_CR_OFFSET(ap, win) (MVEBU_GWIN_BASE(ap) + 0x0 + (0x10 * (win))) -#define GWIN_ALR_OFFSET(ap, win) (MVEBU_GWIN_BASE(ap) + 0x8 + (0x10 * (win))) -#define GWIN_AHR_OFFSET(ap, win) (MVEBU_GWIN_BASE(ap) + 0xc + (0x10 * (win))) +#define GWIN_CR_OFFSET(ap, win) (MVEBU_GWIN_BASE(ap) + 0x0 + \ + (0x10 * (win))) +#define GWIN_ALR_OFFSET(ap, win) (MVEBU_GWIN_BASE(ap) + 0x8 + \ + (0x10 * (win))) +#define GWIN_AHR_OFFSET(ap, win) (MVEBU_GWIN_BASE(ap) + 0xc + \ + (0x10 * (win))) #define CCU_GRU_CR_OFFSET(ap) (MVEBU_CCU_GRU_BASE(ap)) #define CCR_GRU_CR_GWIN_MBYPASS (1 << 1) @@ -42,17 +48,20 @@ static void gwin_check(struct addr_map_win *win) /* The base is always 64M aligned */ if (IS_NOT_ALIGN(win->base_addr, GWIN_ALIGNMENT_64M)) { win->base_addr &= ~(GWIN_ALIGNMENT_64M - 1); - NOTICE("%s: Align the base address to 0x%llx\n", __func__, win->base_addr); + NOTICE("%s: Align the base address to 0x%llx\n", + __func__, win->base_addr); } /* size parameter validity check */ if (IS_NOT_ALIGN(win->win_size, GWIN_ALIGNMENT_64M)) { win->win_size = ALIGN_UP(win->win_size, GWIN_ALIGNMENT_64M); - NOTICE("%s: Aligning window size to 0x%llx\n", __func__, win->win_size); + NOTICE("%s: Aligning window size to 0x%llx\n", + __func__, win->win_size); } } -static void gwin_enable_window(int ap_index, struct addr_map_win *win, uint32_t win_num) +static void gwin_enable_window(int ap_index, struct addr_map_win *win, + uint32_t win_num) { uint32_t alr, ahr; uint64_t end_addr; @@ -117,6 +126,7 @@ void gwin_temp_win_remove(int ap_index, struct addr_map_win *win, int size) for (int i = 0; i < size; i++) { uint64_t base; uint32_t target; + win_id = MVEBU_GWIN_MAX_WINS - i - 1; target = mmio_read_32(GWIN_CR_OFFSET(ap_index, win_id)); @@ -128,7 +138,8 @@ void gwin_temp_win_remove(int ap_index, struct addr_map_win *win, int size) base <<= ADDRESS_RSHIFT; if (win->target_id != target) { - ERROR("%s: Trying to remove bad window-%d!\n", __func__, win_id); + ERROR("%s: Trying to remove bad window-%d!\n", + __func__, win_id); continue; } gwin_disable_window(ap_index, win_id); @@ -142,8 +153,8 @@ static void dump_gwin(int ap_index) uint32_t win_num; /* Dump all GWIN windows */ - printf("\tbank target start end\n"); - printf("\t----------------------------------------------------\n"); + tf_printf("\tbank target start end\n"); + tf_printf("\t----------------------------------------------------\n"); for (win_num = 0; win_num < MVEBU_GWIN_MAX_WINS; win_num++) { uint32_t cr; uint64_t alr, ahr; @@ -155,10 +166,10 @@ static void dump_gwin(int ap_index) alr = (alr >> ADDRESS_LSHIFT) << ADDRESS_RSHIFT; ahr = mmio_read_32(GWIN_AHR_OFFSET(ap_index, win_num)); ahr = (ahr >> ADDRESS_LSHIFT) << ADDRESS_RSHIFT; - printf("\tgwin %d 0x%016llx 0x%016llx\n", (cr >> 8) & 0xF, alr, ahr); + tf_printf("\tgwin %d 0x%016llx 0x%016llx\n", + (cr >> 8) & 0xF, alr, ahr); } } - return; } #endif @@ -179,7 +190,8 @@ int init_gwin(int ap_index) } if (win_count > MVEBU_GWIN_MAX_WINS) { - ERROR("number of windows is bigger than %d\n", MVEBU_GWIN_MAX_WINS); + ERROR("number of windows is bigger than %d\n", + MVEBU_GWIN_MAX_WINS); return 0; } diff --git a/drivers/marvell/i2c/a8k_i2c.c b/drivers/marvell/i2c/a8k_i2c.c index 2ebdec8b..72a77316 100644 --- a/drivers/marvell/i2c/a8k_i2c.c +++ b/drivers/marvell/i2c/a8k_i2c.c @@ -1,59 +1,55 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ - -/* This driver provides I2C support for A8K */ + +/* This driver provides I2C support for Marvell A8K and compatible SoCs */ #include <a8k_i2c.h> #include <debug.h> #include <delay_timer.h> +#include <errno.h> #include <mmio.h> -#include <plat_def.h> +#include <mvebu_def.h> #if LOG_LEVEL >= LOG_LEVEL_VERBOSE #define DEBUG_I2C #endif -#define CONFIG_SYS_TCLK 250000000 -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 0x0 -#define I2C_TIMEOUT_VALUE 0x500 -#define I2C_MAX_RETRY_CNT 1000 -#define I2C_CMD_WRITE 0x0 -#define I2C_CMD_READ 0x1 - -#define I2C_DATA_ADDR_7BIT_OFFS 0x1 -#define I2C_DATA_ADDR_7BIT_MASK (0xFF << I2C_DATA_ADDR_7BIT_OFFS) - -#define I2C_CONTROL_ACK 0x00000004 -#define I2C_CONTROL_IFLG 0x00000008 -#define I2C_CONTROL_STOP 0x00000010 -#define I2C_CONTROL_START 0x00000020 -#define I2C_CONTROL_TWSIEN 0x00000040 -#define I2C_CONTROL_INTEN 0x00000080 - -#define I2C_STATUS_START 0x08 -#define I2C_STATUS_REPEATED_START 0x10 -#define I2C_STATUS_ADDR_W_ACK 0x18 -#define I2C_STATUS_DATA_W_ACK 0x28 +#define CONFIG_SYS_TCLK 250000000 +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 0x0 +#define I2C_TIMEOUT_VALUE 0x500 +#define I2C_MAX_RETRY_CNT 1000 +#define I2C_CMD_WRITE 0x0 +#define I2C_CMD_READ 0x1 + +#define I2C_DATA_ADDR_7BIT_OFFS 0x1 +#define I2C_DATA_ADDR_7BIT_MASK (0xFF << I2C_DATA_ADDR_7BIT_OFFS) + +#define I2C_CONTROL_ACK 0x00000004 +#define I2C_CONTROL_IFLG 0x00000008 +#define I2C_CONTROL_STOP 0x00000010 +#define I2C_CONTROL_START 0x00000020 +#define I2C_CONTROL_TWSIEN 0x00000040 +#define I2C_CONTROL_INTEN 0x00000080 + +#define I2C_STATUS_START 0x08 +#define I2C_STATUS_REPEATED_START 0x10 +#define I2C_STATUS_ADDR_W_ACK 0x18 +#define I2C_STATUS_DATA_W_ACK 0x28 #define I2C_STATUS_LOST_ARB_DATA_ADDR_TRANSFER 0x38 -#define I2C_STATUS_ADDR_R_ACK 0x40 -#define I2C_STATUS_DATA_R_ACK 0x50 -#define I2C_STATUS_DATA_R_NAK 0x58 +#define I2C_STATUS_ADDR_R_ACK 0x40 +#define I2C_STATUS_DATA_R_ACK 0x50 +#define I2C_STATUS_DATA_R_NAK 0x58 #define I2C_STATUS_LOST_ARB_GENERAL_CALL 0x78 -#define I2C_STATUS_IDLE 0xF8 +#define I2C_STATUS_IDLE 0xF8 #define I2C_UNSTUCK_TRIGGER 0x1 #define I2C_UNSTUCK_ONGOING 0x2 #define I2C_UNSTUCK_ERROR 0x4 - -#define EPERM 1 /* Operation not permitted */ -#define EAGAIN 11 /* Try again */ -#define ETIMEDOUT 110 /* Connection timed out */ - struct marvell_i2c_regs { uint32_t slave_address; uint32_t data; @@ -74,7 +70,8 @@ static struct marvell_i2c_regs *base; static int marvell_i2c_lost_arbitration(uint32_t *status) { *status = mmio_read_32((uintptr_t)&base->u.status); - if ((I2C_STATUS_LOST_ARB_DATA_ADDR_TRANSFER == *status) || (I2C_STATUS_LOST_ARB_GENERAL_CALL == *status)) + if ((*status == I2C_STATUS_LOST_ARB_DATA_ADDR_TRANSFER) || + (*status == I2C_STATUS_LOST_ARB_GENERAL_CALL)) return -EAGAIN; return 0; @@ -89,8 +86,6 @@ static void marvell_i2c_interrupt_clear(void) mmio_write_32((uintptr_t)&base->control, reg); /* Wait for 1 us for the clear to take effect */ udelay(1); - - return; } static int marvell_i2c_interrupt_get(void) @@ -106,6 +101,7 @@ static int marvell_i2c_interrupt_get(void) static int marvell_i2c_wait_interrupt(void) { uint32_t timeout = 0; + while (!marvell_i2c_interrupt_get() && (timeout++ < I2C_TIMEOUT_VALUE)) ; if (timeout >= I2C_TIMEOUT_VALUE) @@ -123,7 +119,9 @@ static int marvell_i2c_start_bit_set(void) is_int_flag = 1; /* set start bit */ - mmio_write_32((uintptr_t)&base->control, mmio_read_32((uintptr_t)&base->control) | I2C_CONTROL_START); + mmio_write_32((uintptr_t)&base->control, + mmio_read_32((uintptr_t)&base->control) | + I2C_CONTROL_START); /* in case that the int flag was set before i.e. repeated start bit */ if (is_int_flag) { @@ -137,17 +135,20 @@ static int marvell_i2c_start_bit_set(void) } /* check that start bit went down */ - if ((mmio_read_32((uintptr_t)&base->control) & I2C_CONTROL_START) != 0) { + if ((mmio_read_32((uintptr_t)&base->control) & + I2C_CONTROL_START) != 0) { ERROR("Start bit didn't went down\n"); return -EPERM; } /* check the status */ if (marvell_i2c_lost_arbitration(&status)) { - ERROR("%s - %d: Lost arbitration, got status %x\n", __func__, __LINE__, status); + ERROR("%s - %d: Lost arbitration, got status %x\n", + __func__, __LINE__, status); return -EAGAIN; } - if ((status != I2C_STATUS_START) && (status != I2C_STATUS_REPEATED_START)) { + if ((status != I2C_STATUS_START) && + (status != I2C_STATUS_REPEATED_START)) { ERROR("Got status %x after enable start bit.\n", status); return -EPERM; } @@ -161,12 +162,15 @@ static int marvell_i2c_stop_bit_set(void) uint32_t status; /* Generate stop bit */ - mmio_write_32((uintptr_t)&base->control, mmio_read_32((uintptr_t)&base->control) | I2C_CONTROL_STOP); + mmio_write_32((uintptr_t)&base->control, + mmio_read_32((uintptr_t)&base->control) | + I2C_CONTROL_STOP); marvell_i2c_interrupt_clear(); timeout = 0; /* Read control register, check the control stop bit */ - while ((mmio_read_32((uintptr_t)&base->control) & I2C_CONTROL_STOP) && (timeout++ < I2C_TIMEOUT_VALUE)) + while ((mmio_read_32((uintptr_t)&base->control) & I2C_CONTROL_STOP) && + (timeout++ < I2C_TIMEOUT_VALUE)) ; if (timeout >= I2C_TIMEOUT_VALUE) { ERROR("Stop bit didn't went down\n"); @@ -181,7 +185,8 @@ static int marvell_i2c_stop_bit_set(void) /* check the status */ if (marvell_i2c_lost_arbitration(&status)) { - ERROR("%s - %d: Lost arbitration, got status %x\n", __func__, __LINE__, status); + ERROR("%s - %d: Lost arbitration, got status %x\n", + __func__, __LINE__, status); return -EAGAIN; } if (status != I2C_STATUS_IDLE) { @@ -210,15 +215,18 @@ static int marvell_i2c_address_set(uint8_t chain, int command) /* check the status */ if (marvell_i2c_lost_arbitration(&status)) { - ERROR("%s - %d: Lost arbitration, got status %x\n", __func__, __LINE__, status); + ERROR("%s - %d: Lost arbitration, got status %x\n", + __func__, __LINE__, status); return -EAGAIN; } if (((status != I2C_STATUS_ADDR_R_ACK) && (command == I2C_CMD_READ)) || ((status != I2C_STATUS_ADDR_W_ACK) && (command == I2C_CMD_WRITE))) { - /* only in debug, since in boot we try to read the SPD of both DRAM, and we don't - want error messages in case DIMM doesn't exist. */ - INFO("%s: ERROR - status %x addr in %s mode.\n", __func__, status, (command == I2C_CMD_WRITE) ? - "Write" : "Read"); + /* only in debug, since in boot we try to read the SPD + * of both DRAM, and we don't want error messages in cas + * DIMM doesn't exist. + */ + INFO("%s: ERROR - status %x addr in %s mode.\n", __func__, + status, (command == I2C_CMD_WRITE) ? "Write" : "Read"); return -EPERM; } @@ -245,21 +253,23 @@ static unsigned int marvell_i2c_bus_speed_set(unsigned int requested_speed) unsigned int actual_n = 0, actual_m = 0; int val; - /* Calucalte N and M for the TWSI clock baud rate */ + /* Calculate N and M for the TWSI clock baud rate */ for (n = 0; n < 8; n++) { for (m = 0; m < 16; m++) { freq = CONFIG_SYS_TCLK / (10 * (m + 1) * (2 << n)); val = requested_speed - freq; margin = (val > 0) ? val : -val; - if ((freq <= requested_speed) && (margin < min_margin)) { + if ((freq <= requested_speed) && + (margin < min_margin)) { min_margin = margin; actual_n = n; actual_m = m; } } } - VERBOSE("%s: actual_n = %u, actual_m = %u\n", __func__, actual_n, actual_m); + VERBOSE("%s: actual_n = %u, actual_m = %u\n", + __func__, actual_n, actual_m); /* Set the baud rate */ mmio_write_32((uintptr_t)&base->u.baudrate, (actual_m << 3) | actual_n); @@ -274,14 +284,16 @@ static int marvell_i2c_probe(uint8_t chip) ret = marvell_i2c_start_bit_set(); if (ret != 0) { marvell_i2c_stop_bit_set(); - ERROR("%s - %d: %s", __func__, __LINE__, "marvell_i2c_start_bit_set failed\n"); + ERROR("%s - %d: %s", __func__, __LINE__, + "marvell_i2c_start_bit_set failed\n"); return -EPERM; } ret = marvell_i2c_address_set(chip, I2C_CMD_WRITE); if (ret != 0) { marvell_i2c_stop_bit_set(); - ERROR("%s - %d: %s", __func__, __LINE__, "marvell_i2c_address_set failed\n"); + ERROR("%s - %d: %s", __func__, __LINE__, + "marvell_i2c_address_set failed\n"); return -EPERM; } @@ -317,21 +329,25 @@ static int marvell_i2c_data_receive(uint8_t *p_block, uint32_t block_size) } /* check the status */ if (marvell_i2c_lost_arbitration(&status)) { - ERROR("%s - %d: Lost arbitration, got status %x\n", __func__, __LINE__, status); + ERROR("%s - %d: Lost arbitration, got status %x\n", + __func__, __LINE__, status); return -EAGAIN; } - if ((status != I2C_STATUS_DATA_R_ACK) && (block_size_read != 1)) { + if ((status != I2C_STATUS_DATA_R_ACK) && + (block_size_read != 1)) { ERROR("Status %x in read transaction\n", status); return -EPERM; } - if ((status != I2C_STATUS_DATA_R_NAK) && (block_size_read == 1)) { + if ((status != I2C_STATUS_DATA_R_NAK) && + (block_size_read == 1)) { ERROR("Status %x in Rd Terminate\n", status); return -EPERM; } /* read the data */ *p_block = (uint8_t) mmio_read_32((uintptr_t)&base->data); - VERBOSE("%s: place %d read %x\n", __func__, block_size - block_size_read, *p_block); + VERBOSE("%s: place %d read %x\n", __func__, + block_size - block_size_read, *p_block); p_block++; block_size_read--; } @@ -351,7 +367,8 @@ static int marvell_i2c_data_transmit(uint8_t *p_block, uint32_t block_size) while (block_size_write) { /* write the data */ mmio_write_32((uintptr_t)&base->data, (uint32_t) *p_block); - VERBOSE("%s: index = %d, data = %x\n", __func__, block_size - block_size_write, *p_block); + VERBOSE("%s: index = %d, data = %x\n", __func__, + block_size - block_size_write, *p_block); p_block++; block_size_write--; @@ -364,7 +381,8 @@ static int marvell_i2c_data_transmit(uint8_t *p_block, uint32_t block_size) /* check the status */ if (marvell_i2c_lost_arbitration(&status)) { - ERROR("%s - %d: Lost arbitration, got status %x\n", __func__, __LINE__, status); + ERROR("%s - %d: Lost arbitration, got status %x\n", + __func__, __LINE__, status); return -EAGAIN; } if (status != I2C_STATUS_DATA_W_ACK) { @@ -389,7 +407,8 @@ static int marvell_i2c_target_offset_set(uint8_t chip, uint32_t addr, int alen) off_block[0] = addr & 0xff; off_size = 1; } - VERBOSE("%s: off_size = %x addr1 = %x addr2 = %x\n", __func__, off_size, off_block[0], off_block[1]); + VERBOSE("%s: off_size = %x addr1 = %x addr2 = %x\n", __func__, + off_size, off_block[0], off_block[1]); return marvell_i2c_data_transmit(off_block, off_size); } @@ -417,13 +436,13 @@ static int marvell_i2c_unstuck(int ret) return ret; } -/* +/* * API Functions */ void i2c_init(void *i2c_base) { /* For I2C speed and slave address, now we do not set them since - * we just provide the working speed and slave address in plat_def.h + * we just provide the working speed and slave address in mvebu_def.h * for i2c_init */ base = (struct marvell_i2c_regs *)i2c_base; @@ -436,14 +455,17 @@ void i2c_init(void *i2c_base) marvell_i2c_bus_speed_set(CONFIG_SYS_I2C_SPEED); /* Enable the I2C and slave */ - mmio_write_32((uintptr_t)&base->control, I2C_CONTROL_TWSIEN | I2C_CONTROL_ACK); + mmio_write_32((uintptr_t)&base->control, + I2C_CONTROL_TWSIEN | I2C_CONTROL_ACK); /* set the I2C slave address */ mmio_write_32((uintptr_t)&base->xtnd_slave_addr, 0); mmio_write_32((uintptr_t)&base->slave_address, CONFIG_SYS_I2C_SLAVE); /* unmask I2C interrupt */ - mmio_write_32((uintptr_t)&base->control, mmio_read_32((uintptr_t)&base->control) | I2C_CONTROL_INTEN); + mmio_write_32((uintptr_t)&base->control, + mmio_read_32((uintptr_t)&base->control) | + I2C_CONTROL_INTEN); udelay(10); } @@ -472,7 +494,8 @@ int i2c_read(uint8_t chip, uint32_t addr, int alen, uint8_t *buffer, int len) do { if (ret != -EAGAIN && ret) { - ERROR("i2c transaction failed, after %d retries\n", counter); + ERROR("i2c transaction failed, after %d retries\n", + counter); marvell_i2c_stop_bit_set(); return ret; } @@ -514,10 +537,13 @@ int i2c_read(uint8_t chip, uint32_t addr, int alen, uint8_t *buffer, int len) } while ((ret == -EAGAIN) && (counter < I2C_MAX_RETRY_CNT)); if (counter == I2C_MAX_RETRY_CNT) { - ERROR("I2C transactions failed, got EAGAIN %d times\n", I2C_MAX_RETRY_CNT); + ERROR("I2C transactions failed, got EAGAIN %d times\n", + I2C_MAX_RETRY_CNT); ret = -EPERM; } - mmio_write_32((uintptr_t)&base->control, mmio_read_32((uintptr_t)&base->control) | I2C_CONTROL_ACK); + mmio_write_32((uintptr_t)&base->control, + mmio_read_32((uintptr_t)&base->control) | + I2C_CONTROL_ACK); udelay(1); return ret; @@ -577,7 +603,8 @@ int i2c_write(uint8_t chip, uint32_t addr, int alen, uint8_t *buffer, int len) } while ((ret == -EAGAIN) && (counter < I2C_MAX_RETRY_CNT)); if (counter == I2C_MAX_RETRY_CNT) { - ERROR("I2C transactions failed, got EAGAIN %d times\n", I2C_MAX_RETRY_CNT); + ERROR("I2C transactions failed, got EAGAIN %d times\n", + I2C_MAX_RETRY_CNT); ret = -EPERM; } diff --git a/drivers/marvell/icu.c b/drivers/marvell/icu.c index 144dfc86..20d46a1b 100644 --- a/drivers/marvell/icu.c +++ b/drivers/marvell/icu.c @@ -7,7 +7,7 @@ #include <icu.h> #include <mmio.h> -#include <plat_def.h> +#include <mvebu_def.h> #define ICU_SET_SPI_AL(x) (0x10 + (0x10 * x)) #define ICU_SET_SPI_AH(x) (0x14 + (0x10 * x)) diff --git a/drivers/marvell/io_win.c b/drivers/marvell/io_win.c index 164cbbb8..b8f09776 100644 --- a/drivers/marvell/io_win.c +++ b/drivers/marvell/io_win.c @@ -1,16 +1,18 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ +/* IO Window unit device driver for Marvell AP807, AP807 and AP810 SoCs */ + +#include <armada_common.h> #include <debug.h> #include <io_win.h> #include <mmio.h> #include <mvebu.h> -#include <plat_config.h> -#include <plat_def.h> +#include <mvebu_def.h> #if LOG_LEVEL >= LOG_LEVEL_INFO #define DEBUG_ADDR_MAP @@ -25,9 +27,12 @@ #define IO_WIN_ALIGNMENT_64K (0x10000) /* AP registers */ -#define IO_WIN_ALR_OFFSET(ap, win) (MVEBU_IO_WIN_BASE(ap) + 0x0 + (0x10 * win)) -#define IO_WIN_AHR_OFFSET(ap, win) (MVEBU_IO_WIN_BASE(ap) + 0x8 + (0x10 * win)) -#define IO_WIN_CR_OFFSET(ap, win) (MVEBU_IO_WIN_BASE(ap) + 0xC + (0x10 * win)) +#define IO_WIN_ALR_OFFSET(ap, win) (MVEBU_IO_WIN_BASE(ap) + 0x0 + \ + (0x10 * win)) +#define IO_WIN_AHR_OFFSET(ap, win) (MVEBU_IO_WIN_BASE(ap) + 0x8 + \ + (0x10 * win)) +#define IO_WIN_CR_OFFSET(ap, win) (MVEBU_IO_WIN_BASE(ap) + 0xC + \ + (0x10 * win)) /* For storage of CR, ALR, AHR abd GCR */ static uint32_t io_win_regs_save[MVEBU_IO_WIN_MAX_WINS * 3 + 1]; @@ -38,17 +43,20 @@ static void io_win_check(struct addr_map_win *win) /* check if address is aligned to 1M */ if (IS_NOT_ALIGN(win->base_addr, IO_WIN_ALIGNMENT_1M)) { win->base_addr = ALIGN_UP(win->base_addr, IO_WIN_ALIGNMENT_1M); - NOTICE("%s: Align up the base address to 0x%llx\n", __func__, win->base_addr); + NOTICE("%s: Align up the base address to 0x%llx\n", + __func__, win->base_addr); } /* size parameter validity check */ if (IS_NOT_ALIGN(win->win_size, IO_WIN_ALIGNMENT_1M)) { win->win_size = ALIGN_UP(win->win_size, IO_WIN_ALIGNMENT_1M); - NOTICE("%s: Aligning size to 0x%llx\n", __func__, win->win_size); + NOTICE("%s: Aligning size to 0x%llx\n", + __func__, win->win_size); } } -static void io_win_enable_window(int ap_index, struct addr_map_win *win, uint32_t win_num) +static void io_win_enable_window(int ap_index, struct addr_map_win *win, + uint32_t win_num) { uint32_t alr, ahr; uint64_t end_addr; @@ -124,6 +132,7 @@ void iow_temp_win_remove(int ap_index, struct addr_map_win *win, int size) for (int i = 0; i < size; i++) { uint64_t base; uint32_t target; + win_id = MVEBU_IO_WIN_MAX_WINS - i - 1; target = mmio_read_32(IO_WIN_CR_OFFSET(ap_index, win_id)); @@ -132,7 +141,8 @@ void iow_temp_win_remove(int ap_index, struct addr_map_win *win, int size) base <<= ADDRESS_SHIFT; if ((win->target_id != target) || (win->base_addr != base)) { - ERROR("%s: Trying to remove bad window-%d!\n", __func__, win_id); + ERROR("%s: Trying to remove bad window-%d!\n", + __func__, win_id); continue; } io_win_disable_window(ap_index, win_id); @@ -148,26 +158,29 @@ static void dump_io_win(int ap_index) uint64_t start, end; /* Dump all IO windows */ - printf("\tbank target start end\n"); - printf("\t----------------------------------------------------\n"); + tf_printf("\tbank target start end\n"); + tf_printf("\t----------------------------------------------------\n"); for (win_id = 0; win_id < MVEBU_IO_WIN_MAX_WINS; win_id++) { alr = mmio_read_32(IO_WIN_ALR_OFFSET(ap_index, win_id)); if (alr & WIN_ENABLE_BIT) { alr &= ~WIN_ENABLE_BIT; ahr = mmio_read_32(IO_WIN_AHR_OFFSET(ap_index, win_id)); - trgt_id = mmio_read_32(IO_WIN_CR_OFFSET(ap_index, win_id)); + trgt_id = mmio_read_32(IO_WIN_CR_OFFSET(ap_index, + win_id)); start = ((uint64_t)alr << ADDRESS_SHIFT); end = (((uint64_t)ahr + 0x10) << ADDRESS_SHIFT); - printf("\tio-win %d 0x%016llx 0x%016llx\n", trgt_id, start, end); + tf_printf("\tio-win %d 0x%016llx 0x%016llx\n", + trgt_id, start, end); } } - printf("\tio-win gcr is %x\n", mmio_read_32(MVEBU_IO_WIN_BASE(ap_index) + MVEBU_IO_WIN_GCR_OFFSET)); - - return; + tf_printf("\tio-win gcr is %x\n", + mmio_read_32(MVEBU_IO_WIN_BASE(ap_index) + + MVEBU_IO_WIN_GCR_OFFSET)); } #endif -static void iow_save_win_range(int ap_id, int win_first, int win_last, uint32_t *buffer) +static void iow_save_win_range(int ap_id, int win_first, int win_last, + uint32_t *buffer) { int win_id, idx; @@ -181,7 +194,8 @@ static void iow_save_win_range(int ap_id, int win_first, int win_last, uint32_t MVEBU_IO_WIN_GCR_OFFSET); } -static void iow_restore_win_range(int ap_id, int win_first, int win_last, uint32_t *buffer) +static void iow_restore_win_range(int ap_id, int win_first, int win_last, + uint32_t *buffer) { int win_id, idx; @@ -197,12 +211,14 @@ static void iow_restore_win_range(int ap_id, int win_first, int win_last, uint32 void iow_save_win_all(int ap_id) { - iow_save_win_range(ap_id, 0, MVEBU_IO_WIN_MAX_WINS - 1, io_win_regs_save); + iow_save_win_range(ap_id, 0, MVEBU_IO_WIN_MAX_WINS - 1, + io_win_regs_save); } void iow_restore_win_all(int ap_id) { - iow_restore_win_range(ap_id, 0, MVEBU_IO_WIN_MAX_WINS - 1, io_win_regs_save); + iow_restore_win_range(ap_id, 0, MVEBU_IO_WIN_MAX_WINS - 1, + io_win_regs_save); } int init_io_win(int ap_index) @@ -219,19 +235,23 @@ int init_io_win(int ap_index) INFO("no windows configurations found\n"); if (win_count > MVEBU_IO_WIN_MAX_WINS) { - INFO("number of windows is bigger than %d\n", MVEBU_IO_WIN_MAX_WINS); + INFO("number of windows is bigger than %d\n", + MVEBU_IO_WIN_MAX_WINS); return 0; } /* Get the default target id to set the GCR */ win_reg = marvell_get_io_win_gcr_target(ap_index); - mmio_write_32(MVEBU_IO_WIN_BASE(ap_index) + MVEBU_IO_WIN_GCR_OFFSET, win_reg); + mmio_write_32(MVEBU_IO_WIN_BASE(ap_index) + MVEBU_IO_WIN_GCR_OFFSET, + win_reg); /* disable all IO windows */ for (win_id = 1; win_id < MVEBU_IO_WIN_MAX_WINS; win_id++) io_win_disable_window(ap_index, win_id); - /* enable relevant windows, starting from win_id=1 because index 0 dedicated for BootRom */ + /* enable relevant windows, starting from win_id = 1 because + * index 0 dedicated for BootROM + */ for (win_id = 1; win_id <= win_count; win_id++, win++) { io_win_check(win); io_win_enable_window(ap_index, win, win_id); diff --git a/drivers/marvell/iob.c b/drivers/marvell/iob.c index 343a7cb4..0a30287f 100644 --- a/drivers/marvell/iob.c +++ b/drivers/marvell/iob.c @@ -5,13 +5,15 @@ * https://spdx.org/licenses */ +/* IOW unit device driver for Marvell CP110 and CP115 SoCs */ + +#include <armada_common.h> #include <arch_helpers.h> #include <debug.h> #include <iob.h> #include <mmio.h> #include <mvebu.h> -#include <plat_config.h> -#include <plat_def.h> +#include <mvebu_def.h> #if LOG_LEVEL >= LOG_LEVEL_INFO #define DEBUG_ADDR_MAP @@ -48,15 +50,18 @@ static void iob_win_check(struct addr_map_win *win, uint32_t win_num) /* check if address is aligned to the size */ if (IS_NOT_ALIGN(win->base_addr, IOB_WIN_ALIGNMENT)) { win->base_addr = ALIGN_UP(win->base_addr, IOB_WIN_ALIGNMENT); - ERROR("Window %d: base address unaligned to 0x%x\n", win_num, IOB_WIN_ALIGNMENT); - printf("Align up the base address to 0x%llx\n", win->base_addr); + ERROR("Window %d: base address unaligned to 0x%x\n", + win_num, IOB_WIN_ALIGNMENT); + tf_printf("Align up the base address to 0x%llx\n", + win->base_addr); } /* size parameter validity check */ if (IS_NOT_ALIGN(win->win_size, IOB_WIN_ALIGNMENT)) { win->win_size = ALIGN_UP(win->win_size, IOB_WIN_ALIGNMENT); - ERROR("Window %d: window size unaligned to 0x%x\n", win_num, IOB_WIN_ALIGNMENT); - printf("Aligning size to 0x%llx\n", win->win_size); + ERROR("Window %d: window size unaligned to 0x%x\n", win_num, + IOB_WIN_ALIGNMENT); + tf_printf("Aligning size to 0x%llx\n", win->win_size); } } @@ -74,7 +79,8 @@ static void iob_enable_win(struct addr_map_win *win, uint32_t win_id) mmio_write_32(IOB_WIN_AHR_OFFSET(win_id), ahr); iob_win_reg = WIN_ENABLE_BIT; - iob_win_reg |= (win->target_id & IOB_TARGET_ID_MASK) << IOB_TARGET_ID_OFFSET; + iob_win_reg |= (win->target_id & IOB_TARGET_ID_MASK) + << IOB_TARGET_ID_OFFSET; mmio_write_32(IOB_WIN_CR_OFFSET(win_id), iob_win_reg); } @@ -85,16 +91,18 @@ static void dump_iob(void) uint32_t win_id, win_cr, alr, ahr; uint8_t target_id; uint64_t start, end; - char *iob_target_name[IOB_MAX_TID] = {"CFG ", "MCI0 ", "PEX1 ", "PEX2 ", - "PEX0 ", "NAND ", "RUNIT", "MCI1 "}; + char *iob_target_name[IOB_MAX_TID] = { + "CFG ", "MCI0 ", "PEX1 ", "PEX2 ", + "PEX0 ", "NAND ", "RUNIT", "MCI1 " }; /* Dump all IOB windows */ - printf("bank id target start end\n"); - printf("----------------------------------------------------\n"); + tf_printf("bank id target start end\n"); + tf_printf("----------------------------------------------------\n"); for (win_id = 0; win_id < MVEBU_IOB_MAX_WINS; win_id++) { win_cr = mmio_read_32(IOB_WIN_CR_OFFSET(win_id)); if (win_cr & WIN_ENABLE_BIT) { - target_id = (win_cr >> IOB_TARGET_ID_OFFSET) & IOB_TARGET_ID_MASK; + target_id = (win_cr >> IOB_TARGET_ID_OFFSET) & + IOB_TARGET_ID_MASK; alr = mmio_read_32(IOB_WIN_ALR_OFFSET(win_id)); start = ((uint64_t)alr << ADDRESS_SHIFT); if (win_id != 0) { @@ -102,31 +110,33 @@ static void dump_iob(void) end = (((uint64_t)ahr + 0x10) << ADDRESS_SHIFT); } else { /* Window #0 size is hardcoded to 16MB, as it's - ** reserved for CP configuration space. */ + * reserved for CP configuration space. + */ end = start + (16 << 20); } - printf("iob %02d %s 0x%016llx 0x%016llx\n" - , win_id, iob_target_name[target_id], start, end); + tf_printf("iob %02d %s 0x%016llx 0x%016llx\n", + win_id, iob_target_name[target_id], + start, end); } } - - return; } #endif -void iob_cfg_space_update(int ap_idx, int cp_idx, uintptr_t base, uintptr_t new_base) +void iob_cfg_space_update(int ap_idx, int cp_idx, uintptr_t base, + uintptr_t new_base) { debug_enter(); iob_base = base + MVEBU_IOB_OFFSET; - NOTICE("Change the base address of AP%d-CP%d to %lx\n", ap_idx, cp_idx, new_base); + NOTICE("Change the base address of AP%d-CP%d to %lx\n", + ap_idx, cp_idx, new_base); mmio_write_32(IOB_WIN_ALR_OFFSET(0), new_base >> ADDRESS_SHIFT); iob_base = new_base + MVEBU_IOB_OFFSET; /* Make sure the address was configured by the CPU before - * any possibe access to the CP. + * any possible access to the CP. */ dsb(); @@ -150,12 +160,14 @@ int init_iob(uintptr_t base) INFO("no windows configurations found\n"); return 0; } else if (win_count > (MVEBU_IOB_MAX_WINS - 1)) { - ERROR("IOB memory map array greater than max available windows, set win_count to max %d\n", - MVEBU_IOB_MAX_WINS); + ERROR("IOB mem map array > than max available windows (%d)\n", + MVEBU_IOB_MAX_WINS); win_count = MVEBU_IOB_MAX_WINS; } - /* disable all IOB windows, start from win_id = 1 because can't disable internal register window */ + /* disable all IOB windows, start from win_id = 1 + * because can't disable internal register window + */ for (win_id = 1; win_id < MVEBU_IOB_MAX_WINS; win_id++) { win_reg = mmio_read_32(IOB_WIN_CR_OFFSET(win_id)); win_reg &= ~WIN_ENABLE_BIT; diff --git a/drivers/marvell/jtag.c b/drivers/marvell/jtag.c index 7800524e..3d8f30c9 100644 --- a/drivers/marvell/jtag.c +++ b/drivers/marvell/jtag.c @@ -5,9 +5,9 @@ * https://spdx.org/licenses */ -#include <plat_def.h> -#include <mmio.h> #include <delay_timer.h> +#include <mmio.h> +#include <mvebu_def.h> #define MPP_CTRL_REG 0xEC6f4000 #define GPIO_DATA_EN 0xEC6f5044 diff --git a/drivers/marvell/mc_trustzone/mc_trustzone.c b/drivers/marvell/mc_trustzone/mc_trustzone.c index 6062379f..bd4295a3 100644 --- a/drivers/marvell/mc_trustzone/mc_trustzone.c +++ b/drivers/marvell/mc_trustzone/mc_trustzone.c @@ -8,7 +8,7 @@ #include <addr_map.h> #include <debug.h> #include <mmio.h> -#include <plat_def.h> +#include <mvebu_def.h> #include "mc_trustzone.h" #define TZ_SIZE(x) ((x) >> 13) diff --git a/drivers/marvell/mci.c b/drivers/marvell/mci.c index a35c2b22..721504e0 100644 --- a/drivers/marvell/mci.c +++ b/drivers/marvell/mci.c @@ -1,53 +1,67 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ - + +/* MCI bus driver for Marvell ARMADA 8K and 8K+ SoCs */ + #include <debug.h> #include <delay_timer.h> #include <mmio.h> #include <mci.h> #include <mvebu.h> -#include <plat_def.h> +#include <mvebu_def.h> #include <plat_marvell.h> -/* /HB /Units /Direct_regs /Direct regs /Configuration Register Write/Read Data Register */ -#define MCI_WRITE_READ_DATA_REG(mci_index) MVEBU_MCI_REG_BASE_REMAP(mci_index) -/* /HB /Units /Direct_regs /Direct regs /Configuration Register Access Command Register */ -#define MCI_ACCESS_CMD_REG(mci_index) (MVEBU_MCI_REG_BASE_REMAP(mci_index) + 0x4) +/* /HB /Units /Direct_regs /Direct regs + * /Configuration Register Write/Read Data Register + */ +#define MCI_WRITE_READ_DATA_REG(mci_index) \ + MVEBU_MCI_REG_BASE_REMAP(mci_index) +/* /HB /Units /Direct_regs /Direct regs + * /Configuration Register Access Command Register + */ +#define MCI_ACCESS_CMD_REG(mci_index) \ + (MVEBU_MCI_REG_BASE_REMAP(mci_index) + 0x4) /* Access Command fields : - * bit[3:0] - Sub command: 1 => Periferal Config Register Read, - * 0 => Periferal Config Refister Write, - * 2 => Periferal Assign ID request, + * bit[3:0] - Sub command: 1 => Peripheral Config Register Read, + * 0 => Peripheral Config Register Write, + * 2 => Peripheral Assign ID request, * 3 => Circular Config Write * bit[5] - 1 => Local (same chip access) 0 => Remote * bit[15:8] - Destination hop ID. Put Global ID (GID) here (see scheme below). * bit[23:22] - 0x3 IHB PHY REG address space, 0x0 IHB Controller space * bit[21:16] - Low 6 bits of offset. Hight 2 bits are taken from bit[28:27] - * of IHB_PHY_CTRL (must be set before any PHY register access occures): - * /IHB_REG /IHB_REGInterchip Hopping Bus Registers /IHB Version Control Register + * of IHB_PHY_CTRL + * (must be set before any PHY register access occurs): + * /IHB_REG /IHB_REGInterchip Hopping Bus Registers + * /IHB Version Control Register * - * ixi_ihb_top IHB PHY + * ixi_ihb_top IHB PHY * AXI ----------------------------- ------------- * <--| axi_hb_top | ihb_pipe_top |-->| | * -->| GID=1 | GID=0 |<--| | * ----------------------------- ------------- */ -#define MCI_INDIRECT_CTRL_READ_CMD 0x1 -#define MCI_INDIRECT_CTRL_ASSIGN_CMD 0x2 -#define MCI_INDIRECT_CTRL_CIRCULAR_CMD 0x3 -#define MCI_INDIRECT_CTRL_LOCAL_PKT (1 << 5) -#define MCI_INDIRECT_CTRL_CMD_DONE_OFFSET 6 -#define MCI_INDIRECT_CTRL_CMD_DONE (1 << MCI_INDIRECT_CTRL_CMD_DONE_OFFSET) -#define MCI_INDIRECT_CTRL_DATA_READY_OFFSET 7 -#define MCI_INDIRECT_CTRL_DATA_READY (1 << MCI_INDIRECT_CTRL_DATA_READY_OFFSET) -#define MCI_INDIRECT_CTRL_HOPID_OFFSET 8 -#define MCI_INDIRECT_CTRL_HOPID(id) (((id) & 0xFF) << MCI_INDIRECT_CTRL_HOPID_OFFSET) -#define MCI_INDIRECT_CTRL_REG_CHIPID_OFFSET 16 -#define MCI_INDIRECT_REG_CTRL_ADDR(reg_num) (reg_num << MCI_INDIRECT_CTRL_REG_CHIPID_OFFSET) +#define MCI_INDIRECT_CTRL_READ_CMD 0x1 +#define MCI_INDIRECT_CTRL_ASSIGN_CMD 0x2 +#define MCI_INDIRECT_CTRL_CIRCULAR_CMD 0x3 +#define MCI_INDIRECT_CTRL_LOCAL_PKT (1 << 5) +#define MCI_INDIRECT_CTRL_CMD_DONE_OFFSET 6 +#define MCI_INDIRECT_CTRL_CMD_DONE \ + (1 << MCI_INDIRECT_CTRL_CMD_DONE_OFFSET) +#define MCI_INDIRECT_CTRL_DATA_READY_OFFSET 7 +#define MCI_INDIRECT_CTRL_DATA_READY \ + (1 << MCI_INDIRECT_CTRL_DATA_READY_OFFSET) +#define MCI_INDIRECT_CTRL_HOPID_OFFSET 8 +#define MCI_INDIRECT_CTRL_HOPID(id) \ + (((id) & 0xFF) << MCI_INDIRECT_CTRL_HOPID_OFFSET) +#define MCI_INDIRECT_CTRL_REG_CHIPID_OFFSET 16 +#define MCI_INDIRECT_REG_CTRL_ADDR(reg_num) \ + (reg_num << MCI_INDIRECT_CTRL_REG_CHIPID_OFFSET) /* Hop ID values */ #define GID_IHB_PIPE 0 @@ -73,95 +87,121 @@ #define MCI_CTRL_RX_TX_MEM_CFG_DELTA_THRESH(val) (((val) & 0xF) << 4) #define MCI_CTRL_RX_TX_MEM_CFG_RTC(val) (((val) & 0x3) << 2) #define MCI_CTRL_RX_TX_MEM_CFG_WTC(val) (((val) & 0x3) << 0) -#define MCI_CTRL_RX_MEM_CFG_REG_DEF_CP_VAL (MCI_CTRL_RX_TX_MEM_CFG_RQ_THRESH(0x07) | \ - MCI_CTRL_RX_TX_MEM_CFG_PQ_THRESH(0x3f) | \ - MCI_CTRL_RX_TX_MEM_CFG_NQ_THRESH(0x3f) | \ - MCI_CTRL_RX_TX_MEM_CFG_DELTA_THRESH(0xf) | \ - MCI_CTRL_RX_TX_MEM_CFG_RTC(1) | \ - MCI_CTRL_RX_TX_MEM_CFG_WTC(1)) - -#define MCI_CTRL_RX_MEM_CFG_REG_DEF_AP_VAL (MCI_CTRL_RX_TX_MEM_CFG_RQ_THRESH(0x3f) | \ - MCI_CTRL_RX_TX_MEM_CFG_PQ_THRESH(0x03) | \ - MCI_CTRL_RX_TX_MEM_CFG_NQ_THRESH(0x3f) | \ - MCI_CTRL_RX_TX_MEM_CFG_DELTA_THRESH(0xf) | \ - MCI_CTRL_RX_TX_MEM_CFG_RTC(1) | \ - MCI_CTRL_RX_TX_MEM_CFG_WTC(1)) +#define MCI_CTRL_RX_MEM_CFG_REG_DEF_CP_VAL \ + (MCI_CTRL_RX_TX_MEM_CFG_RQ_THRESH(0x07) | \ + MCI_CTRL_RX_TX_MEM_CFG_PQ_THRESH(0x3f) | \ + MCI_CTRL_RX_TX_MEM_CFG_NQ_THRESH(0x3f) | \ + MCI_CTRL_RX_TX_MEM_CFG_DELTA_THRESH(0xf) | \ + MCI_CTRL_RX_TX_MEM_CFG_RTC(1) | \ + MCI_CTRL_RX_TX_MEM_CFG_WTC(1)) + +#define MCI_CTRL_RX_MEM_CFG_REG_DEF_AP_VAL \ + (MCI_CTRL_RX_TX_MEM_CFG_RQ_THRESH(0x3f) | \ + MCI_CTRL_RX_TX_MEM_CFG_PQ_THRESH(0x03) | \ + MCI_CTRL_RX_TX_MEM_CFG_NQ_THRESH(0x3f) | \ + MCI_CTRL_RX_TX_MEM_CFG_DELTA_THRESH(0xf) | \ + MCI_CTRL_RX_TX_MEM_CFG_RTC(1) | \ + MCI_CTRL_RX_TX_MEM_CFG_WTC(1)) /* /HB /Units /IHB_REG /IHB_REGInterchip Hopping Bus Registers/ - * Tx Memory Configuration Register (TX_MEM_CFG) */ + * Tx Memory Configuration Register (TX_MEM_CFG) + */ #define MCI_CTRL_TX_MEM_CFG_REG_NUM 0x1 -/* field mapping for TX mem config register are the as for RX register - see register above */ -#define MCI_CTRL_TX_MEM_CFG_REG_DEF_VAL (MCI_CTRL_RX_TX_MEM_CFG_RQ_THRESH(0x20) | \ - MCI_CTRL_RX_TX_MEM_CFG_PQ_THRESH(0x20) | \ - MCI_CTRL_RX_TX_MEM_CFG_NQ_THRESH(0x20) | \ - MCI_CTRL_RX_TX_MEM_CFG_DELTA_THRESH(2) | \ - MCI_CTRL_RX_TX_MEM_CFG_RTC(1) | \ - MCI_CTRL_RX_TX_MEM_CFG_WTC(1)) - -/* /HB /Units /IHB_REG /IHB_REGInterchip Hopping Bus Registers /IHB Link CRC Control */ +/* field mapping for TX mem config register + * are the same as for RX register - see register above + */ +#define MCI_CTRL_TX_MEM_CFG_REG_DEF_VAL \ + (MCI_CTRL_RX_TX_MEM_CFG_RQ_THRESH(0x20) | \ + MCI_CTRL_RX_TX_MEM_CFG_PQ_THRESH(0x20) | \ + MCI_CTRL_RX_TX_MEM_CFG_NQ_THRESH(0x20) | \ + MCI_CTRL_RX_TX_MEM_CFG_DELTA_THRESH(2) | \ + MCI_CTRL_RX_TX_MEM_CFG_RTC(1) | \ + MCI_CTRL_RX_TX_MEM_CFG_WTC(1)) + +/* /HB /Units /IHB_REG /IHB_REGInterchip Hopping Bus Registers + * /IHB Link CRC Control + */ /* MCi Link CRC Control Register (MCi_CRC_CTRL) */ #define MCI_LINK_CRC_CTRL_REG_NUM 0x4 -/* /HB /Units /IHB_REG /IHB_REGInterchip Hopping Bus Registers /IHB Status Register */ +/* /HB /Units /IHB_REG /IHB_REGInterchip Hopping Bus Registers + * /IHB Status Register + */ /* MCi Status Register (MCi_STS) */ #define MCI_CTRL_STATUS_REG_NUM 0x5 #define MCI_CTRL_STATUS_REG_PHY_READY (1 << 12) #define MCI_CTRL_STATUS_REG_LINK_PRESENT (1 << 15) #define MCI_CTRL_STATUS_REG_PHY_CID_VIO_OFFSET 24 -#define MCI_CTRL_STATUS_REG_PHY_CID_VIO_MASK (0xF << MCI_CTRL_STATUS_REG_PHY_CID_VIO_OFFSET) +#define MCI_CTRL_STATUS_REG_PHY_CID_VIO_MASK \ + (0xF << MCI_CTRL_STATUS_REG_PHY_CID_VIO_OFFSET) /* Expected successful Link result, including reserved bit */ -#define MCI_CTRL_PHY_READY (MCI_CTRL_STATUS_REG_PHY_READY | \ - MCI_CTRL_STATUS_REG_LINK_PRESENT | \ - MCI_CTRL_STATUS_REG_PHY_CID_VIO_MASK) +#define MCI_CTRL_PHY_READY (MCI_CTRL_STATUS_REG_PHY_READY | \ + MCI_CTRL_STATUS_REG_LINK_PRESENT | \ + MCI_CTRL_STATUS_REG_PHY_CID_VIO_MASK) /* /HB /Units /IHB_REG /IHB_REGInterchip Hopping Bus Registers/ - * MCi PHY Speed Settings Register (MCi_PHY_SETTING) */ + * MCi PHY Speed Settings Register (MCi_PHY_SETTING) + */ #define MCI_CTRL_MCI_PHY_SETTINGS_REG_NUM 0x8 #define MCI_CTRL_MCI_PHY_SET_DLO_FIFO_FULL_TRESH(val) (((val) & 0xF) << 28) #define MCI_CTRL_MCI_PHY_SET_PHY_MAX_SPEED(val) (((val) & 0xF) << 12) #define MCI_CTRL_MCI_PHY_SET_PHYCLK_SEL(val) (((val) & 0xF) << 8) #define MCI_CTRL_MCI_PHY_SET_REFCLK_FREQ_SEL(val) (((val) & 0xF) << 4) #define MCI_CTRL_MCI_PHY_SET_AUTO_LINK_EN(val) (((val) & 0x1) << 1) -#define MCI_CTRL_MCI_PHY_SET_REG_DEF_VAL (MCI_CTRL_MCI_PHY_SET_DLO_FIFO_FULL_TRESH(0x3) | \ - MCI_CTRL_MCI_PHY_SET_PHY_MAX_SPEED(0x3) | \ - MCI_CTRL_MCI_PHY_SET_PHYCLK_SEL(0x2) | \ - MCI_CTRL_MCI_PHY_SET_REFCLK_FREQ_SEL(0x1)) -#define MCI_CTRL_MCI_PHY_SET_REG_DEF_VAL2 (MCI_CTRL_MCI_PHY_SET_DLO_FIFO_FULL_TRESH(0x3) | \ - MCI_CTRL_MCI_PHY_SET_PHY_MAX_SPEED(0x3) | \ - MCI_CTRL_MCI_PHY_SET_PHYCLK_SEL(0x5) | \ - MCI_CTRL_MCI_PHY_SET_REFCLK_FREQ_SEL(0x1)) - -/* /HB /Units /IHB_REG /IHB_REGInterchip Hopping Bus Registers /IHB Mode Config */ +#define MCI_CTRL_MCI_PHY_SET_REG_DEF_VAL \ + (MCI_CTRL_MCI_PHY_SET_DLO_FIFO_FULL_TRESH(0x3) | \ + MCI_CTRL_MCI_PHY_SET_PHY_MAX_SPEED(0x3) | \ + MCI_CTRL_MCI_PHY_SET_PHYCLK_SEL(0x2) | \ + MCI_CTRL_MCI_PHY_SET_REFCLK_FREQ_SEL(0x1)) +#define MCI_CTRL_MCI_PHY_SET_REG_DEF_VAL2 \ + (MCI_CTRL_MCI_PHY_SET_DLO_FIFO_FULL_TRESH(0x3) | \ + MCI_CTRL_MCI_PHY_SET_PHY_MAX_SPEED(0x3) | \ + MCI_CTRL_MCI_PHY_SET_PHYCLK_SEL(0x5) | \ + MCI_CTRL_MCI_PHY_SET_REFCLK_FREQ_SEL(0x1)) + +/* /HB /Units /IHB_REG /IHB_REGInterchip Hopping Bus Registers + * /IHB Mode Config + */ #define MCI_CTRL_IHB_MODE_CFG_REG_NUM 0x25 #define MCI_CTRL_IHB_MODE_HBCLK_DIV(val) ((val) & 0xFF) #define MCI_CTRL_IHB_MODE_CHUNK_MOD_OFFSET 8 -#define MCI_CTRL_IHB_MODE_CHUNK_MOD (1 << MCI_CTRL_IHB_MODE_CHUNK_MOD_OFFSET) +#define MCI_CTRL_IHB_MODE_CHUNK_MOD \ + (1 << MCI_CTRL_IHB_MODE_CHUNK_MOD_OFFSET) #define MCI_CTRL_IHB_MODE_FWD_MOD_OFFSET 9 -#define MCI_CTRL_IHB_MODE_FWD_MOD (1 << MCI_CTRL_IHB_MODE_FWD_MOD_OFFSET) +#define MCI_CTRL_IHB_MODE_FWD_MOD \ + (1 << MCI_CTRL_IHB_MODE_FWD_MOD_OFFSET) #define MCI_CTRL_IHB_MODE_SEQFF_FINE_MOD(val) (((val) & 0xF) << 12) #define MCI_CTRL_IHB_MODE_RX_COMB_THRESH(val) (((val) & 0xFF) << 16) #define MCI_CTRL_IHB_MODE_TX_COMB_THRESH(val) (((val) & 0xFF) << 24) -#define MCI_CTRL_IHB_MODE_CFG_REG_DEF_VAL (MCI_CTRL_IHB_MODE_HBCLK_DIV(6) | \ - MCI_CTRL_IHB_MODE_FWD_MOD | \ - MCI_CTRL_IHB_MODE_SEQFF_FINE_MOD(0xF) | \ - MCI_CTRL_IHB_MODE_RX_COMB_THRESH(0x3f) | \ - MCI_CTRL_IHB_MODE_TX_COMB_THRESH(0x40)) +#define MCI_CTRL_IHB_MODE_CFG_REG_DEF_VAL \ + (MCI_CTRL_IHB_MODE_HBCLK_DIV(6) | \ + MCI_CTRL_IHB_MODE_FWD_MOD | \ + MCI_CTRL_IHB_MODE_SEQFF_FINE_MOD(0xF) | \ + MCI_CTRL_IHB_MODE_RX_COMB_THRESH(0x3f) | \ + MCI_CTRL_IHB_MODE_TX_COMB_THRESH(0x40)) /* AXI_HB registers */ #define MCI_AXI_ACCESS_DATA_REG_NUM 0x0 #define MCI_AXI_ACCESS_PCIE_MODE 1 #define MCI_AXI_ACCESS_CACHE_CHECK_OFFSET 5 -#define MCI_AXI_ACCESS_CACHE_CHECK (1 << MCI_AXI_ACCESS_CACHE_CHECK_OFFSET) +#define MCI_AXI_ACCESS_CACHE_CHECK \ + (1 << MCI_AXI_ACCESS_CACHE_CHECK_OFFSET) #define MCI_AXI_ACCESS_FORCE_POST_WR_OFFSET 6 -#define MCI_AXI_ACCESS_FORCE_POST_WR (1 << MCI_AXI_ACCESS_FORCE_POST_WR_OFFSET) +#define MCI_AXI_ACCESS_FORCE_POST_WR \ + (1 << MCI_AXI_ACCESS_FORCE_POST_WR_OFFSET) #define MCI_AXI_ACCESS_DISABLE_CLK_GATING_OFFSET 9 -#define MCI_AXI_ACCESS_DISABLE_CLK_GATING (1 << MCI_AXI_ACCESS_DISABLE_CLK_GATING_OFFSET) +#define MCI_AXI_ACCESS_DISABLE_CLK_GATING \ + (1 << MCI_AXI_ACCESS_DISABLE_CLK_GATING_OFFSET) -/* /HB /Units /HB_REG /HB_REGHopping Bus Registers /Window 0 Address Mask Register */ +/* /HB /Units /HB_REG /HB_REGHopping Bus Registers + * /Window 0 Address Mask Register + */ #define MCI_HB_CTRL_WIN0_ADDRESS_MASK_REG_NUM 0x2 -/* /HB /Units /HB_REG /HB_REGHopping Bus Registers /Window 0 Destination Register */ +/* /HB /Units /HB_REG /HB_REGHopping Bus Registers + * /Window 0 Destination Register + */ #define MCI_HB_CTRL_WIN0_DESTINATION_REG_NUM 0x3 #define MCI_HB_CTRL_WIN0_DEST_VALID_FLAG(val) (((val) & 0x1) << 16) #define MCI_HB_CTRL_WIN0_DEST_ID(val) (((val) & 0xFF) << 0) @@ -169,28 +209,42 @@ /* /HB /Units /HB_REG /HB_REGHopping Bus Registers /Tx Control Register */ #define MCI_HB_CTRL_TX_CTRL_REG_NUM 0xD #define MCI_HB_CTRL_TX_CTRL_PCIE_MODE_OFFSET 24 -#define MCI_HB_CTRL_TX_CTRL_PCIE_MODE (1 << MCI_HB_CTRL_TX_CTRL_PCIE_MODE_OFFSET) +#define MCI_HB_CTRL_TX_CTRL_PCIE_MODE \ + (1 << MCI_HB_CTRL_TX_CTRL_PCIE_MODE_OFFSET) #define MCI_HB_CTRL_TX_CTRL_PRI_TH_QOS(val) (((val) & 0xF) << 12) #define MCI_HB_CTRL_TX_CTRL_MAX_RD_CNT(val) (((val) & 0x1F) << 6) #define MCI_HB_CTRL_TX_CTRL_MAX_WR_CNT(val) (((val) & 0x1F) << 0) -/* /HB /Units /IHB_REG /IHB_REGInterchip Hopping Bus Registers /IHB Version Control Register */ +/* /HB /Units /IHB_REG /IHB_REGInterchip Hopping Bus Registers + * /IHB Version Control Register + */ #define MCI_PHY_CTRL_REG_NUM 0x7 #define MCI_PHY_CTRL_MCI_MINOR 0x8 /* BITS [3:0] */ #define MCI_PHY_CTRL_MCI_MAJOR_OFFSET 4 -#define MCI_PHY_CTRL_MCI_MAJOR (1 << MCI_PHY_CTRL_MCI_MAJOR_OFFSET) +#define MCI_PHY_CTRL_MCI_MAJOR \ + (1 << MCI_PHY_CTRL_MCI_MAJOR_OFFSET) #define MCI_PHY_CTRL_MCI_SLEEP_REQ_OFFSET 11 -#define MCI_PHY_CTRL_MCI_SLEEP_REQ (1 << MCI_PHY_CTRL_MCI_SLEEP_REQ_OFFSET) -#define MCI_PHY_CTRL_MCI_PHY_MODE_OFFSET 24 /* Host=1 / Device=0 PHY mode */ -#define MCI_PHY_CTRL_MCI_PHY_MODE_HOST (1 << MCI_PHY_CTRL_MCI_PHY_MODE_OFFSET) -#define MCI_PHY_CTRL_MCI_PHY_REG_IF_MODE_OFFSET 25 /* Register=1 / PWM=0 interface */ -#define MCI_PHY_CTRL_MCI_PHY_REG_IF_MODE (1 << MCI_PHY_CTRL_MCI_PHY_REG_IF_MODE_OFFSET) -#define MCI_PHY_CTRL_MCI_PHY_RESET_CORE_OFFSET 26 /* PHY code InReset=1 */ -#define MCI_PHY_CTRL_MCI_PHY_RESET_CORE (1 << MCI_PHY_CTRL_MCI_PHY_RESET_CORE_OFFSET) +#define MCI_PHY_CTRL_MCI_SLEEP_REQ \ + (1 << MCI_PHY_CTRL_MCI_SLEEP_REQ_OFFSET) +/* Host=1 / Device=0 PHY mode */ +#define MCI_PHY_CTRL_MCI_PHY_MODE_OFFSET 24 +#define MCI_PHY_CTRL_MCI_PHY_MODE_HOST \ + (1 << MCI_PHY_CTRL_MCI_PHY_MODE_OFFSET) +/* Register=1 / PWM=0 interface */ +#define MCI_PHY_CTRL_MCI_PHY_REG_IF_MODE_OFFSET 25 +#define MCI_PHY_CTRL_MCI_PHY_REG_IF_MODE \ + (1 << MCI_PHY_CTRL_MCI_PHY_REG_IF_MODE_OFFSET) + /* PHY code InReset=1 */ +#define MCI_PHY_CTRL_MCI_PHY_RESET_CORE_OFFSET 26 +#define MCI_PHY_CTRL_MCI_PHY_RESET_CORE \ + (1 << MCI_PHY_CTRL_MCI_PHY_RESET_CORE_OFFSET) #define MCI_PHY_CTRL_PHY_ADDR_MSB_OFFSET 27 -#define MCI_PHY_CTRL_PHY_ADDR_MSB(addr) (((addr) & 0x3) << MCI_PHY_CTRL_PHY_ADDR_MSB_OFFSET) +#define MCI_PHY_CTRL_PHY_ADDR_MSB(addr) \ + (((addr) & 0x3) << \ + MCI_PHY_CTRL_PHY_ADDR_MSB_OFFSET) #define MCI_PHY_CTRL_PIDI_MODE_OFFSET 31 -#define MCI_PHY_CTRL_PIDI_MODE (1 << MCI_PHY_CTRL_PIDI_MODE_OFFSET) +#define MCI_PHY_CTRL_PIDI_MODE \ + (1 << MCI_PHY_CTRL_PIDI_MODE_OFFSET) /* Number of times to wait for the MCI link ready after MCI configurations * Normally takes 34-35 successive reads @@ -221,6 +275,7 @@ static void mci_mmio_write_32(uintptr_t addr, uint32_t value) static uint32_t mci_mmio_read_32(uintptr_t addr) { uint32_t value; + value = mmio_read_32(addr); VERBOSE("Read:\t0x%x = 0x%x\n", (uint32_t)addr, value); return value; @@ -251,7 +306,8 @@ static int mci_poll_command_completion(int mci_index, int command_type) (retry_count-- > 0)); if (retry_count == 0) { - ERROR("%s: MCI command timeout (command status = 0x%x)\n", __func__, mci_cmd_value); + ERROR("%s: MCI command timeout (command status = 0x%x)\n", + __func__, mci_cmd_value); ret = 1; } @@ -280,16 +336,18 @@ int mci_write(int mci_idx, uint32_t cmd, uint32_t data) return mci_poll_command_completion(mci_idx, MCI_CMD_WRITE); } -/* Perform 3 configurations in one command: PCI mode, queues separation and cache bit */ +/* Perform 3 configurations in one command: PCI mode, + * queues separation and cache bit + */ static int mci_axi_set_pcie_mode(int mci_index) { uint32_t reg_data, ret = 1; debug_enter(); - /* This configuration makes MCI IP behave consistently with AXI protocol. - * It should be configured at one side only (for example localy at AP). - * The IP takes care of performing the same configurations at MCI on another - * side (for example remotely at CP). + /* This configuration makes MCI IP behave consistently with AXI protocol + * It should be configured at one side only (for example locally at AP). + * The IP takes care of performing the same configurations at MCI on + * another side (for example remotely at CP). */ mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), MCI_AXI_ACCESS_PCIE_MODE | @@ -297,7 +355,8 @@ static int mci_axi_set_pcie_mode(int mci_index) MCI_AXI_ACCESS_FORCE_POST_WR | MCI_AXI_ACCESS_DISABLE_CLK_GATING); mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), - MCI_INDIRECT_REG_CTRL_ADDR(MCI_AXI_ACCESS_DATA_REG_NUM) | + MCI_INDIRECT_REG_CTRL_ADDR( + MCI_AXI_ACCESS_DATA_REG_NUM) | MCI_INDIRECT_CTRL_HOPID(GID_AXI_HB) | MCI_INDIRECT_CTRL_LOCAL_PKT | MCI_INDIRECT_CTRL_CIRCULAR_CMD); @@ -306,13 +365,15 @@ static int mci_axi_set_pcie_mode(int mci_index) if (mci_poll_command_completion(mci_index, MCI_CMD_WRITE) == 0) { /* Verify the PCIe mode selected */ mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), - MCI_INDIRECT_REG_CTRL_ADDR(MCI_HB_CTRL_TX_CTRL_REG_NUM) | + MCI_INDIRECT_REG_CTRL_ADDR( + MCI_HB_CTRL_TX_CTRL_REG_NUM) | MCI_INDIRECT_CTRL_HOPID(GID_AXI_HB) | MCI_INDIRECT_CTRL_LOCAL_PKT | MCI_INDIRECT_CTRL_READ_CMD); /* if read was completed, verify PCIe mode */ if (mci_poll_command_completion(mci_index, MCI_CMD_READ) == 0) { - reg_data = mci_mmio_read_32(MCI_WRITE_READ_DATA_REG(mci_index)); + reg_data = mci_mmio_read_32( + MCI_WRITE_READ_DATA_REG(mci_index)); if (reg_data & MCI_HB_CTRL_TX_CTRL_PCIE_MODE) ret = 0; } @@ -322,25 +383,29 @@ static int mci_axi_set_pcie_mode(int mci_index) return ret; } -/* Reduce sequence FIFO timer expiration threshold, including PIDI workaround */ +/* Reduce sequence FIFO timer expiration threshold */ static int mci_axi_set_fifo_thresh(int mci_index) { uint32_t reg_data, ret = 0; debug_enter(); - /* This configuration reduces sequence FIFO timer expiration threshold (to 0x7 instead of 0xA). - * In MCI 1.6 version this configuration prevents possible functional issues. + /* This configuration reduces sequence FIFO timer expiration threshold + * (to 0x7 instead of 0xA). + * In MCI 1.6 version this configuration prevents possible functional + * issues. * In version 1.82 the configuration prevents performance degradation */ /* Configure local AP side */ - /* PIDI Workaround for entering PIDI mode */ - reg_data = MCI_PHY_CTRL_PIDI_MODE | MCI_PHY_CTRL_MCI_PHY_REG_IF_MODE - | MCI_PHY_CTRL_MCI_PHY_MODE_HOST - | MCI_PHY_CTRL_MCI_MAJOR | MCI_PHY_CTRL_MCI_MINOR; + reg_data = MCI_PHY_CTRL_PIDI_MODE | + MCI_PHY_CTRL_MCI_PHY_REG_IF_MODE | + MCI_PHY_CTRL_MCI_PHY_MODE_HOST | + MCI_PHY_CTRL_MCI_MAJOR | + MCI_PHY_CTRL_MCI_MINOR; mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), reg_data); mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), - MCI_INDIRECT_REG_CTRL_ADDR(MCI_PHY_CTRL_REG_NUM) | MCI_INDIRECT_CTRL_LOCAL_PKT); + MCI_INDIRECT_REG_CTRL_ADDR(MCI_PHY_CTRL_REG_NUM) | + MCI_INDIRECT_CTRL_LOCAL_PKT); ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); /* Reduce the threshold */ @@ -348,40 +413,50 @@ static int mci_axi_set_fifo_thresh(int mci_index) MCI_CTRL_IHB_MODE_CFG_REG_DEF_VAL); mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), - MCI_INDIRECT_REG_CTRL_ADDR(MCI_CTRL_IHB_MODE_CFG_REG_NUM) | + MCI_INDIRECT_REG_CTRL_ADDR( + MCI_CTRL_IHB_MODE_CFG_REG_NUM) | MCI_INDIRECT_CTRL_LOCAL_PKT); ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); /* Exit PIDI mode */ - reg_data = MCI_PHY_CTRL_MCI_PHY_REG_IF_MODE | MCI_PHY_CTRL_MCI_PHY_MODE_HOST - | MCI_PHY_CTRL_MCI_MAJOR | MCI_PHY_CTRL_MCI_MINOR; + reg_data = MCI_PHY_CTRL_MCI_PHY_REG_IF_MODE | + MCI_PHY_CTRL_MCI_PHY_MODE_HOST | + MCI_PHY_CTRL_MCI_MAJOR | + MCI_PHY_CTRL_MCI_MINOR; mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), reg_data); mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), - MCI_INDIRECT_REG_CTRL_ADDR(MCI_PHY_CTRL_REG_NUM) | MCI_INDIRECT_CTRL_LOCAL_PKT); + MCI_INDIRECT_REG_CTRL_ADDR(MCI_PHY_CTRL_REG_NUM) | + MCI_INDIRECT_CTRL_LOCAL_PKT); ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); /* Configure remote CP side */ - /* PIDI Workaround for entering PIDI mode */ - reg_data = MCI_PHY_CTRL_PIDI_MODE | MCI_PHY_CTRL_MCI_MAJOR | MCI_PHY_CTRL_MCI_MINOR | + reg_data = MCI_PHY_CTRL_PIDI_MODE | + MCI_PHY_CTRL_MCI_MAJOR | + MCI_PHY_CTRL_MCI_MINOR | MCI_PHY_CTRL_MCI_PHY_REG_IF_MODE; mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), reg_data); mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), - MCI_INDIRECT_REG_CTRL_ADDR(MCI_PHY_CTRL_REG_NUM) | MCI_CTRL_IHB_MODE_FWD_MOD); + MCI_INDIRECT_REG_CTRL_ADDR(MCI_PHY_CTRL_REG_NUM) | + MCI_CTRL_IHB_MODE_FWD_MOD); ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); /* Reduce the threshold */ mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), MCI_CTRL_IHB_MODE_CFG_REG_DEF_VAL); mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), - MCI_INDIRECT_REG_CTRL_ADDR(MCI_CTRL_IHB_MODE_CFG_REG_NUM) | + MCI_INDIRECT_REG_CTRL_ADDR( + MCI_CTRL_IHB_MODE_CFG_REG_NUM) | MCI_INDIRECT_CTRL_HOPID(GID_IHB_EXT)); ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); /* Exit PIDI mode */ - reg_data = MCI_PHY_CTRL_MCI_MAJOR | MCI_PHY_CTRL_MCI_MINOR | MCI_PHY_CTRL_MCI_PHY_REG_IF_MODE; + reg_data = MCI_PHY_CTRL_MCI_MAJOR | + MCI_PHY_CTRL_MCI_MINOR | + MCI_PHY_CTRL_MCI_PHY_REG_IF_MODE; mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), reg_data); mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), - MCI_INDIRECT_REG_CTRL_ADDR(MCI_PHY_CTRL_REG_NUM) | MCI_CTRL_IHB_MODE_FWD_MOD); + MCI_INDIRECT_REG_CTRL_ADDR(MCI_PHY_CTRL_REG_NUM) | + MCI_CTRL_IHB_MODE_FWD_MOD); ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); @@ -405,7 +480,8 @@ static int mci_axi_set_fifo_rx_tx_thresh(int mci_index) mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), MCI_CTRL_TX_MEM_CFG_REG_DEF_VAL); mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), - MCI_INDIRECT_REG_CTRL_ADDR(MCI_CTRL_TX_MEM_CFG_REG_NUM) | + MCI_INDIRECT_REG_CTRL_ADDR( + MCI_CTRL_TX_MEM_CFG_REG_NUM) | MCI_INDIRECT_CTRL_LOCAL_PKT); ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); @@ -413,15 +489,18 @@ static int mci_axi_set_fifo_rx_tx_thresh(int mci_index) mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), MCI_CTRL_TX_MEM_CFG_REG_DEF_VAL); mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), - MCI_INDIRECT_REG_CTRL_ADDR(MCI_CTRL_TX_MEM_CFG_REG_NUM) | + MCI_INDIRECT_REG_CTRL_ADDR( + MCI_CTRL_TX_MEM_CFG_REG_NUM) | MCI_INDIRECT_CTRL_HOPID(GID_IHB_EXT)); ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); /* AP DLO & DLI FIFO full threshold & Auto-Link enable (IHB_reg 0x8) */ mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), - MCI_CTRL_MCI_PHY_SET_REG_DEF_VAL | MCI_CTRL_MCI_PHY_SET_AUTO_LINK_EN(1)); + MCI_CTRL_MCI_PHY_SET_REG_DEF_VAL | + MCI_CTRL_MCI_PHY_SET_AUTO_LINK_EN(1)); mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), - MCI_INDIRECT_REG_CTRL_ADDR(MCI_CTRL_MCI_PHY_SETTINGS_REG_NUM) | + MCI_INDIRECT_REG_CTRL_ADDR( + MCI_CTRL_MCI_PHY_SETTINGS_REG_NUM) | MCI_INDIRECT_CTRL_LOCAL_PKT); ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); @@ -429,7 +508,8 @@ static int mci_axi_set_fifo_rx_tx_thresh(int mci_index) mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), MCI_CTRL_MCI_PHY_SET_REG_DEF_VAL); mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), - MCI_INDIRECT_REG_CTRL_ADDR(MCI_CTRL_MCI_PHY_SETTINGS_REG_NUM) | + MCI_INDIRECT_REG_CTRL_ADDR( + MCI_CTRL_MCI_PHY_SETTINGS_REG_NUM) | MCI_INDIRECT_CTRL_HOPID(GID_IHB_EXT)); ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); @@ -437,7 +517,8 @@ static int mci_axi_set_fifo_rx_tx_thresh(int mci_index) mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), MCI_CTRL_RX_MEM_CFG_REG_DEF_AP_VAL); mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), - MCI_INDIRECT_REG_CTRL_ADDR(MCI_CTRL_RX_MEM_CFG_REG_NUM) | + MCI_INDIRECT_REG_CTRL_ADDR( + MCI_CTRL_RX_MEM_CFG_REG_NUM) | MCI_INDIRECT_CTRL_LOCAL_PKT); ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); @@ -445,28 +526,31 @@ static int mci_axi_set_fifo_rx_tx_thresh(int mci_index) mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), MCI_CTRL_RX_MEM_CFG_REG_DEF_CP_VAL); mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), - MCI_INDIRECT_REG_CTRL_ADDR(MCI_CTRL_RX_MEM_CFG_REG_NUM) | + MCI_INDIRECT_REG_CTRL_ADDR( + MCI_CTRL_RX_MEM_CFG_REG_NUM) | MCI_INDIRECT_CTRL_HOPID(GID_IHB_EXT)); ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); - /* AP AR & AW maximum AXI outstanding request configuration (HB_reg 0xd) */ + /* AP AR & AW maximum AXI outstanding request cfg (HB_reg 0xd) */ mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), MCI_HB_CTRL_TX_CTRL_PRI_TH_QOS(8) | MCI_HB_CTRL_TX_CTRL_MAX_RD_CNT(3) | MCI_HB_CTRL_TX_CTRL_MAX_WR_CNT(3)); mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), - MCI_INDIRECT_REG_CTRL_ADDR(MCI_HB_CTRL_TX_CTRL_REG_NUM) | + MCI_INDIRECT_REG_CTRL_ADDR( + MCI_HB_CTRL_TX_CTRL_REG_NUM) | MCI_INDIRECT_CTRL_HOPID(GID_AXI_HB) | MCI_INDIRECT_CTRL_LOCAL_PKT); ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); - /* CP AR & AW maximum AXI outstanding request configuration (HB_reg 0xd) */ + /* CP AR & AW maximum AXI outstanding request cfg (HB_reg 0xd) */ mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(mci_index), MCI_HB_CTRL_TX_CTRL_PRI_TH_QOS(8) | MCI_HB_CTRL_TX_CTRL_MAX_RD_CNT(0xB) | MCI_HB_CTRL_TX_CTRL_MAX_WR_CNT(0x11)); mci_mmio_write_32(MCI_ACCESS_CMD_REG(mci_index), - MCI_INDIRECT_REG_CTRL_ADDR(MCI_HB_CTRL_TX_CTRL_REG_NUM) | + MCI_INDIRECT_REG_CTRL_ADDR( + MCI_HB_CTRL_TX_CTRL_REG_NUM) | MCI_INDIRECT_CTRL_HOPID(GID_IHB_EXT) | MCI_INDIRECT_CTRL_HOPID(GID_AXI_HB)); ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); @@ -476,8 +560,8 @@ static int mci_axi_set_fifo_rx_tx_thresh(int mci_index) } /* configure MCI to allow read & write transactions to arrive at the same time. - * Without the below configuration, MCI won't sent response to CPU for transactions - * which arrived simultaneously and will lead to CPU hang. + * Without the below configuration, MCI won't sent response to CPU for + * transactions which arrived simultaneously and will lead to CPU hang. * The below will configure MCI to be able to pass transactions from/to CP/AP. */ static int mci_enable_simultaneous_transactions(int mci_index) @@ -491,46 +575,53 @@ static int mci_enable_simultaneous_transactions(int mci_index) MCI_DID_GLOBAL_ASSIGN_REQ_MCI_COUNT(2) | MCI_DID_GLOBAL_ASSIGN_REQ_HOPS_NUM(2)); mci_mmio_write_32(MCI_ACCESS_CMD_REG(0), - MCI_INDIRECT_REG_CTRL_ADDR(MCI_DID_GLOBAL_ASSIGNMENT_REQUEST_REG) | + MCI_INDIRECT_REG_CTRL_ADDR( + MCI_DID_GLOBAL_ASSIGNMENT_REQUEST_REG) | MCI_INDIRECT_CTRL_ASSIGN_CMD); ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); - /* Assigning destination ID=3 to all transactions entering from AXI at AP */ + /* Assigning dest. ID=3 to all transactions entering from AXI at AP */ mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(0), MCI_HB_CTRL_WIN0_DEST_VALID_FLAG(1) | MCI_HB_CTRL_WIN0_DEST_ID(3)); mci_mmio_write_32(MCI_ACCESS_CMD_REG(0), - MCI_INDIRECT_REG_CTRL_ADDR(MCI_HB_CTRL_WIN0_DESTINATION_REG_NUM) | + MCI_INDIRECT_REG_CTRL_ADDR( + MCI_HB_CTRL_WIN0_DESTINATION_REG_NUM) | MCI_INDIRECT_CTRL_HOPID(GID_AXI_HB) | MCI_INDIRECT_CTRL_LOCAL_PKT); ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); - /* Assigning destination ID=1 to all transactions entering from AXI at CP */ + /* Assigning dest. ID=1 to all transactions entering from AXI at CP */ mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(0), MCI_HB_CTRL_WIN0_DEST_VALID_FLAG(1) | MCI_HB_CTRL_WIN0_DEST_ID(1)); mci_mmio_write_32(MCI_ACCESS_CMD_REG(0), - MCI_INDIRECT_REG_CTRL_ADDR(MCI_HB_CTRL_WIN0_DESTINATION_REG_NUM) | + MCI_INDIRECT_REG_CTRL_ADDR( + MCI_HB_CTRL_WIN0_DESTINATION_REG_NUM) | MCI_INDIRECT_CTRL_HOPID(GID_IHB_EXT) | MCI_INDIRECT_CTRL_HOPID(GID_AXI_HB)); ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); - /* End address to all transactions entering from AXI at AP. This will lead to - * get match for any AXI address, and receive destination ID=3 + /* End address to all transactions entering from AXI at AP. + * This will lead to get match for any AXI address + * and receive destination ID=3 */ mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(0), 0xffffffff); mci_mmio_write_32(MCI_ACCESS_CMD_REG(0), - MCI_INDIRECT_REG_CTRL_ADDR(MCI_HB_CTRL_WIN0_ADDRESS_MASK_REG_NUM) | + MCI_INDIRECT_REG_CTRL_ADDR( + MCI_HB_CTRL_WIN0_ADDRESS_MASK_REG_NUM) | MCI_INDIRECT_CTRL_HOPID(GID_AXI_HB) | MCI_INDIRECT_CTRL_LOCAL_PKT); ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); - /* End address to all transactions entering from AXI at CP. This will lead to - * get match for any AXI address, and receive destination ID=1 + /* End address to all transactions entering from AXI at CP. + * This will lead to get match for any AXI address + * and receive destination ID=1 */ mci_mmio_write_32(MCI_WRITE_READ_DATA_REG(0), 0xffffffff); mci_mmio_write_32(MCI_ACCESS_CMD_REG(0), - MCI_INDIRECT_REG_CTRL_ADDR(MCI_HB_CTRL_WIN0_ADDRESS_MASK_REG_NUM) | + MCI_INDIRECT_REG_CTRL_ADDR( + MCI_HB_CTRL_WIN0_ADDRESS_MASK_REG_NUM) | MCI_INDIRECT_CTRL_HOPID(GID_IHB_EXT) | MCI_INDIRECT_CTRL_HOPID(GID_AXI_HB)); ret |= mci_poll_command_completion(mci_index, MCI_CMD_WRITE); @@ -562,7 +653,8 @@ static _Bool mci_simulatenous_trans_missing(int mci_index) */ debug_enter(); mci_mmio_write_32(MCI_ACCESS_CMD_REG(0), - MCI_INDIRECT_REG_CTRL_ADDR(MCI_HB_CTRL_WIN0_DESTINATION_REG_NUM) | + MCI_INDIRECT_REG_CTRL_ADDR( + MCI_HB_CTRL_WIN0_DESTINATION_REG_NUM) | MCI_INDIRECT_CTRL_HOPID(GID_AXI_HB) | MCI_INDIRECT_CTRL_LOCAL_PKT | MCI_INDIRECT_CTRL_READ_CMD); @@ -571,7 +663,7 @@ static _Bool mci_simulatenous_trans_missing(int mci_index) reg = mci_mmio_read_32(MCI_WRITE_READ_DATA_REG(mci_index)); if (ret) - ERROR("Failed to verify if MCI simultaneous read/write was enabled\n"); + ERROR("Failed to verify MCI simultaneous read/write status\n"); debug_exit(); /* default ID assignment is 0, so if register doesn't contain zeros @@ -605,12 +697,14 @@ int mci_configure(int mci_index) */ if (mci_simulatenous_trans_missing(mci_index)) { VERBOSE("Enabling MCI simultaneous transaction\n"); - /* set MCI to support read/write transactions to arrive at the same time */ + /* set MCI to support read/write transactions + * to arrive at the same time + */ rval = mci_enable_simultaneous_transactions(mci_index); if (rval) - ERROR("Failed to set MCI for simultaneous read/write transactions\n"); + ERROR("Failed to set MCI simultaneous read/write\n"); } else - VERBOSE("Skipping MCI ID assignment - already done by bootrom\n"); + VERBOSE("Skip MCI ID assignment - already done by bootrom\n"); /* Configure MCI for more consistent behavior with AXI protocol */ rval = mci_axi_set_pcie_mode(mci_index); @@ -661,24 +755,30 @@ void mci_turn_link_down(void) /* Turn off auto-link */ cmd = (MCI_INDIRECT_REG_CTRL_ADDR(MCI_CTRL_MCI_PHY_SETTINGS_REG_NUM) | MCI_INDIRECT_CTRL_LOCAL_PKT); - data = (MCI_CTRL_MCI_PHY_SET_REG_DEF_VAL2 | MCI_CTRL_MCI_PHY_SET_AUTO_LINK_EN(0)); + data = (MCI_CTRL_MCI_PHY_SET_REG_DEF_VAL2 | + MCI_CTRL_MCI_PHY_SET_AUTO_LINK_EN(0)); rval = mci_write(0, cmd, data); if (rval) ERROR("Failed to turn off auto-link\n"); /* Reset AP PHY */ - cmd = (MCI_INDIRECT_REG_CTRL_ADDR(MCI_PHY_CTRL_REG_NUM) | MCI_INDIRECT_CTRL_LOCAL_PKT); - data = (MCI_PHY_CTRL_MCI_MINOR | MCI_PHY_CTRL_MCI_MAJOR | - MCI_PHY_CTRL_MCI_PHY_MODE_HOST | MCI_PHY_CTRL_MCI_PHY_RESET_CORE); + cmd = (MCI_INDIRECT_REG_CTRL_ADDR(MCI_PHY_CTRL_REG_NUM) | + MCI_INDIRECT_CTRL_LOCAL_PKT); + data = (MCI_PHY_CTRL_MCI_MINOR | + MCI_PHY_CTRL_MCI_MAJOR | + MCI_PHY_CTRL_MCI_PHY_MODE_HOST | + MCI_PHY_CTRL_MCI_PHY_RESET_CORE); rval = mci_write(0, cmd, data); if (rval) ERROR("Failed to reset AP PHY\n"); /* Clear all status & CRC values */ - cmd = (MCI_INDIRECT_REG_CTRL_ADDR(MCI_LINK_CRC_CTRL_REG_NUM) | MCI_INDIRECT_CTRL_LOCAL_PKT); + cmd = (MCI_INDIRECT_REG_CTRL_ADDR(MCI_LINK_CRC_CTRL_REG_NUM) | + MCI_INDIRECT_CTRL_LOCAL_PKT); data = 0x0; mci_write(0, cmd, data); - cmd = (MCI_INDIRECT_REG_CTRL_ADDR(MCI_CTRL_STATUS_REG_NUM) | MCI_INDIRECT_CTRL_LOCAL_PKT); + cmd = (MCI_INDIRECT_REG_CTRL_ADDR(MCI_CTRL_STATUS_REG_NUM) | + MCI_INDIRECT_CTRL_LOCAL_PKT); data = 0x0; rval = mci_write(0, cmd, data); if (rval) @@ -688,8 +788,10 @@ void mci_turn_link_down(void) mdelay(5); /* Un-reset AP PHY */ - cmd = (MCI_INDIRECT_REG_CTRL_ADDR(MCI_PHY_CTRL_REG_NUM) | MCI_INDIRECT_CTRL_LOCAL_PKT); - data = (MCI_PHY_CTRL_MCI_MINOR | MCI_PHY_CTRL_MCI_MAJOR | MCI_PHY_CTRL_MCI_PHY_MODE_HOST); + cmd = (MCI_INDIRECT_REG_CTRL_ADDR(MCI_PHY_CTRL_REG_NUM) | + MCI_INDIRECT_CTRL_LOCAL_PKT); + data = (MCI_PHY_CTRL_MCI_MINOR | MCI_PHY_CTRL_MCI_MAJOR | + MCI_PHY_CTRL_MCI_PHY_MODE_HOST); rval = mci_write(0, cmd, data); if (rval) ERROR("Failed to un-reset AP PHY\n"); @@ -706,7 +808,8 @@ void mci_turn_link_on(void) /* Turn on auto-link */ cmd = (MCI_INDIRECT_REG_CTRL_ADDR(MCI_CTRL_MCI_PHY_SETTINGS_REG_NUM) | MCI_INDIRECT_CTRL_LOCAL_PKT); - data = (MCI_CTRL_MCI_PHY_SET_REG_DEF_VAL2 | MCI_CTRL_MCI_PHY_SET_AUTO_LINK_EN(1)); + data = (MCI_CTRL_MCI_PHY_SET_REG_DEF_VAL2 | + MCI_CTRL_MCI_PHY_SET_AUTO_LINK_EN(1)); rval = mci_write(0, cmd, data); if (rval) ERROR("Failed to turn on auto-link\n"); diff --git a/drivers/marvell/mochi/ap807_setup.c b/drivers/marvell/mochi/ap807_setup.c index b3f5fa3b..075ca31f 100644 --- a/drivers/marvell/mochi/ap807_setup.c +++ b/drivers/marvell/mochi/ap807_setup.c @@ -5,6 +5,8 @@ * https://spdx.org/licenses */ +/* AP807 Marvell SoC driver */ + #include <ap_setup.h> #include <cache_llc.h> #include <ccu.h> @@ -12,15 +14,17 @@ #include <io_win.h> #include <mci.h> #include <mmio.h> -#include <plat_def.h> +#include <mvebu_def.h> #define SMMU_sACR (MVEBU_SMMU_BASE + 0x10) #define SMMU_sACR_PG_64K (1 << 16) -#define CCU_GSPMU_CR (MVEBU_CCU_BASE(MVEBU_AP0) + 0x3F0) +#define CCU_GSPMU_CR (MVEBU_CCU_BASE(MVEBU_AP0) \ + + 0x3F0) #define GSPMU_CPU_CONTROL (0x1 << 0) -#define CCU_HTC_CR (MVEBU_CCU_BASE(MVEBU_AP0) + 0x200) +#define CCU_HTC_CR (MVEBU_CCU_BASE(MVEBU_AP0) \ + + 0x200) #define CCU_SET_POC_OFFSET 5 #define DSS_CR0 (MVEBU_RFU_BASE + 0x100) @@ -49,7 +53,8 @@ /* Used for Units of AP-807 (e.g. SDIO and etc) */ #define MVEBU_AXI_ATTR_BASE (MVEBU_REGS_BASE + 0x6F4580) -#define MVEBU_AXI_ATTR_REG(index) (MVEBU_AXI_ATTR_BASE + 0x4 * index) +#define MVEBU_AXI_ATTR_REG(index) (MVEBU_AXI_ATTR_BASE + \ + 0x4 * index) enum axi_attr { AXI_SDIO_ATTR = 0, @@ -67,9 +72,11 @@ static void ap_sec_masters_access_en(uint32_t enable) */ reg = mmio_read_32(SEC_MOCHI_IN_ACC_REG); if (enable) - mmio_write_32(SEC_MOCHI_IN_ACC_REG, reg | SEC_IN_ACCESS_ENA_ALL_MASTERS); + mmio_write_32(SEC_MOCHI_IN_ACC_REG, reg | + SEC_IN_ACCESS_ENA_ALL_MASTERS); else - mmio_write_32(SEC_MOCHI_IN_ACC_REG, reg & ~SEC_IN_ACCESS_ENA_ALL_MASTERS); + mmio_write_32(SEC_MOCHI_IN_ACC_REG, + reg & ~SEC_IN_ACCESS_ENA_ALL_MASTERS); } static void setup_smmu(void) @@ -117,7 +124,8 @@ static void mci_remap_indirect_access_base(void) for (mci = 0; mci < MCI_MAX_UNIT_ID; mci++) mmio_write_32(MCIX4_REG_START_ADDRESS_REG(mci), - MVEBU_MCI_REG_BASE_REMAP(mci) >> MCI_REMAP_OFF_SHIFT); + MVEBU_MCI_REG_BASE_REMAP(mci) >> + MCI_REMAP_OFF_SHIFT); } static void ap807_axi_attr_init(void) @@ -134,27 +142,32 @@ static void ap807_axi_attr_init(void) case AXI_DFX_ATTR: continue; default: - /* Set Ax-Cache as cacheable, no allocate, modifiable, bufferable - * The values are different because Read & Write definition - * is different in Ax-Cache + /* Set Ax-Cache as cacheable, no allocate, modifiable, + * bufferable. + * The values are different because Read & Write + * definition is different in Ax-Cache */ data = mmio_read_32(MVEBU_AXI_ATTR_REG(index)); data &= ~MVEBU_AXI_ATTR_ARCACHE_MASK; - data |= (CACHE_ATTR_WRITE_ALLOC | CACHE_ATTR_CACHEABLE | CACHE_ATTR_BUFFERABLE) - << MVEBU_AXI_ATTR_ARCACHE_OFFSET; + data |= (CACHE_ATTR_WRITE_ALLOC | + CACHE_ATTR_CACHEABLE | + CACHE_ATTR_BUFFERABLE) << + MVEBU_AXI_ATTR_ARCACHE_OFFSET; data &= ~MVEBU_AXI_ATTR_AWCACHE_MASK; - data |= (CACHE_ATTR_READ_ALLOC | CACHE_ATTR_CACHEABLE | CACHE_ATTR_BUFFERABLE) - << MVEBU_AXI_ATTR_AWCACHE_OFFSET; + data |= (CACHE_ATTR_READ_ALLOC | + CACHE_ATTR_CACHEABLE | + CACHE_ATTR_BUFFERABLE) << + MVEBU_AXI_ATTR_AWCACHE_OFFSET; /* Set Ax-Domain as Outer domain */ data &= ~MVEBU_AXI_ATTR_ARDOMAIN_MASK; - data |= DOMAIN_OUTER_SHAREABLE << MVEBU_AXI_ATTR_ARDOMAIN_OFFSET; + data |= DOMAIN_OUTER_SHAREABLE << + MVEBU_AXI_ATTR_ARDOMAIN_OFFSET; data &= ~MVEBU_AXI_ATTR_AWDOMAIN_MASK; - data |= DOMAIN_OUTER_SHAREABLE << MVEBU_AXI_ATTR_AWDOMAIN_OFFSET; + data |= DOMAIN_OUTER_SHAREABLE << + MVEBU_AXI_ATTR_AWDOMAIN_OFFSET; mmio_write_32(MVEBU_AXI_ATTR_REG(index), data); } } - - return; } static void misc_soc_configurations(void) @@ -165,7 +178,7 @@ static void misc_soc_configurations(void) mmio_setbits_32(DSS_CR0, DVM_48BIT_VA_ENABLE); /* Un-mask Watchdog reset from influencing the SYSRST_OUTn. - * Otherwise, upon WD timeout, the WD reset singal won't trigger reset + * Otherwise, upon WD timeout, the WD reset signal won't trigger reset */ reg = mmio_read_32(MVEBU_SYSRST_OUT_CONFIG_REG); reg &= ~(WD_MASK_SYS_RST_OUT); @@ -205,7 +218,8 @@ static void ap807_dram_phy_access_config(void) /* Update DSS port access permission to DSS_PHY */ reg_val = mmio_read_32(DSS_SCR_REG); reg_val &= ~(DSS_PPROT_MASK << DSS_PPROT_OFFS); - reg_val |= ((DSS_PPROT_PRIV_SECURE_DATA & DSS_PPROT_MASK) << DSS_PPROT_OFFS); + reg_val |= ((DSS_PPROT_PRIV_SECURE_DATA & DSS_PPROT_MASK) << + DSS_PPROT_OFFS); mmio_write_32(DSS_SCR_REG, reg_val); } diff --git a/drivers/marvell/mochi/ap810_setup.c b/drivers/marvell/mochi/ap810_setup.c index 6f1aadad..4252a49c 100644 --- a/drivers/marvell/mochi/ap810_setup.c +++ b/drivers/marvell/mochi/ap810_setup.c @@ -8,7 +8,7 @@ #include <ap810_setup.h> #include <debug.h> #include <mmio.h> -#include <plat_def.h> +#include <mvebu_def.h> #define CCU_B_GIDACR(ap, stop) (MVEBU_A2_BANKED_STOP_BASE(ap, stop) + 0x34) diff --git a/drivers/marvell/mochi/apn806_setup.c b/drivers/marvell/mochi/apn806_setup.c index 1fa7e4b0..10acbca3 100644 --- a/drivers/marvell/mochi/apn806_setup.c +++ b/drivers/marvell/mochi/apn806_setup.c @@ -1,10 +1,12 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ - + +/* AP806 Marvell SoC driver */ + #include <ap_setup.h> #include <ccu.h> #include <cache_llc.h> @@ -12,18 +14,21 @@ #include <io_win.h> #include <mci.h> #include <mmio.h> -#include <plat_def.h> +#include <mvebu_def.h> #define SMMU_sACR (MVEBU_SMMU_BASE + 0x10) #define SMMU_sACR_PG_64K (1 << 16) -#define CCU_GSPMU_CR (MVEBU_CCU_BASE(MVEBU_AP0) + 0x3F0) +#define CCU_GSPMU_CR (MVEBU_CCU_BASE(MVEBU_AP0) + \ + 0x3F0) #define GSPMU_CPU_CONTROL (0x1 << 0) -#define CCU_HTC_CR (MVEBU_CCU_BASE(MVEBU_AP0) + 0x200) +#define CCU_HTC_CR (MVEBU_CCU_BASE(MVEBU_AP0) + \ + 0x200) #define CCU_SET_POC_OFFSET 5 -#define CCU_RGF(win) (MVEBU_CCU_BASE(MVEBU_AP0) + 0x90 + 4 * (win)) +#define CCU_RGF(win) (MVEBU_CCU_BASE(MVEBU_AP0) + \ + 0x90 + 4 * (win)) #define DSS_CR0 (MVEBU_RFU_BASE + 0x100) #define DVM_48BIT_VA_ENABLE (1 << 21) @@ -53,7 +58,8 @@ /* Used for Units of AP-806 (e.g. SDIO and etc) */ #define MVEBU_AXI_ATTR_BASE (MVEBU_REGS_BASE + 0x6F4580) -#define MVEBU_AXI_ATTR_REG(index) (MVEBU_AXI_ATTR_BASE + 0x4 * index) +#define MVEBU_AXI_ATTR_REG(index) (MVEBU_AXI_ATTR_BASE + \ + 0x4 * index) enum axi_attr { AXI_SDIO_ATTR = 0, @@ -71,9 +77,11 @@ static void apn_sec_masters_access_en(uint32_t enable) */ reg = mmio_read_32(SEC_MOCHI_IN_ACC_REG); if (enable) - mmio_write_32(SEC_MOCHI_IN_ACC_REG, reg | SEC_IN_ACCESS_ENA_ALL_MASTERS); + mmio_write_32(SEC_MOCHI_IN_ACC_REG, reg | + SEC_IN_ACCESS_ENA_ALL_MASTERS); else - mmio_write_32(SEC_MOCHI_IN_ACC_REG, reg & ~SEC_IN_ACCESS_ENA_ALL_MASTERS); + mmio_write_32(SEC_MOCHI_IN_ACC_REG, reg & + ~SEC_IN_ACCESS_ENA_ALL_MASTERS); } static void setup_smmu(void) @@ -102,7 +110,7 @@ static void ap806_generic_timer_init(void) static void apn806_errata_wa_init(void) { /* - * EERATA ID: RES-3033912 - Internal Address Space Init state causes + * ERRATA ID: RES-3033912 - Internal Address Space Init state causes * a hang upon accesses to [0xf070_0000, 0xf07f_ffff] * Workaround: Boot Firmware (ATF) should configure CCU_RGF_WIN(4) to * split [0x6e_0000, 0xff_ffff] to values [0x6e_0000, 0x6f_ffff] and @@ -150,7 +158,8 @@ static void mci_remap_indirect_access_base(void) for (mci = 0; mci < MCI_MAX_UNIT_ID; mci++) mmio_write_32(MCIX4_REG_START_ADDRESS_REG(mci), - MVEBU_MCI_REG_BASE_REMAP(mci) >> MCI_REMAP_OFF_SHIFT); + MVEBU_MCI_REG_BASE_REMAP(mci) >> + MCI_REMAP_OFF_SHIFT); } static void apn806_axi_attr_init(void) @@ -168,27 +177,32 @@ static void apn806_axi_attr_init(void) case AXI_DFX_ATTR: continue; default: - /* Set Ax-Cache as cacheable, no allocate, modifiable, bufferable - * The values are different because Read & Write definition - * is different in Ax-Cache + /* Set Ax-Cache as cacheable, no allocate, modifiable, + * bufferable + * The values are different because Read & Write + * definition is different in Ax-Cache */ data = mmio_read_32(MVEBU_AXI_ATTR_REG(index)); data &= ~MVEBU_AXI_ATTR_ARCACHE_MASK; - data |= (CACHE_ATTR_WRITE_ALLOC | CACHE_ATTR_CACHEABLE | CACHE_ATTR_BUFFERABLE) - << MVEBU_AXI_ATTR_ARCACHE_OFFSET; + data |= (CACHE_ATTR_WRITE_ALLOC | + CACHE_ATTR_CACHEABLE | + CACHE_ATTR_BUFFERABLE) << + MVEBU_AXI_ATTR_ARCACHE_OFFSET; data &= ~MVEBU_AXI_ATTR_AWCACHE_MASK; - data |= (CACHE_ATTR_READ_ALLOC | CACHE_ATTR_CACHEABLE | CACHE_ATTR_BUFFERABLE) - << MVEBU_AXI_ATTR_AWCACHE_OFFSET; + data |= (CACHE_ATTR_READ_ALLOC | + CACHE_ATTR_CACHEABLE | + CACHE_ATTR_BUFFERABLE) << + MVEBU_AXI_ATTR_AWCACHE_OFFSET; /* Set Ax-Domain as Outer domain */ data &= ~MVEBU_AXI_ATTR_ARDOMAIN_MASK; - data |= DOMAIN_OUTER_SHAREABLE << MVEBU_AXI_ATTR_ARDOMAIN_OFFSET; + data |= DOMAIN_OUTER_SHAREABLE << + MVEBU_AXI_ATTR_ARDOMAIN_OFFSET; data &= ~MVEBU_AXI_ATTR_AWDOMAIN_MASK; - data |= DOMAIN_OUTER_SHAREABLE << MVEBU_AXI_ATTR_AWDOMAIN_OFFSET; + data |= DOMAIN_OUTER_SHAREABLE << + MVEBU_AXI_ATTR_AWDOMAIN_OFFSET; mmio_write_32(MVEBU_AXI_ATTR_REG(index), data); } } - - return; } static void dss_setup(void) @@ -202,7 +216,7 @@ void misc_soc_configurations(void) uint32_t reg; /* Un-mask Watchdog reset from influencing the SYSRST_OUTn. - * Otherwise, upon WD timeout, the WD reset singal won't trigger reset + * Otherwise, upon WD timeout, the WD reset signal won't trigger reset */ reg = mmio_read_32(MVEBU_SYSRST_OUT_CONFIG_REG); reg &= ~(WD_MASK_SYS_RST_OUT); @@ -239,8 +253,10 @@ void ap_init(void) misc_soc_configurations(); #if PALLADIUM - /* This code required to Palladium run only, BootROM init the generic timer - and BootROM isn't running for Palladium */ + /* This code required to Palladium run only, + * BootROM init the generic timer + * and BootROM isn't running for Palladium + */ ap806_generic_timer_init(); #endif } diff --git a/drivers/marvell/mochi/cp110_setup.c b/drivers/marvell/mochi/cp110_setup.c index a655af69..79a9c491 100644 --- a/drivers/marvell/mochi/cp110_setup.c +++ b/drivers/marvell/mochi/cp110_setup.c @@ -1,10 +1,12 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ - + +/* CP110 Marvell SoC driver */ + #include <amb_adec.h> #include <cp110_setup.h> #include <debug.h> @@ -65,88 +67,90 @@ static const struct icu_config icu_config = { */ /* Used for Units of CP-110 (e.g. USB device, USB Host, and etc) */ -#define MVEBU_AXI_ATTR_OFFSET (0x441300) -#define MVEBU_AXI_ATTR_REG(index) (MVEBU_AXI_ATTR_OFFSET + 0x4 * index) +#define MVEBU_AXI_ATTR_OFFSET (0x441300) +#define MVEBU_AXI_ATTR_REG(index) (MVEBU_AXI_ATTR_OFFSET + \ + 0x4 * index) /* AXI Protection bits */ -#define MVEBU_AXI_PROT_OFFSET (0x441200) +#define MVEBU_AXI_PROT_OFFSET (0x441200) /* AXI Protection regs */ -#define MVEBU_AXI_PROT_REG(index) ((index <= 4) ? (MVEBU_AXI_PROT_OFFSET + 0x4 * index) : \ - (MVEBU_AXI_PROT_OFFSET + 0x18)) -#define MVEBU_AXI_PROT_REGS_NUM (6) - -#define MVEBU_SOC_CFGS_OFFSET (0x441900) -#define MVEBU_SOC_CFG_REG(index) (MVEBU_SOC_CFGS_OFFSET + 0x4 * index) -#define MVEBU_SOC_CFG_REG_NUM (0) -#define MVEBU_SOC_CFG_GLOG_SECURE_EN_MASK (0xE) +#define MVEBU_AXI_PROT_REG(index) ((index <= 4) ? \ + (MVEBU_AXI_PROT_OFFSET + \ + 0x4 * index) : \ + (MVEBU_AXI_PROT_OFFSET + 0x18)) +#define MVEBU_AXI_PROT_REGS_NUM (6) + +#define MVEBU_SOC_CFGS_OFFSET (0x441900) +#define MVEBU_SOC_CFG_REG(index) (MVEBU_SOC_CFGS_OFFSET + \ + 0x4 * index) +#define MVEBU_SOC_CFG_REG_NUM (0) +#define MVEBU_SOC_CFG_GLOG_SECURE_EN_MASK (0xE) /* SATA3 MBUS to AXI regs */ -#define MVEBU_BRIDGE_WIN_DIS_REG (MVEBU_SOC_CFGS_OFFSET + 0x10) -#define MVEBU_BRIDGE_WIN_DIS_OFF (0x0) +#define MVEBU_BRIDGE_WIN_DIS_REG (MVEBU_SOC_CFGS_OFFSET + 0x10) +#define MVEBU_BRIDGE_WIN_DIS_OFF (0x0) /* SATA3 MBUS to AXI regs */ -#define MVEBU_SATA_M2A_AXI_PORT_CTRL_REG (0x54ff04) +#define MVEBU_SATA_M2A_AXI_PORT_CTRL_REG (0x54ff04) /* AXI to MBUS bridge registers */ -#define MVEBU_AMB_IP_OFFSET (0x13ff00) -#define MVEBU_AMB_IP_BRIDGE_WIN_REG(win) (MVEBU_AMB_IP_OFFSET + (win * 0x8)) -#define MVEBU_AMB_IP_BRIDGE_WIN_EN_OFFSET 0 -#define MVEBU_AMB_IP_BRIDGE_WIN_EN_MASK (0x1 << MVEBU_AMB_IP_BRIDGE_WIN_EN_OFFSET) -#define MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET 16 -#define MVEBU_AMB_IP_BRIDGE_WIN_SIZE_MASK (0xffff << MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET) - -#define MVEBU_SAMPLE_AT_RESET_REG (0x440600) -#define SAR_PCIE1_CLK_CFG_OFFSET 31 -#define SAR_PCIE1_CLK_CFG_MASK (0x1 << SAR_PCIE1_CLK_CFG_OFFSET) -#define SAR_PCIE0_CLK_CFG_OFFSET 30 -#define SAR_PCIE0_CLK_CFG_MASK (0x1 << SAR_PCIE0_CLK_CFG_OFFSET) -#define SAR_I2C_INIT_EN_OFFSET 24 -#define SAR_I2C_INIT_EN_MASK (1 << SAR_I2C_INIT_EN_OFFSET) +#define MVEBU_AMB_IP_OFFSET (0x13ff00) +#define MVEBU_AMB_IP_BRIDGE_WIN_REG(win) (MVEBU_AMB_IP_OFFSET + \ + (win * 0x8)) +#define MVEBU_AMB_IP_BRIDGE_WIN_EN_OFFSET 0 +#define MVEBU_AMB_IP_BRIDGE_WIN_EN_MASK \ + (0x1 << MVEBU_AMB_IP_BRIDGE_WIN_EN_OFFSET) +#define MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET 16 +#define MVEBU_AMB_IP_BRIDGE_WIN_SIZE_MASK \ + (0xffff << MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET) + +#define MVEBU_SAMPLE_AT_RESET_REG (0x440600) +#define SAR_PCIE1_CLK_CFG_OFFSET 31 +#define SAR_PCIE1_CLK_CFG_MASK (0x1 << SAR_PCIE1_CLK_CFG_OFFSET) +#define SAR_PCIE0_CLK_CFG_OFFSET 30 +#define SAR_PCIE0_CLK_CFG_MASK (0x1 << SAR_PCIE0_CLK_CFG_OFFSET) +#define SAR_I2C_INIT_EN_OFFSET 24 +#define SAR_I2C_INIT_EN_MASK (1 << SAR_I2C_INIT_EN_OFFSET) /******************************************************************************* * PCIE clock buffer control ******************************************************************************/ -#define MVEBU_PCIE_REF_CLK_BUF_CTRL (0x4404F0) -#define PCIE1_REFCLK_BUFF_SOURCE 0x800 -#define PCIE0_REFCLK_BUFF_SOURCE 0x400 +#define MVEBU_PCIE_REF_CLK_BUF_CTRL (0x4404F0) +#define PCIE1_REFCLK_BUFF_SOURCE 0x800 +#define PCIE0_REFCLK_BUFF_SOURCE 0x400 /******************************************************************************* * MSS Device Push Set Register ******************************************************************************/ -#define MVEBU_CP_MSS_DPSHSR_REG (0x280040) -#define MSS_DPSHSR_REG_PCIE_CLK_SEL 0x8 +#define MVEBU_CP_MSS_DPSHSR_REG (0x280040) +#define MSS_DPSHSR_REG_PCIE_CLK_SEL 0x8 /******************************************************************************* * RTC Configuration ******************************************************************************/ -#define MVEBU_RTC_BASE (0x284000) -#define MVEBU_RTC_STATUS_REG (MVEBU_RTC_BASE + 0x0) -#define MVEBU_RTC_STATUS_ALARM1_MASK 0x1 -#define MVEBU_RTC_STATUS_ALARM2_MASK 0x2 -#define MVEBU_RTC_IRQ_1_CONFIG_REG (MVEBU_RTC_BASE + 0x4) -#define MVEBU_RTC_IRQ_2_CONFIG_REG (MVEBU_RTC_BASE + 0x8) -#define MVEBU_RTC_TIME_REG (MVEBU_RTC_BASE + 0xC) -#define MVEBU_RTC_ALARM_1_REG (MVEBU_RTC_BASE + 0x10) -#define MVEBU_RTC_ALARM_2_REG (MVEBU_RTC_BASE + 0x14) -#define MVEBU_RTC_CCR_REG (MVEBU_RTC_BASE + 0x18) -#define MVEBU_RTC_NOMINAL_TIMING 0x2000 -#define MVEBU_RTC_NOMINAL_TIMING_MASK 0x7FFF -#define MVEBU_RTC_TEST_CONFIG_REG (MVEBU_RTC_BASE + 0x1C) -#define MVEBU_RTC_BRIDGE_TIMING_CTRL0_REG (MVEBU_RTC_BASE + 0x80) -#define MVEBU_RTC_WRCLK_PERIOD_MASK 0xFFFF -#define MVEBU_RTC_WRCLK_PERIOD_DEFAULT 0x3FF -#define MVEBU_RTC_WRCLK_SETUP_OFFS 16 -#define MVEBU_RTC_WRCLK_SETUP_MASK 0xFFFF0000 -#define MVEBU_RTC_WRCLK_SETUP_DEFAULT 0x29 -#define MVEBU_RTC_BRIDGE_TIMING_CTRL1_REG (MVEBU_RTC_BASE + 0x84) -#define MVEBU_RTC_READ_OUTPUT_DELAY_MASK 0xFFFF -#define MVEBU_RTC_READ_OUTPUT_DELAY_DEFAULT 0x1F - -/* Errata */ -/* This bit disables internal HW fix for CP i2c init on REV A1 and later */ -#define MVEBU_CONF_I2C_INIT_SEL_BIT (4) -#define MVEBU_CONF_I2C_INIT_SEL_MASK (1 << MVEBU_CONF_I2C_INIT_SEL_BIT) +#define MVEBU_RTC_BASE (0x284000) +#define MVEBU_RTC_STATUS_REG (MVEBU_RTC_BASE + 0x0) +#define MVEBU_RTC_STATUS_ALARM1_MASK 0x1 +#define MVEBU_RTC_STATUS_ALARM2_MASK 0x2 +#define MVEBU_RTC_IRQ_1_CONFIG_REG (MVEBU_RTC_BASE + 0x4) +#define MVEBU_RTC_IRQ_2_CONFIG_REG (MVEBU_RTC_BASE + 0x8) +#define MVEBU_RTC_TIME_REG (MVEBU_RTC_BASE + 0xC) +#define MVEBU_RTC_ALARM_1_REG (MVEBU_RTC_BASE + 0x10) +#define MVEBU_RTC_ALARM_2_REG (MVEBU_RTC_BASE + 0x14) +#define MVEBU_RTC_CCR_REG (MVEBU_RTC_BASE + 0x18) +#define MVEBU_RTC_NOMINAL_TIMING 0x2000 +#define MVEBU_RTC_NOMINAL_TIMING_MASK 0x7FFF +#define MVEBU_RTC_TEST_CONFIG_REG (MVEBU_RTC_BASE + 0x1C) +#define MVEBU_RTC_BRIDGE_TIMING_CTRL0_REG (MVEBU_RTC_BASE + 0x80) +#define MVEBU_RTC_WRCLK_PERIOD_MASK 0xFFFF +#define MVEBU_RTC_WRCLK_PERIOD_DEFAULT 0x3FF +#define MVEBU_RTC_WRCLK_SETUP_OFFS 16 +#define MVEBU_RTC_WRCLK_SETUP_MASK 0xFFFF0000 +#define MVEBU_RTC_WRCLK_SETUP_DEFAULT 0x29 +#define MVEBU_RTC_BRIDGE_TIMING_CTRL1_REG (MVEBU_RTC_BASE + 0x84) +#define MVEBU_RTC_READ_OUTPUT_DELAY_MASK 0xFFFF +#define MVEBU_RTC_READ_OUTPUT_DELAY_DEFAULT 0x1F enum axi_attr { AXI_ADUNIT_ATTR = 0, @@ -195,8 +199,10 @@ static void cp110_errata_wa_init(uintptr_t base) uint32_t data; /* ERRATA GL-4076863: - * Reset value for global_secure_enable inputs must be changed from '1' to '0'. - * When asserted, only "secured" transactions can enter IHB configuration space. + * Reset value for global_secure_enable inputs must be changed + * from '1' to '0'. + * When asserted, only "secured" transactions can enter IHB + * configuration space. * However, blocking AXI transactions is performed by IOB. * Performing it also at IHB/HB complicates programming model. * @@ -257,7 +263,7 @@ static void cp110_stream_id_init(uintptr_t base, uint32_t stream_id) while (stream_id_reg[i]) { if (i > MAX_STREAM_ID_PER_CP) { - NOTICE("Too many Stream IDs per CP, allocate only the first %d Stream IDs\n", + NOTICE("Only first %d (maximum) Stream IDs allocated\n", MAX_STREAM_ID_PER_CP); return; } @@ -295,22 +301,29 @@ static void cp110_axi_attr_init(uintptr_t base) case AXI_MSS_ATTR: continue; default: - /* Set Ax-Cache as cacheable, no allocate, modifiable, bufferable - * The values are different because Read & Write definition - * is different in Ax-Cache + /* Set Ax-Cache as cacheable, no allocate, modifiable, + * bufferable + * The values are different because Read & Write + * definition is different in Ax-Cache */ data = mmio_read_32(base + MVEBU_AXI_ATTR_REG(index)); data &= ~MVEBU_AXI_ATTR_ARCACHE_MASK; - data |= (CACHE_ATTR_WRITE_ALLOC | CACHE_ATTR_CACHEABLE | CACHE_ATTR_BUFFERABLE) - << MVEBU_AXI_ATTR_ARCACHE_OFFSET; + data |= (CACHE_ATTR_WRITE_ALLOC | + CACHE_ATTR_CACHEABLE | + CACHE_ATTR_BUFFERABLE) << + MVEBU_AXI_ATTR_ARCACHE_OFFSET; data &= ~MVEBU_AXI_ATTR_AWCACHE_MASK; - data |= (CACHE_ATTR_READ_ALLOC | CACHE_ATTR_CACHEABLE | CACHE_ATTR_BUFFERABLE) - << MVEBU_AXI_ATTR_AWCACHE_OFFSET; + data |= (CACHE_ATTR_READ_ALLOC | + CACHE_ATTR_CACHEABLE | + CACHE_ATTR_BUFFERABLE) << + MVEBU_AXI_ATTR_AWCACHE_OFFSET; /* Set Ax-Domain as Outer domain */ data &= ~MVEBU_AXI_ATTR_ARDOMAIN_MASK; - data |= DOMAIN_OUTER_SHAREABLE << MVEBU_AXI_ATTR_ARDOMAIN_OFFSET; + data |= DOMAIN_OUTER_SHAREABLE << + MVEBU_AXI_ATTR_ARDOMAIN_OFFSET; data &= ~MVEBU_AXI_ATTR_AWDOMAIN_MASK; - data |= DOMAIN_OUTER_SHAREABLE << MVEBU_AXI_ATTR_AWDOMAIN_OFFSET; + data |= DOMAIN_OUTER_SHAREABLE << + MVEBU_AXI_ATTR_AWDOMAIN_OFFSET; mmio_write_32(base + MVEBU_AXI_ATTR_REG(index), data); } } @@ -321,18 +334,21 @@ static void cp110_axi_attr_init(uintptr_t base) */ data = mmio_read_32(base + MVEBU_SATA_M2A_AXI_PORT_CTRL_REG); data &= ~MVEBU_SATA_M2A_AXI_AWCACHE_MASK; - data |= (CACHE_ATTR_WRITE_ALLOC | CACHE_ATTR_CACHEABLE | CACHE_ATTR_BUFFERABLE) - << MVEBU_SATA_M2A_AXI_AWCACHE_OFFSET; + data |= (CACHE_ATTR_WRITE_ALLOC | + CACHE_ATTR_CACHEABLE | + CACHE_ATTR_BUFFERABLE) << + MVEBU_SATA_M2A_AXI_AWCACHE_OFFSET; data &= ~MVEBU_SATA_M2A_AXI_ARCACHE_MASK; - data |= (CACHE_ATTR_READ_ALLOC | CACHE_ATTR_CACHEABLE | CACHE_ATTR_BUFFERABLE) - << MVEBU_SATA_M2A_AXI_ARCACHE_OFFSET; + data |= (CACHE_ATTR_READ_ALLOC | + CACHE_ATTR_CACHEABLE | + CACHE_ATTR_BUFFERABLE) << + MVEBU_SATA_M2A_AXI_ARCACHE_OFFSET; mmio_write_32(base + MVEBU_SATA_M2A_AXI_PORT_CTRL_REG, data); #endif /* Set all IO's AXI attribute to non-secure access. */ for (index = 0; index < MVEBU_AXI_PROT_REGS_NUM; index++) - mmio_write_32(base + MVEBU_AXI_PROT_REG(index), DOMAIN_SYSTEM_SHAREABLE); - - return; + mmio_write_32(base + MVEBU_AXI_PROT_REG(index), + DOMAIN_SYSTEM_SHAREABLE); } static void amb_bridge_init(uintptr_t base) @@ -341,8 +357,10 @@ static void amb_bridge_init(uintptr_t base) /* Open AMB bridge Window to Access COMPHY/MDIO registers */ reg = mmio_read_32(base + MVEBU_AMB_IP_BRIDGE_WIN_REG(0)); - reg &= ~(MVEBU_AMB_IP_BRIDGE_WIN_SIZE_MASK | MVEBU_AMB_IP_BRIDGE_WIN_EN_MASK); - reg |= (0x7ff << MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET | 0x1 << MVEBU_AMB_IP_BRIDGE_WIN_EN_OFFSET); + reg &= ~(MVEBU_AMB_IP_BRIDGE_WIN_SIZE_MASK | + MVEBU_AMB_IP_BRIDGE_WIN_EN_MASK); + reg |= (0x7ff << MVEBU_AMB_IP_BRIDGE_WIN_SIZE_OFFSET) | + (0x1 << MVEBU_AMB_IP_BRIDGE_WIN_EN_OFFSET); mmio_write_32(base + MVEBU_AMB_IP_BRIDGE_WIN_REG(0), reg); } @@ -355,7 +373,8 @@ static void cp110_rtc_init(uintptr_t base) mmio_clrsetbits_32(base + MVEBU_RTC_BRIDGE_TIMING_CTRL0_REG, MVEBU_RTC_WRCLK_SETUP_MASK, - MVEBU_RTC_WRCLK_SETUP_DEFAULT << MVEBU_RTC_WRCLK_SETUP_OFFS); + MVEBU_RTC_WRCLK_SETUP_DEFAULT << + MVEBU_RTC_WRCLK_SETUP_OFFS); mmio_clrsetbits_32(base + MVEBU_RTC_BRIDGE_TIMING_CTRL1_REG, MVEBU_RTC_READ_OUTPUT_DELAY_MASK, @@ -369,7 +388,7 @@ static void cp110_rtc_init(uintptr_t base) MVEBU_RTC_NOMINAL_TIMING_MASK) != MVEBU_RTC_NOMINAL_TIMING) { /* Reset Test register */ mmio_write_32(base + MVEBU_RTC_TEST_CONFIG_REG, 0); - udelay(500000); + mdelay(500); /* Reset Time register */ mmio_write_32(base + MVEBU_RTC_TIME_REG, 0); @@ -377,7 +396,8 @@ static void cp110_rtc_init(uintptr_t base) /* Reset Status register */ mmio_write_32(base + MVEBU_RTC_STATUS_REG, - (MVEBU_RTC_STATUS_ALARM1_MASK | MVEBU_RTC_STATUS_ALARM2_MASK)); + (MVEBU_RTC_STATUS_ALARM1_MASK | + MVEBU_RTC_STATUS_ALARM2_MASK)); udelay(62); /* Turn off Int1 and Int2 sources & clear the Alarm count */ @@ -387,7 +407,8 @@ static void cp110_rtc_init(uintptr_t base) mmio_write_32(base + MVEBU_RTC_ALARM_2_REG, 0); /* Setup nominal register access timing */ - mmio_write_32(base + MVEBU_RTC_CCR_REG, MVEBU_RTC_NOMINAL_TIMING); + mmio_write_32(base + MVEBU_RTC_CCR_REG, + MVEBU_RTC_NOMINAL_TIMING); /* Reset Time register */ mmio_write_32(base + MVEBU_RTC_TIME_REG, 0); @@ -395,7 +416,8 @@ static void cp110_rtc_init(uintptr_t base) /* Reset Status register */ mmio_write_32(base + MVEBU_RTC_STATUS_REG, - (MVEBU_RTC_STATUS_ALARM1_MASK | MVEBU_RTC_STATUS_ALARM2_MASK)); + (MVEBU_RTC_STATUS_ALARM1_MASK | + MVEBU_RTC_STATUS_ALARM2_MASK)); udelay(50); } } @@ -403,7 +425,8 @@ static void cp110_rtc_init(uintptr_t base) static void cp110_amb_adec_init(uintptr_t base) { /* enable AXI-MBUS by clearing "Bridge Windows Disable" */ - mmio_clrbits_32(base + MVEBU_BRIDGE_WIN_DIS_REG, (1 << MVEBU_BRIDGE_WIN_DIS_OFF)); + mmio_clrbits_32(base + MVEBU_BRIDGE_WIN_DIS_REG, + (1 << MVEBU_BRIDGE_WIN_DIS_OFF)); /* configure AXI-MBUS windows for CP */ init_amb_adec(base); diff --git a/drivers/marvell/pcie-comphy-cp110.c b/drivers/marvell/pcie-comphy-cp110.c index 0ca667cb..e537a63d 100644 --- a/drivers/marvell/pcie-comphy-cp110.c +++ b/drivers/marvell/pcie-comphy-cp110.c @@ -4,11 +4,12 @@ * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + +#include "comphy.h" #include <debug.h> #include <delay_timer.h> #include <mmio.h> -#include <plat_def.h> -#include "comphy.h" +#include <mvebu_def.h> #include "pci_ep.h" #define SD_ADDR(base, lane) (base + 0x1000 * lane) diff --git a/drivers/marvell/thermal.c b/drivers/marvell/thermal.c index c2703d7a..c7ceb929 100644 --- a/drivers/marvell/thermal.c +++ b/drivers/marvell/thermal.c @@ -1,10 +1,12 @@ /* - * Copyright (C) 2017 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ +/* Driver for thermal unit located in Marvell ARMADA 8K and compatible SoCs */ + #include <debug.h> #include <thermal.h> |