diff options
Diffstat (limited to 'plat/marvell/a3700')
19 files changed, 277 insertions, 170 deletions
diff --git a/plat/marvell/a3700/a3700/board/pm_src.c b/plat/marvell/a3700/a3700/board/pm_src.c index 1c4958c6..bc48ce8c 100644 --- a/plat/marvell/a3700/a3700/board/pm_src.c +++ b/plat/marvell/a3700/a3700/board/pm_src.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses diff --git a/plat/marvell/a3700/a3700/plat_def.h b/plat/marvell/a3700/a3700/mvebu_def.h index 6a1ff0fa..c58f06bb 100644 --- a/plat/marvell/a3700/a3700/plat_def.h +++ b/plat/marvell/a3700/a3700/mvebu_def.h @@ -1,9 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * - * SPDX-License-Identifier: BSD-3-Clause + * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #ifndef __MVEBU_DEF_H__ #define __MVEBU_DEF_H__ diff --git a/plat/marvell/a3700/a3700/plat_bl31_setup.c b/plat/marvell/a3700/a3700/plat_bl31_setup.c index 1e813f32..a37af930 100644 --- a/plat/marvell/a3700/a3700/plat_bl31_setup.c +++ b/plat/marvell/a3700/a3700/plat_bl31_setup.c @@ -1,16 +1,17 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #include <a3700_dram_cs.h> +#include <armada_common.h> #include <dram_win.h> #include <io_addr_dec.h> #include <mmio.h> -#include <plat_config.h> +#include <marvell_plat_priv.h> #include <plat_marvell.h> -#include <plat_private.h> #include <sys_info.h> /* This function passes DRAM cpu decode window information in ATF to sys info */ @@ -47,7 +48,8 @@ static void marvell_bl31_mpp_init(void) * And anyway, this bit value should be 1 in all modes, * so here we does not judge boot mode and set this bit to 1 always. */ - mmio_setbits_32(MVEBU_NB_GPIO_OUTPUT_EN_HIGH_REG, 1 << MVEBU_GPIO_NB_SPI_PIN_MODE_OFF); + mmio_setbits_32(MVEBU_NB_GPIO_OUTPUT_EN_HIGH_REG, + 1 << MVEBU_GPIO_NB_SPI_PIN_MODE_OFF); } /* This function overruns the same function in marvell_bl31_setup.c */ diff --git a/plat/marvell/a3700/a3700/platform.mk b/plat/marvell/a3700/a3700/platform.mk index d2316f67..4f7ac08c 100644 --- a/plat/marvell/a3700/a3700/platform.mk +++ b/plat/marvell/a3700/a3700/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (C) 2016 - 2018 Marvell International Ltd. +# Copyright (C) 2018 Marvell International Ltd. # # SPDX-License-Identifier: BSD-3-Clause # https://spdx.org/licenses diff --git a/plat/marvell/a3700/common/a3700_common.mk b/plat/marvell/a3700/common/a3700_common.mk index d963284a..54f8bdaa 100644 --- a/plat/marvell/a3700/common/a3700_common.mk +++ b/plat/marvell/a3700/common/a3700_common.mk @@ -1,5 +1,5 @@ # -# Copyright (C) 2016 Marvell International Ltd. +# Copyright (C) 2018 Marvell International Ltd. # # SPDX-License-Identifier: BSD-3-Clause # https://spdx.org/licenses @@ -36,16 +36,19 @@ endif #MARVELL_SECURE_BOOT TIMBUILD := $(DOIMAGEPATH)/script/buildtim.sh TIM2IMG := $(DOIMAGEPATH)/script/tim2img.pl -# WTMI_IMG is used to specify the customized RTOS image runing over CM3 processor. By default, it -# points to a baremetal binary of fuse programming in A3700_utils. +# WTMI_IMG is used to specify the customized RTOS image runing over +# Service CPU (CM3 processor). By the default, it points to a +# baremetal binary of fuse programming in A3700_utils. WTMI_IMG := $(DOIMAGEPATH)/wtmi/fuse/build/fuse.bin -# WTMI_SYSINIT_IMG is used for the system early initialization, such as AVS settings, clock-tree -# setup and dynamic DDR PHY training. After the initialization is done, this image will be wiped out +# WTMI_SYSINIT_IMG is used for the system early initialization, +# such as AVS settings, clock-tree setup and dynamic DDR PHY training. +# After the initialization is done, this image will be wiped out # from the memory and CM3 will continue with RTOS image or other application. WTMI_SYSINIT_IMG := $(DOIMAGEPATH)/wtmi/sys_init/build/sys_init.bin -# WTMI_MULTI_IMG is composed of CM3 RTOS image (WTMI_IMG) and sys-init image (WTMI_SYSINIT_IMG). +# WTMI_MULTI_IMG is composed of CM3 RTOS image (WTMI_IMG) +# and sys-init image (WTMI_SYSINIT_IMG). WTMI_MULTI_IMG := $(DOIMAGEPATH)/wtmi/build/wtmi.bin WTMI_ENC_IMG := $(DOIMAGEPATH)/wtmi/build/wtmi-enc.bin @@ -84,31 +87,31 @@ MARVELL_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ ATF_INCLUDES := -Iinclude/common/tbbr \ -Iinclude/drivers -PLAT_INCLUDES := -I$(PLAT_FAMILY_BASE)/$(PLAT) \ - -I$(PLAT_COMMON_BASE)/include \ - -I$(PLAT_INCLUDE_BASE)/common \ - -I$(MARVELL_DRV_BASE)/uart \ - -I$/drivers/arm/gic/common/ \ +PLAT_INCLUDES := -I$(PLAT_FAMILY_BASE)/$(PLAT) \ + -I$(PLAT_COMMON_BASE)/include \ + -I$(PLAT_INCLUDE_BASE)/common \ + -I$(MARVELL_DRV_BASE)/uart \ + -I$/drivers/arm/gic/common/ \ $(ATF_INCLUDES) -PLAT_BL_COMMON_SOURCES := $(PLAT_COMMON_BASE)/aarch64/a3700_common.c \ - drivers/console/aarch64/console.S \ - plat/marvell/common/marvell_cci.c \ +PLAT_BL_COMMON_SOURCES := $(PLAT_COMMON_BASE)/aarch64/a3700_common.c \ + drivers/console/aarch64/console.S \ + plat/marvell/common/marvell_cci.c \ $(MARVELL_DRV_BASE)/uart/a3700_console.S -BL1_SOURCES += $(PLAT_COMMON_BASE)/aarch64/plat_helpers.S \ +BL1_SOURCES += $(PLAT_COMMON_BASE)/aarch64/plat_helpers.S \ lib/cpus/aarch64/cortex_a53.S BL31_PORTING_SOURCES := $(PLAT_FAMILY_BASE)/$(PLAT)/board/pm_src.c BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ - $(PLAT_COMMON_BASE)/aarch64/plat_helpers.S \ + $(PLAT_COMMON_BASE)/aarch64/plat_helpers.S \ $(PLAT_COMMON_BASE)/plat_pm.c \ $(PLAT_COMMON_BASE)/a3700_dram_cs.c \ $(PLAT_COMMON_BASE)/dram_win.c \ $(PLAT_COMMON_BASE)/io_addr_dec.c \ - $(PLAT_COMMON_BASE)/marvell_plat_config.c \ - $(PLAT_FAMILY_BASE)/$(PLAT)/plat_bl31_setup.c \ + $(PLAT_COMMON_BASE)/marvell_plat_config.c \ + $(PLAT_FAMILY_BASE)/$(PLAT)/plat_bl31_setup.c \ plat/marvell/common/sys_info.c \ plat/marvell/common/marvell_gicv3.c \ $(MARVELL_GIC_SOURCES) \ @@ -154,11 +157,13 @@ ifeq ($(MARVELL_SECURE_BOOT),1) @echo -e "\t Secure boot. Encrypting wtmi and boot-image \n"; @echo -e "\t=======================================================\n"; @truncate -s %16 $(WTMI_MULTI_IMG) - @openssl enc -aes-256-cbc -e -in $(WTMI_MULTI_IMG) -out $(WTMI_ENC_IMG) \ + @openssl enc -aes-256-cbc -e -in $(WTMI_MULTI_IMG) \ + -out $(WTMI_ENC_IMG) \ -K `cat $(IMAGESPATH)/aes-256.txt` -k 0 -nosalt \ -iv `cat $(IMAGESPATH)/iv.txt` -p @truncate -s %16 $(BUILD_PLAT)/$(BOOT_IMAGE); - @openssl enc -aes-256-cbc -e -in $(BUILD_PLAT)/$(BOOT_IMAGE) -out $(BUILD_PLAT)/$(BOOT_ENC_IMAGE) \ + @openssl enc -aes-256-cbc -e -in $(BUILD_PLAT)/$(BOOT_IMAGE) \ + -out $(BUILD_PLAT)/$(BOOT_ENC_IMAGE) \ -K `cat $(IMAGESPATH)/aes-256.txt` -k 0 -nosalt \ -iv `cat $(IMAGESPATH)/iv.txt` -p endif diff --git a/plat/marvell/a3700/common/a3700_dram_cs.c b/plat/marvell/a3700/common/a3700_dram_cs.c index 400eea06..d894f1d5 100644 --- a/plat/marvell/a3700/common/a3700_dram_cs.c +++ b/plat/marvell/a3700/common/a3700_dram_cs.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses @@ -76,13 +76,18 @@ static struct dram_cs_addr_len_to_size dram_cs_addr_len_to_size_map[] = { {0x1A, TB_2_MB(4) } }; -static int marvell_dram_cs_get_size_by_addr_len(uint32_t addr_len_value, uint32_t *size_mbytes) +static int marvell_dram_cs_get_size_by_addr_len(uint32_t addr_len_value, + uint32_t *size_mbytes) { int i; - for (i = 0; i < sizeof(dram_cs_addr_len_to_size_map)/sizeof(struct dram_cs_addr_len_to_size); i++) { - if (dram_cs_addr_len_to_size_map[i].addr_len_value == addr_len_value) { - *size_mbytes = dram_cs_addr_len_to_size_map[i].size_mbytes; + for (i = 0; i < sizeof(dram_cs_addr_len_to_size_map)/ + sizeof(struct dram_cs_addr_len_to_size); i++) { + + if (dram_cs_addr_len_to_size_map[i].addr_len_value == + addr_len_value) { + *size_mbytes = + dram_cs_addr_len_to_size_map[i].size_mbytes; return 0; } } @@ -121,9 +126,11 @@ int marvell_get_dram_cs_base_size(uint32_t cs_num, if (!(cs_mmap_reg & MVEBU_CS_MMAP_ENABLE)) return -ENODEV; - *base_low = (cs_mmap_reg & MVEBU_CS_MMAP_START_ADDR_LOW_MASK) >> MVEBU_CS_MMAP_START_ADDR_LOW_OFFS; + *base_low = (cs_mmap_reg & MVEBU_CS_MMAP_START_ADDR_LOW_MASK) >> + MVEBU_CS_MMAP_START_ADDR_LOW_OFFS; *base_high = mmio_read_32(MVEBU_CS_MMAP_HIGH(cs_num)); - area_len = (cs_mmap_reg & MVEBU_CS_MMAP_AREA_LEN_MASK) >> MVEBU_CS_MMAP_AREA_LEN_OFFS; + area_len = (cs_mmap_reg & MVEBU_CS_MMAP_AREA_LEN_MASK) >> + MVEBU_CS_MMAP_AREA_LEN_OFFS; if (marvell_dram_cs_get_size_by_addr_len(area_len, size_mbytes)) return -EFAULT; diff --git a/plat/marvell/a3700/common/aarch64/a3700_common.c b/plat/marvell/a3700/common/aarch64/a3700_common.c index 07a3a2f6..e7840094 100644 --- a/plat/marvell/a3700/common/aarch64/a3700_common.c +++ b/plat/marvell/a3700/common/aarch64/a3700_common.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses diff --git a/plat/marvell/a3700/common/aarch64/plat_helpers.S b/plat/marvell/a3700/common/aarch64/plat_helpers.S index 9da72ad3..c132dcdd 100644 --- a/plat/marvell/a3700/common/aarch64/plat_helpers.S +++ b/plat/marvell/a3700/common/aarch64/plat_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses @@ -27,7 +27,7 @@ endfunc plat_secondary_cold_boot_setup /* --------------------------------------------------------------------- * unsigned long plat_get_my_entrypoint (void); * - * Main job of this routine is to distinguish between a cold and warm boot + * Main job of this routine is to distinguish between cold and warm boot * For a cold boot, return 0. * For a warm boot, read the mailbox and return the address it contains. * A magic number is placed before entrypoint to avoid mistake caused by @@ -35,16 +35,19 @@ endfunc plat_secondary_cold_boot_setup * --------------------------------------------------------------------- */ func plat_get_my_entrypoint - mov_imm x0, PLAT_MARVELL_MAILBOX_BASE /* Read first word and compare it with magic num */ - ldr x1, [x0] + /* Read first word and compare it with magic num */ + mov_imm x0, PLAT_MARVELL_MAILBOX_BASE + ldr x1, [x0] mov_imm x2, PLAT_MARVELL_MAILBOX_MAGIC_NUM - cmp x1, x2 - beq entrypoint /* If compare failed, return 0, i.e. cold boot */ - mov x0, #0 + cmp x1, x2 + /* If compare failed, return 0, i.e. cold boot */ + beq entrypoint + mov x0, #0 ret entrypoint: - add x0, x0, #8 /* Second word contains the jump address */ - ldr x0, [x0] + /* Second word contains the jump address */ + add x0, x0, #8 + ldr x0, [x0] ret endfunc plat_get_my_entrypoint diff --git a/plat/marvell/a3700/common/dram_win.c b/plat/marvell/a3700/common/dram_win.c index e623362e..3ffc98cd 100644 --- a/plat/marvell/a3700/common/dram_win.c +++ b/plat/marvell/a3700/common/dram_win.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses @@ -134,7 +134,8 @@ void dram_win_map_build(struct dram_win_map *win_map) memset(win_map, 0, sizeof(struct dram_win_map)); for (win_id = 0; win_id < DRAM_WIN_MAP_NUM_MAX; win_id++) { ctrl_reg = mmio_read_32(CPU_DEC_WIN_CTRL_REG(win_id)); - target = (ctrl_reg & CPU_DEC_CR_WIN_TARGET_MASK) >> CPU_DEC_CR_WIN_TARGET_OFFS; + target = (ctrl_reg & CPU_DEC_CR_WIN_TARGET_MASK) >> + CPU_DEC_CR_WIN_TARGET_OFFS; enabled = ctrl_reg & CPU_DEC_CR_WIN_ENABLE; /* Ignore invalid and non-dram windows*/ if ((enabled == 0) || (target != DRAM_CPU_DEC_TARGET_NUM)) @@ -144,15 +145,19 @@ void dram_win_map_build(struct dram_win_map *win_map) base_reg = mmio_read_32(CPU_DEC_WIN_BASE_REG(win_id)); size_reg = mmio_read_32(CPU_DEC_WIN_SIZE_REG(win_id)); /* Base reg [15:0] corresponds to transaction address [39:16] */ - win->base_addr = (base_reg & CPU_DEC_BR_BASE_MASK) >> CPU_DEC_BR_BASE_OFFS; + win->base_addr = (base_reg & CPU_DEC_BR_BASE_MASK) >> + CPU_DEC_BR_BASE_OFFS; win->base_addr *= CPU_DEC_CR_WIN_SIZE_ALIGNMENT; /* - * Size reg [15:0] is programmed from LSB to MSB as a sequence of 1s followed by a sequence of 0s, - * and the number of 1s specifies the size of the window in 64 KB granularity, + * Size reg [15:0] is programmed from LSB to MSB as a sequence + * of 1s followed by a sequence of 0s and the number of 1s + * specifies the size of the window in 64 KB granularity, * for example, a value of 00FFh specifies 256 x 64 KB = 16 MB */ - win->win_size = (size_reg & CPU_DEC_CR_WIN_SIZE_MASK) >> CPU_DEC_CR_WIN_SIZE_OFFS; - win->win_size = (win->win_size + 1) * CPU_DEC_CR_WIN_SIZE_ALIGNMENT; + win->win_size = (size_reg & CPU_DEC_CR_WIN_SIZE_MASK) >> + CPU_DEC_CR_WIN_SIZE_OFFS; + win->win_size = (win->win_size + 1) * + CPU_DEC_CR_WIN_SIZE_ALIGNMENT; win_map->dram_win_num++; } @@ -174,13 +179,17 @@ static void cpu_win_set(uint32_t win_id, struct cpu_win_configuration *win_cfg) return; /* Set Base Register */ - base_reg = (uint32_t)(win_cfg->base_addr / CPU_DEC_CR_WIN_SIZE_ALIGNMENT); + base_reg = (uint32_t)(win_cfg->base_addr / + CPU_DEC_CR_WIN_SIZE_ALIGNMENT); base_reg <<= CPU_DEC_BR_BASE_OFFS; base_reg &= CPU_DEC_BR_BASE_MASK; mmio_write_32(CPU_DEC_WIN_BASE_REG(win_id), base_reg); - /* Set Remap Register with the same value as the <Base> field in Base Register */ - remap_reg = (uint32_t)(win_cfg->remap_addr / CPU_DEC_CR_WIN_SIZE_ALIGNMENT); + /* Set Remap Register with the same value + * as the <Base> field in Base Register + */ + remap_reg = (uint32_t)(win_cfg->remap_addr / + CPU_DEC_CR_WIN_SIZE_ALIGNMENT); remap_reg <<= CPU_DEC_RLR_REMAP_LOW_OFFS; remap_reg &= CPU_DEC_RLR_REMAP_LOW_MASK; mmio_write_32(CPU_DEC_REMAP_LOW_REG(win_id), remap_reg); @@ -200,10 +209,12 @@ static void cpu_win_set(uint32_t win_id, struct cpu_win_configuration *win_cfg) void cpu_wins_init(void) { - uint32_t cfg_idx, win_id, cs_id, base_low, base_high, size_mbytes, total_mbytes = 0; + uint32_t cfg_idx, win_id, cs_id; + uint32_t base_low, base_high, size_mbytes, total_mbytes = 0; for (cs_id = 0; cs_id < MVEBU_MAX_CS_MMAP_NUM; cs_id++) - if (!marvell_get_dram_cs_base_size(cs_id, &base_low, &base_high, &size_mbytes)) + if (!marvell_get_dram_cs_base_size(cs_id, &base_low, + &base_high, &size_mbytes)) total_mbytes += size_mbytes; if (total_mbytes <= 2048) @@ -211,7 +222,9 @@ void cpu_wins_init(void) else cfg_idx = CPU_WIN_CONFIG_DRAM_4GB; - /* Window 0 is configured always for DRAM in tim header already, no need to configure it again here */ + /* Window 0 is configured always for DRAM in tim header + * already, no need to configure it again here + */ for (win_id = 1; win_id < MV_CPU_WIN_NUM; win_id++) cpu_win_set(win_id, &mv_cpu_wins[cfg_idx][win_id]); } diff --git a/plat/marvell/a3700/common/include/a3700_dram_cs.h b/plat/marvell/a3700/common/include/a3700_dram_cs.h index 6a9edaf4..4ce64dec 100644 --- a/plat/marvell/a3700/common/include/a3700_dram_cs.h +++ b/plat/marvell/a3700/common/include/a3700_dram_cs.h @@ -1,9 +1,10 @@ /* - * Copyright (C) 2016 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #ifndef __MVEBU_A3700_DRAM_CS_H__ #define __MVEBU_A3700_DRAM_CS_H__ diff --git a/plat/marvell/a3700/common/include/a3700_plat_def.h b/plat/marvell/a3700/common/include/a3700_plat_def.h index 05c71351..e145c532 100644 --- a/plat/marvell/a3700/common/include/a3700_plat_def.h +++ b/plat/marvell/a3700/common/include/a3700_plat_def.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses diff --git a/plat/marvell/a3700/common/include/a3700_pm.h b/plat/marvell/a3700/common/include/a3700_pm.h index 3ab7c736..a3dac274 100644 --- a/plat/marvell/a3700/common/include/a3700_pm.h +++ b/plat/marvell/a3700/common/include/a3700_pm.h @@ -4,6 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #ifndef __MVEBU_A3700_PM_H__ #define __MVEBU_A3700_PM_H__ diff --git a/plat/marvell/a3700/common/include/dram_win.h b/plat/marvell/a3700/common/include/dram_win.h index 8191b298..4537f916 100644 --- a/plat/marvell/a3700/common/include/dram_win.h +++ b/plat/marvell/a3700/common/include/dram_win.h @@ -1,9 +1,10 @@ /* - * Copyright (C) 2016 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #ifndef _DRAM_WIN_H_ #define _DRAM_WIN_H_ diff --git a/plat/marvell/a3700/common/include/io_addr_dec.h b/plat/marvell/a3700/common/include/io_addr_dec.h index d77e9c18..2e4183cd 100644 --- a/plat/marvell/a3700/common/include/io_addr_dec.h +++ b/plat/marvell/a3700/common/include/io_addr_dec.h @@ -1,9 +1,10 @@ /* - * Copyright (C) 2016 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #ifndef _IO_ADDR_DEC_H_ #define _IO_ADDR_DEC_H_ @@ -23,10 +24,15 @@ */ struct dec_win_config { uint32_t dec_reg_base; /* IO address decoder register base address */ - uint32_t win_attr; /* IO address decoder windows attributes */ - uint32_t max_dram_win; /* How many configurable dram decoder windows that this unit has; */ - uint32_t max_remap; /* The decoder windows number including remapping that this unit has */ - uint32_t win_offset; /* The offset between continuous decode windows within the same unit, typically 0x10 */ + uint32_t win_attr; /* IO address decoder windows attributes */ + /* How many configurable dram decoder windows that this unit has; */ + uint32_t max_dram_win; + /* The decoder windows number including remapping that this unit has */ + uint32_t max_remap; + /* The offset between continuous decode windows + * within the same unit, typically 0x10 + */ + uint32_t win_offset; }; struct dram_win { @@ -53,7 +59,9 @@ struct dram_win_map { * * @return: 0 on success and others on failure */ -int init_io_addr_dec(struct dram_win_map *dram_wins_map, struct dec_win_config *io_dec_config, uint32_t io_unit_num); +int init_io_addr_dec(struct dram_win_map *dram_wins_map, + struct dec_win_config *io_dec_config, + uint32_t io_unit_num); #endif /* _IO_ADDR_DEC_H_ */ diff --git a/plat/marvell/a3700/common/include/plat_macros.S b/plat/marvell/a3700/common/include/plat_macros.S index af084882..12f0d6f9 100644 --- a/plat/marvell/a3700/common/include/plat_macros.S +++ b/plat/marvell/a3700/common/include/plat_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses diff --git a/plat/marvell/a3700/common/include/platform_def.h b/plat/marvell/a3700/common/include/platform_def.h index 9e90e0dc..7da1fa14 100644 --- a/plat/marvell/a3700/common/include/platform_def.h +++ b/plat/marvell/a3700/common/include/platform_def.h @@ -8,7 +8,7 @@ #define __PLATFORM_DEF_H__ #include <board_marvell_def.h> -#include <plat_def.h> +#include <mvebu_def.h> #ifndef __ASSEMBLY__ #include <stdio.h> #endif /* __ASSEMBLY__ */ @@ -94,9 +94,9 @@ Trusted SRAM section 0x4000000..0x4200000: #define PLAT_MARVELL_CPU_ENTRY_ADDR BL1_RO_BASE /* GIC related definitions */ -#define PLAT_MARVELL_GICD_BASE (MVEBU_REGS_BASE + MVEBU_GICD_BASE) -#define PLAT_MARVELL_GICR_BASE (MVEBU_REGS_BASE + MVEBU_GICR_BASE) -#define PLAT_MARVELL_GICC_BASE (MVEBU_REGS_BASE + MVEBU_GICC_BASE) +#define PLAT_MARVELL_GICD_BASE (MVEBU_REGS_BASE + MVEBU_GICD_BASE) +#define PLAT_MARVELL_GICR_BASE (MVEBU_REGS_BASE + MVEBU_GICR_BASE) +#define PLAT_MARVELL_GICC_BASE (MVEBU_REGS_BASE + MVEBU_GICC_BASE) #define PLAT_MARVELL_G0_IRQ_PROPS(grp) \ INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ diff --git a/plat/marvell/a3700/common/io_addr_dec.c b/plat/marvell/a3700/common/io_addr_dec.c index e40fac97..c1c404aa 100644 --- a/plat/marvell/a3700/common/io_addr_dec.c +++ b/plat/marvell/a3700/common/io_addr_dec.c @@ -9,9 +9,12 @@ #include <mmio.h> #include <io_addr_dec.h> -#define MVEBU_DEC_WIN_CTRL_REG(base, win, off) (MVEBU_REGS_BASE + base + (win * off)) -#define MVEBU_DEC_WIN_BASE_REG(base, win, off) (MVEBU_REGS_BASE + base + (win * off) + 0x4) -#define MVEBU_DEC_WIN_REMAP_REG(base, win, off) (MVEBU_REGS_BASE + base + (win * off) + 0x8) +#define MVEBU_DEC_WIN_CTRL_REG(base, win, off) (MVEBU_REGS_BASE + base + \ + (win * off)) +#define MVEBU_DEC_WIN_BASE_REG(base, win, off) (MVEBU_REGS_BASE + base + \ + (win * off) + 0x4) +#define MVEBU_DEC_WIN_REMAP_REG(base, win, off) (MVEBU_REGS_BASE + base + \ + (win * off) + 0x8) #define MVEBU_DEC_WIN_CTRL_SIZE_OFF (16) #define MVEBU_DEC_WIN_ENABLE (0x1) @@ -22,65 +25,81 @@ #define MVEBU_WIN_BASE_SIZE_ALIGNMENT (0x10000) -/* There are up to 14 IO unit which need address deocode in Armada-3700 */ +/* There are up to 14 IO unit which need address decode in Armada-3700 */ #define IO_UNIT_NUM_MAX (14) #define MVEBU_MAX_ADDRSS_4GB (0x100000000ULL) -static void set_io_addr_dec_win(int win_id, uintptr_t base_addr, uintptr_t win_size, struct dec_win_config *dec_win) +static void set_io_addr_dec_win(int win_id, uintptr_t base_addr, + uintptr_t win_size, + struct dec_win_config *dec_win) { uint32_t ctrl = 0; uint32_t base = 0; /* set size */ - ctrl = ((win_size / MVEBU_WIN_BASE_SIZE_ALIGNMENT) - 1) << MVEBU_DEC_WIN_CTRL_SIZE_OFF; + ctrl = ((win_size / MVEBU_WIN_BASE_SIZE_ALIGNMENT) - 1) << + MVEBU_DEC_WIN_CTRL_SIZE_OFF; /* set attr according to IO decode window */ ctrl |= dec_win->win_attr << MVEBU_DEC_WIN_CTRL_ATTR_OFF; /* set target */ ctrl |= DRAM_CPU_DEC_TARGET_NUM << MVEBU_DEC_WIN_CTRL_TARGET_OFF; /* set base */ - base = (base_addr / MVEBU_WIN_BASE_SIZE_ALIGNMENT) << MVEBU_DEC_WIN_BASE_OFF; + base = (base_addr / MVEBU_WIN_BASE_SIZE_ALIGNMENT) << + MVEBU_DEC_WIN_BASE_OFF; /* set base address*/ - mmio_write_32(MVEBU_DEC_WIN_BASE_REG(dec_win->dec_reg_base, win_id, dec_win->win_offset), base); + mmio_write_32(MVEBU_DEC_WIN_BASE_REG(dec_win->dec_reg_base, + win_id, dec_win->win_offset), + base); /* set remap window, some unit does not have remap window */ if (win_id < dec_win->max_remap) - mmio_write_32(MVEBU_DEC_WIN_REMAP_REG(dec_win->dec_reg_base, win_id, dec_win->win_offset), base); + mmio_write_32(MVEBU_DEC_WIN_REMAP_REG(dec_win->dec_reg_base, + win_id, dec_win->win_offset), base); /* set control register */ - mmio_write_32(MVEBU_DEC_WIN_CTRL_REG(dec_win->dec_reg_base, win_id, dec_win->win_offset), ctrl); + mmio_write_32(MVEBU_DEC_WIN_CTRL_REG(dec_win->dec_reg_base, + win_id, dec_win->win_offset), ctrl); /* enable the address decode window at last to make it effective */ ctrl |= MVEBU_DEC_WIN_ENABLE << MVEBU_DEC_WIN_CTRL_EN_OFF; - mmio_write_32(MVEBU_DEC_WIN_CTRL_REG(dec_win->dec_reg_base, win_id, dec_win->win_offset), ctrl); + mmio_write_32(MVEBU_DEC_WIN_CTRL_REG(dec_win->dec_reg_base, + win_id, dec_win->win_offset), ctrl); INFO("set_io_addr_dec %d result: ctrl(0x%x) base(0x%x)", - win_id, mmio_read_32(MVEBU_DEC_WIN_CTRL_REG(dec_win->dec_reg_base, win_id, dec_win->win_offset)), - mmio_read_32(MVEBU_DEC_WIN_BASE_REG(dec_win->dec_reg_base, win_id, dec_win->win_offset))); + win_id, mmio_read_32(MVEBU_DEC_WIN_CTRL_REG(dec_win->dec_reg_base, + win_id, dec_win->win_offset)), + mmio_read_32(MVEBU_DEC_WIN_BASE_REG(dec_win->dec_reg_base, + win_id, dec_win->win_offset))); if (win_id < dec_win->max_remap) INFO(" remap(%x)\n", - mmio_read_32(MVEBU_DEC_WIN_REMAP_REG(dec_win->dec_reg_base, win_id, dec_win->win_offset))); + mmio_read_32(MVEBU_DEC_WIN_REMAP_REG(dec_win->dec_reg_base, + win_id, dec_win->win_offset))); else INFO("\n"); } /* Set io decode window */ -static int set_io_addr_dec(struct dram_win_map *win_map, struct dec_win_config *dec_win) +static int set_io_addr_dec(struct dram_win_map *win_map, + struct dec_win_config *dec_win) { struct dram_win *win; int id; /* disable all windows first */ for (id = 0; id < dec_win->max_dram_win; id++) - mmio_write_32(MVEBU_DEC_WIN_CTRL_REG(dec_win->dec_reg_base, id, dec_win->win_offset), 0); + mmio_write_32(MVEBU_DEC_WIN_CTRL_REG(dec_win->dec_reg_base, id, + dec_win->win_offset), 0); - /* configure IO decode windows for DRAM, inheritate DRAM size, base and target from CPU-DRAM - * decode window, and others from hard coded IO decode window settings array. + /* configure IO decode windows for DRAM, inheritate DRAM size, + * base and target from CPU-DRAM decode window and others + * from hard coded IO decode window settings array. */ if (win_map->dram_win_num > dec_win->max_dram_win) { /* - * If cpu dram windows number exceeds the io decode windows max number, - * then fill the first io decode window with base(0) and size(4GB). - */ + * If cpu dram windows number exceeds the io decode windows + * max number, then fill the first io decode window + * with base(0) and size(4GB). + */ set_io_addr_dec_win(0, 0, MVEBU_MAX_ADDRSS_4GB, dec_win); return 0; @@ -108,7 +127,8 @@ static int set_io_addr_dec(struct dram_win_map *win_map, struct dec_win_config * * * @return: 0 on success and others on failure */ -int init_io_addr_dec(struct dram_win_map *dram_wins_map, struct dec_win_config *io_dec_config, uint32_t io_unit_num) +int init_io_addr_dec(struct dram_win_map *dram_wins_map, + struct dec_win_config *io_dec_config, uint32_t io_unit_num) { int32_t index; struct dec_win_config *io_dec_win; @@ -122,7 +142,8 @@ int init_io_addr_dec(struct dram_win_map *dram_wins_map, struct dec_win_config * } if (io_unit_num > IO_UNIT_NUM_MAX) { - ERROR("IO address decoder windows number %d is over max number %d\n", io_unit_num, IO_UNIT_NUM_MAX); + ERROR("IO address decoder windows number %d is over max %d\n", + io_unit_num, IO_UNIT_NUM_MAX); return -1; } @@ -133,7 +154,8 @@ int init_io_addr_dec(struct dram_win_map *dram_wins_map, struct dec_win_config * for (index = 0; index < dram_wins_map->dram_win_num; index++) INFO("DRAM mapping %d base(0x%lx) size(0x%lx)\n", - index, dram_wins_map->dram_windows[index].base_addr, dram_wins_map->dram_windows[index].win_size); + index, dram_wins_map->dram_windows[index].base_addr, + dram_wins_map->dram_windows[index].win_size); /* Set address decode window for each IO */ for (index = 0; index < io_unit_num; index++) { @@ -143,9 +165,11 @@ int init_io_addr_dec(struct dram_win_map *dram_wins_map, struct dec_win_config * ERROR("Failed to set IO address decode\n"); return -1; } - INFO("Set IO decode window successfully, base(0x%x)", io_dec_win->dec_reg_base); + INFO("Set IO decode window successfully, base(0x%x)", + io_dec_win->dec_reg_base); INFO(" win_attr(%x) max_dram_win(%d) max_remap(%d) win_offset(%d)\n", - io_dec_win->win_attr, io_dec_win->max_dram_win, io_dec_win->max_remap, io_dec_win->win_offset); + io_dec_win->win_attr, io_dec_win->max_dram_win, + io_dec_win->max_remap, io_dec_win->win_offset); } return 0; diff --git a/plat/marvell/a3700/common/marvell_plat_config.c b/plat/marvell/a3700/common/marvell_plat_config.c index 8501ad5b..8207658c 100644 --- a/plat/marvell/a3700/common/marvell_plat_config.c +++ b/plat/marvell/a3700/common/marvell_plat_config.c @@ -1,12 +1,12 @@ /* - * Copyright (C) 2016 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -#include <types.h> -#include <plat_def.h> #include <io_addr_dec.h> +#include <mvebu_def.h> +#include <types.h> struct dec_win_config io_dec_win_conf[] = { /* dec_reg_base win_attr max_dram_win max_remap win_offset */ diff --git a/plat/marvell/a3700/common/plat_pm.c b/plat/marvell/a3700/common/plat_pm.c index 06da17e4..13df14a1 100644 --- a/plat/marvell/a3700/common/plat_pm.c +++ b/plat/marvell/a3700/common/plat_pm.c @@ -1,22 +1,23 @@ /* - * Copyright (C) 2016 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + +#include <a3700_pm.h> #include <arch_helpers.h> -#include <plat_marvell.h> -#include <plat_private.h> -#include <plat_def.h> -#include <psci.h> +#include <armada_common.h> #include <debug.h> +#include <dram_win.h> +#include <io_addr_dec.h> #include <mmio.h> #include <mvebu.h> +#include <mvebu_def.h> +#include <marvell_plat_priv.h> #include <platform.h> -#include <a3700_pm.h> -#include <io_addr_dec.h> -#include <plat_config.h> -#include <dram_win.h> +#include <plat_marvell.h> +#include <psci.h> #ifdef USE_CCI #include <cci.h> #endif @@ -39,22 +40,36 @@ /* IRQ register */ #define MVEBU_NB_IRQ_STATUS_1_REG (MVEBU_NB_SB_IRQ_REG_BASE) -#define MVEBU_NB_IRQ_STATUS_2_REG (MVEBU_NB_SB_IRQ_REG_BASE + 0x10) -#define MVEBU_NB_IRQ_MASK_2_REG (MVEBU_NB_SB_IRQ_REG_BASE + 0x18) -#define MVEBU_SB_IRQ_STATUS_1_REG (MVEBU_NB_SB_IRQ_REG_BASE + 0x40) -#define MVEBU_SB_IRQ_STATUS_2_REG (MVEBU_NB_SB_IRQ_REG_BASE + 0x50) -#define MVEBU_NB_GPIO_IRQ_MASK_1_REG (MVEBU_NB_SB_IRQ_REG_BASE + 0xC8) -#define MVEBU_NB_GPIO_IRQ_MASK_2_REG (MVEBU_NB_SB_IRQ_REG_BASE + 0xD8) -#define MVEBU_SB_GPIO_IRQ_MASK_REG (MVEBU_NB_SB_IRQ_REG_BASE + 0xE8) +#define MVEBU_NB_IRQ_STATUS_2_REG (MVEBU_NB_SB_IRQ_REG_BASE + \ + 0x10) +#define MVEBU_NB_IRQ_MASK_2_REG (MVEBU_NB_SB_IRQ_REG_BASE + \ + 0x18) +#define MVEBU_SB_IRQ_STATUS_1_REG (MVEBU_NB_SB_IRQ_REG_BASE + \ + 0x40) +#define MVEBU_SB_IRQ_STATUS_2_REG (MVEBU_NB_SB_IRQ_REG_BASE + \ + 0x50) +#define MVEBU_NB_GPIO_IRQ_MASK_1_REG (MVEBU_NB_SB_IRQ_REG_BASE + \ + 0xC8) +#define MVEBU_NB_GPIO_IRQ_MASK_2_REG (MVEBU_NB_SB_IRQ_REG_BASE + \ + 0xD8) +#define MVEBU_SB_GPIO_IRQ_MASK_REG (MVEBU_NB_SB_IRQ_REG_BASE + \ + 0xE8) #define MVEBU_NB_GPIO_IRQ_EN_LOW_REG (MVEBU_NB_GPIO_IRQ_REG_BASE) -#define MVEBU_NB_GPIO_IRQ_EN_HIGH_REG (MVEBU_NB_GPIO_IRQ_REG_BASE + 0x04) -#define MVEBU_NB_GPIO_IRQ_STATUS_LOW_REG (MVEBU_NB_GPIO_IRQ_REG_BASE + 0x10) -#define MVEBU_NB_GPIO_IRQ_STATUS_HIGH_REG (MVEBU_NB_GPIO_IRQ_REG_BASE + 0x14) -#define MVEBU_NB_GPIO_IRQ_WK_LOW_REG (MVEBU_NB_GPIO_IRQ_REG_BASE + 0x18) -#define MVEBU_NB_GPIO_IRQ_WK_HIGH_REG (MVEBU_NB_GPIO_IRQ_REG_BASE + 0x1C) +#define MVEBU_NB_GPIO_IRQ_EN_HIGH_REG (MVEBU_NB_GPIO_IRQ_REG_BASE + \ + 0x04) +#define MVEBU_NB_GPIO_IRQ_STATUS_LOW_REG (MVEBU_NB_GPIO_IRQ_REG_BASE + \ + 0x10) +#define MVEBU_NB_GPIO_IRQ_STATUS_HIGH_REG (MVEBU_NB_GPIO_IRQ_REG_BASE + \ + 0x14) +#define MVEBU_NB_GPIO_IRQ_WK_LOW_REG (MVEBU_NB_GPIO_IRQ_REG_BASE + \ + 0x18) +#define MVEBU_NB_GPIO_IRQ_WK_HIGH_REG (MVEBU_NB_GPIO_IRQ_REG_BASE + \ + 0x1C) #define MVEBU_SB_GPIO_IRQ_EN_REG (MVEBU_SB_GPIO_IRQ_REG_BASE) -#define MVEBU_SB_GPIO_IRQ_STATUS_REG (MVEBU_SB_GPIO_IRQ_REG_BASE + 0x10) -#define MVEBU_SB_GPIO_IRQ_WK_REG (MVEBU_SB_GPIO_IRQ_REG_BASE + 0x18) +#define MVEBU_SB_GPIO_IRQ_STATUS_REG (MVEBU_SB_GPIO_IRQ_REG_BASE + \ + 0x10) +#define MVEBU_SB_GPIO_IRQ_WK_REG (MVEBU_SB_GPIO_IRQ_REG_BASE + \ + 0x18) /* PMU registers */ #define MVEBU_PM_NB_PWR_CTRL_REG (MVEBU_PMSU_REG_BASE) @@ -177,9 +192,8 @@ struct wake_up_src_func_map { wake_up_src_func func; }; -void psci_arch_init(int die_index) +void marvell_psci_arch_init(int die_index) { - return; } static void a3700_pm_ack_irq(void) @@ -221,7 +235,7 @@ static void a3700_pm_ack_irq(void) ***************************************************************************** */ int a3700_validate_power_state(unsigned int power_state, - psci_power_state_t *req_state) + psci_power_state_t *req_state) { ERROR("a3700_validate_power_state needs to be implemented\n"); panic(); @@ -248,7 +262,8 @@ int a3700_pwr_domain_on(u_register_t mpidr) __asm__ volatile("dsb sy"); /* Set the cpu start address to BL1 entry point */ - mmio_write_32(MVEBU_CPU_1_RESET_VECTOR, PLAT_MARVELL_CPU_ENTRY_ADDR >> 2); + mmio_write_32(MVEBU_CPU_1_RESET_VECTOR, + PLAT_MARVELL_CPU_ENTRY_ADDR >> 2); /* Get the cpu out of reset */ mmio_clrbits_32(MVEBU_CPU_1_RESET_REG, BIT(MVEBU_CPU_1_RESET_BIT)); @@ -282,9 +297,12 @@ void a3700_pwr_domain_off(const psci_power_state_t *target_state) * Enable Core VDD OFF, core is supposed to be powered * off by PMU when WFI command is issued. */ - mmio_setbits_32(MVEBU_PM_CPU_0_PWR_CTRL_REG + 4 * cpu_idx, MVEBU_PM_CORE_PD); + mmio_setbits_32(MVEBU_PM_CPU_0_PWR_CTRL_REG + 4 * cpu_idx, + MVEBU_PM_CORE_PD); - /* Core can not be powered down with pending IRQ, acknowledge all the pending IRQ */ + /* Core can not be powered down with pending IRQ, + * acknowledge all the pending IRQ + */ a3700_pm_ack_irq(); } @@ -294,22 +312,22 @@ static void a3700_set_gen_pwr_off_option(void) mmio_setbits_32(MVEBU_PM_NB_CPU_PWR_CTRL_REG, MVEBU_PM_L2_FLUSH_EN); /* - * North bridge cannot be VDD off (always ON). The NB state machine support low power - * mode by its state machine. - * This bit MUST be set for north bridge power down, e.g., OSC input cutoff(NOT TEST), - * SRAM power down, PMIC, etc. + * North bridge cannot be VDD off (always ON). + * The NB state machine support low power mode by its state machine. + * This bit MUST be set for north bridge power down, e.g., + * OSC input cutoff(NOT TEST), SRAM power down, PMIC, etc. * It is not related to CPU VDD OFF!! */ mmio_clrbits_32(MVEBU_PM_NB_PWR_OPTION_REG, MVEBU_PM_CPU_VDDV_OFF_EN); /* * MUST: Switch CPU/AXI clock to OSC - * NB state machine clock is always connected to OSC (slow clock). But Core0/1/processor - * state machine's clock are connected to AXI clock. Now, AXI clock takes the - * TBG as clock source. - * If using AXI clock, Core0/1/processor state machine may much faster than - * NB state machine. It will cause problem in this case if cores are released - * before north bridge gets ready. + * NB state machine clock is always connected to OSC (slow clock). + * But Core0/1/processor state machine's clock are connected to AXI + * clock. Now, AXI clock takes the TBG as clock source. + * If using AXI clock, Core0/1/processor state machine may much faster + * than NB state machine. It will cause problem in this case if cores + * are released before north bridge gets ready. */ mmio_clrbits_32(MVEBU_NB_CLOCK_SEL_REG, MVEBU_A53_CPU_CLK_SEL); @@ -328,9 +346,10 @@ static void a3700_set_gen_pwr_off_option(void) /* * Idle AXI interface in order to get L2_WFI - * L2 WFI is only asserted after CORE-0 and CORE-1 WFI asserted. (only both core-0/1 - * in WFI, L2 WFI will be issued by CORE.) - * Once L2 WFI asserted, this bit is used for signalling assertion to AXI IO masters. + * L2 WFI is only asserted after CORE-0 and CORE-1 WFI asserted. + * (only both core-0/1in WFI, L2 WFI will be issued by CORE.) + * Once L2 WFI asserted, this bit is used for signalling assertion + * to AXI IO masters. */ mmio_setbits_32(MVEBU_PM_NB_PWR_CTRL_REG, MVEBU_PM_INTERFACE_IDLE); @@ -352,37 +371,47 @@ static void a3700_set_gen_pwr_off_option(void) static void a3700_en_ddr_self_refresh(void) { /* - * Both count is 16 bits and configurable. By default, osc stb cnt is 0xFFF for lower 12 bits. + * Both count is 16 bits and configurable. By default, osc stb cnt + * is 0xFFF for lower 12 bits. * Thus, powerdown count is smaller than osc count. * This count is used for exiting DDR SR mode on wakeup event. * The powerdown count also has impact on the following * state changes: idle -> count-down -> ... (power-down, vdd off, etc) * Here, make stable counter shorter - * Use power down count value instead of osc_stb_cnt to speed up DDR self refresh exit + * Use power down count value instead of osc_stb_cnt to speed up + * DDR self refresh exit */ mmio_setbits_32(MVEBU_PM_NB_PWR_CTRL_REG, MVEBU_PM_PWR_DN_CNT_SEL); /* * Enable DDR SR mode => controlled by north bridge state machine - * Therefore, we must powerdown north bridge to trigger the DDR SR mode switching. + * Therefore, we must powerdown north bridge to trigger the DDR SR + * mode switching. */ mmio_setbits_32(MVEBU_PM_NB_PWR_OPTION_REG, MVEBU_PM_DDR_SR_EN); /* Disable DDR clock, otherwise DDR will not enter into SR mode. */ mmio_setbits_32(MVEBU_PM_NB_PWR_OPTION_REG, MVEBU_PM_DDR_CLK_DIS_EN); /* Power down DDR PHY (PAD) */ mmio_setbits_32(MVEBU_PM_NB_PWR_OPTION_REG, MVEBU_PM_DDRPHY_PWRDWN_EN); - mmio_setbits_32(MVEBU_PM_NB_PWR_OPTION_REG, MVEBU_PM_DDRPHY_PAD_PWRDWN_EN); + mmio_setbits_32(MVEBU_PM_NB_PWR_OPTION_REG, + MVEBU_PM_DDRPHY_PAD_PWRDWN_EN); /* Set wait time for DDR ready in ROM code */ - mmio_write_32(MVEBU_PM_CPU_VDD_OFF_INFO_1_REG, MVEBU_PM_WAIT_DDR_RDY_VALUE); + mmio_write_32(MVEBU_PM_CPU_VDD_OFF_INFO_1_REG, + MVEBU_PM_WAIT_DDR_RDY_VALUE); /* DDR flush write buffer - mandatory */ - mmio_write_32(MVEBU_DRAM_CMD_0_REG, MVEBU_DRAM_CH0_CMD0 | MVEBU_DRAM_CS_CMD0 | MVEBU_DRAM_WCB_DRAIN_REQ); - while ((mmio_read_32(MVEBU_DRAM_STATS_CH0_REG) & MVEBU_DRAM_WCP_EMPTY) != MVEBU_DRAM_WCP_EMPTY) + mmio_write_32(MVEBU_DRAM_CMD_0_REG, MVEBU_DRAM_CH0_CMD0 | + MVEBU_DRAM_CS_CMD0 | MVEBU_DRAM_WCB_DRAIN_REQ); + while ((mmio_read_32(MVEBU_DRAM_STATS_CH0_REG) & + MVEBU_DRAM_WCP_EMPTY) != MVEBU_DRAM_WCP_EMPTY) ; - /* Trigger PHY reset after ddr out of self refresh => supply reset pulse for DDR phy after wake up. */ - mmio_setbits_32(MVEBU_DRAM_PWR_CTRL_REG, MVEBU_DRAM_PHY_CLK_GATING_EN | MVEBU_DRAM_PHY_AUTO_AC_OFF_EN); + /* Trigger PHY reset after ddr out of self refresh => + * supply reset pulse for DDR phy after wake up + */ + mmio_setbits_32(MVEBU_DRAM_PWR_CTRL_REG, MVEBU_DRAM_PHY_CLK_GATING_EN | + MVEBU_DRAM_PHY_AUTO_AC_OFF_EN); } static void a3700_pwr_dn_avs(void) @@ -443,7 +472,9 @@ static void a3700_set_pwr_off_option(void) /* Power down TBG */ a3700_pwr_dn_tbg(); - /* Power down south bridge, pay attention south bridge setting should be done before */ + /* Power down south bridge, pay attention south bridge setting + * should be done before + */ a3700_pwr_dn_sb(); } @@ -456,7 +487,8 @@ static void a3700_set_wake_up_option(void) mmio_setbits_32(MVEBU_PM_NB_WAKE_UP_EN_REG, MVEBU_PM_NB_WKP_EN); /* Enable both core0 and core1 wakeup on demand */ - mmio_setbits_32(MVEBU_PM_CPU_WAKE_UP_CONF_REG, MVEBU_PM_CORE1_WAKEUP | MVEBU_PM_CORE0_WAKEUP); + mmio_setbits_32(MVEBU_PM_CPU_WAKE_UP_CONF_REG, + MVEBU_PM_CORE1_WAKEUP | MVEBU_PM_CORE0_WAKEUP); /* Enable warm reset in low power mode */ mmio_setbits_32(MVEBU_PM_NB_PWR_OPTION_REG, MVEBU_PM_WARM_RESET_EN); @@ -479,21 +511,27 @@ static void a3700_pm_en_nb_gpio(uint32_t gpio) mmio_setbits_32(MVEBU_NB_GPIO_IRQ_EN_LOW_REG, BIT(gpio)); } - mmio_setbits_32(MVEBU_NB_STEP_DOWN_INT_EN_REG, MVEBU_NB_GPIO_INT_WAKE_WCPU_CLK); + mmio_setbits_32(MVEBU_NB_STEP_DOWN_INT_EN_REG, + MVEBU_NB_GPIO_INT_WAKE_WCPU_CLK); - /* Enable using GPIO as wakeup event (actually not only for north bridge) */ + /* Enable using GPIO as wakeup event + * (actually not only for north bridge) + */ mmio_setbits_32(MVEBU_PM_NB_WAKE_UP_EN_REG, MVEBU_PM_NB_GPIO_WKP_EN | - MVEBU_PM_NB_WKP_EN | MVEBU_PM_CORE1_FIQ_IRQ_WKP_EN | MVEBU_PM_CORE0_FIQ_IRQ_WKP_EN); + MVEBU_PM_NB_WKP_EN | MVEBU_PM_CORE1_FIQ_IRQ_WKP_EN | + MVEBU_PM_CORE0_FIQ_IRQ_WKP_EN); } static void a3700_pm_en_sb_gpio(uint32_t gpio) { /* Enable using GPIO as wakeup event */ mmio_setbits_32(MVEBU_PM_NB_WAKE_UP_EN_REG, MVEBU_PM_SB_WKP_NB_EN | - MVEBU_PM_NB_WKP_EN | MVEBU_PM_CORE1_FIQ_IRQ_WKP_EN | MVEBU_PM_CORE0_FIQ_IRQ_WKP_EN); + MVEBU_PM_NB_WKP_EN | MVEBU_PM_CORE1_FIQ_IRQ_WKP_EN | + MVEBU_PM_CORE0_FIQ_IRQ_WKP_EN); /* SB GPIO Wake UP | South Bridge Wake Up Enable */ - mmio_setbits_32(MVEBU_PM_SB_WK_EN_REG, MVEBU_PM_SB_GPIO_WKP_EN | MVEBU_PM_SB_GPIO_WKP_EN); + mmio_setbits_32(MVEBU_PM_SB_WK_EN_REG, MVEBU_PM_SB_GPIO_WKP_EN | + MVEBU_PM_SB_GPIO_WKP_EN); /* GPIO int mask */ mmio_clrbits_32(MVEBU_SB_GPIO_IRQ_MASK_REG, BIT(gpio)); @@ -548,7 +586,8 @@ struct wake_up_src_func_map src_func_table[WAKE_UP_SRC_MAX] = { {WAKE_UP_SRC_TIMER, NULL} }; -static wake_up_src_func a3700_get_wake_up_src_func(enum pm_wake_up_src_type type) +static wake_up_src_func a3700_get_wake_up_src_func( + enum pm_wake_up_src_type type) { uint32_t loop; for (loop = 0; loop < WAKE_UP_SRC_MAX; loop++) { @@ -566,7 +605,8 @@ static void a3700_set_wake_up_source(void) wake_up_src = mv_wake_up_src_config_get(); for (loop = 0; loop < wake_up_src->wake_up_src_num; loop++) { - src_func = a3700_get_wake_up_src_func(wake_up_src->wake_up_src[loop].wake_up_src_type); + src_func = a3700_get_wake_up_src_func( + wake_up_src->wake_up_src[loop].wake_up_src_type); if (src_func) src_func(&(wake_up_src->wake_up_src[loop].wake_up_data)); } @@ -577,19 +617,22 @@ static void a3700_set_wake_up_source(void) static void a3700_pm_save_lp_flag(void) { /* Save the flag for enter the low power mode */ - mmio_setbits_32(MVEBU_PM_CPU_VDD_OFF_INFO_2_REG, MVEBU_PM_LOW_POWER_STATE); + mmio_setbits_32(MVEBU_PM_CPU_VDD_OFF_INFO_2_REG, + MVEBU_PM_LOW_POWER_STATE); } static void a3700_pm_clear_lp_flag(void) { /* Clear the flag for enter the low power mode */ - mmio_clrbits_32(MVEBU_PM_CPU_VDD_OFF_INFO_2_REG, MVEBU_PM_LOW_POWER_STATE); + mmio_clrbits_32(MVEBU_PM_CPU_VDD_OFF_INFO_2_REG, + MVEBU_PM_LOW_POWER_STATE); } static uint32_t a3700_pm_get_lp_flag(void) { /* Get the flag for enter the low power mode */ - return mmio_read_32(MVEBU_PM_CPU_VDD_OFF_INFO_2_REG) & MVEBU_PM_LOW_POWER_STATE; + return mmio_read_32(MVEBU_PM_CPU_VDD_OFF_INFO_2_REG) & + MVEBU_PM_LOW_POWER_STATE; } /***************************************************************************** @@ -634,7 +677,7 @@ void a3700_pwr_domain_suspend(const psci_power_state_t *target_state) void a3700_pwr_domain_on_finish(const psci_power_state_t *target_state) { /* arch specific configuration */ - psci_arch_init(0); + marvell_psci_arch_init(0); /* Per-CPU interrupt initialization */ plat_marvell_gic_pcpu_init(); @@ -660,7 +703,7 @@ void a3700_pwr_domain_suspend_finish(const psci_power_state_t *target_state) struct dram_win_map dram_wins_map; /* arch specific configuration */ - psci_arch_init(0); + marvell_psci_arch_init(0); /* Interrupt initialization */ plat_marvell_gic_init(); @@ -726,9 +769,6 @@ static void __dead2 a3700_system_off(void) { ERROR("a3700_system_off needs to be implemented\n"); panic(); - wfi(); - ERROR("A3700 System Off: operation not handled.\n"); - panic(); } /***************************************************************************** @@ -744,7 +784,8 @@ static void __dead2 a3700_system_reset(void) /* Flush data cache if the mail box shared RAM is cached */ #if PLAT_MARVELL_SHARED_RAM_CACHED - flush_dcache_range((uintptr_t)PLAT_MARVELL_MAILBOX_BASE, 2 * sizeof(uint64_t)); + flush_dcache_range((uintptr_t)PLAT_MARVELL_MAILBOX_BASE, + 2 * sizeof(uint64_t)); #endif /* Trigger the warm reset */ |