diff options
Diffstat (limited to 'plat/marvell/a8k/a80x0/board/marvell_plat_config.c')
| -rw-r--r-- | plat/marvell/a8k/a80x0/board/marvell_plat_config.c | 33 |
1 files changed, 19 insertions, 14 deletions
diff --git a/plat/marvell/a8k/a80x0/board/marvell_plat_config.c b/plat/marvell/a8k/a80x0/board/marvell_plat_config.c index 65684434..836c9b40 100644 --- a/plat/marvell/a8k/a80x0/board/marvell_plat_config.c +++ b/plat/marvell/a8k/a80x0/board/marvell_plat_config.c @@ -1,16 +1,17 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -#include <plat_config.h> +#include <armada_common.h> + /* * If bootrom is currently at BLE there's no need to include the memory * maps structure at this point */ -#include <plat_def.h> +#include <mvebu_def.h> #ifndef IMAGE_BLE /***************************************************************************** @@ -22,13 +23,14 @@ struct addr_map_win amb_memory_map[] = { {0xf900, 0x1000000, AMB_SPI1_CS0_ID}, }; -int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { *win = amb_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(amb_memory_map)/sizeof(amb_memory_map[0]); + *size = ARRAY_SIZE(amb_memory_map); return 0; } @@ -60,13 +62,14 @@ uint32_t marvell_get_io_win_gcr_target(int ap_index) return PIDI_TID; } -int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = io_win_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(io_win_memory_map)/sizeof(io_win_memory_map[0]); + *size = ARRAY_SIZE(io_win_memory_map); return 0; } @@ -100,16 +103,17 @@ struct addr_map_win iob_memory_map_cp1[] = { {0x00000000fa000000, 0x1000000, PEX0_TID} }; -int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { switch (base) { case MVEBU_CP_REGS_BASE(0): *win = iob_memory_map_cp0; - *size = sizeof(iob_memory_map_cp0)/sizeof(iob_memory_map_cp0[0]); + *size = ARRAY_SIZE(iob_memory_map_cp0); return 0; case MVEBU_CP_REGS_BASE(1): *win = iob_memory_map_cp1; - *size = sizeof(iob_memory_map_cp1)/sizeof(iob_memory_map_cp1[0]); + *size = ARRAY_SIZE(iob_memory_map_cp1); return 0; default: *size = 0; @@ -138,10 +142,11 @@ uint32_t marvell_get_ccu_gcr_target(int ap) return DRAM_0_TID; } -int marvell_get_ccu_memory_map(int ap, struct addr_map_win **win, uint32_t *size) +int marvell_get_ccu_memory_map(int ap, struct addr_map_win **win, + uint32_t *size) { *win = ccu_memory_map; - *size = sizeof(ccu_memory_map)/sizeof(ccu_memory_map[0]); + *size = ARRAY_SIZE(ccu_memory_map); return 0; } @@ -161,7 +166,7 @@ struct power_off_method pm_cfg = { .cfg.gpio.delay_ms = 10, }; -void *plat_get_pm_cfg(void) +void *plat_marvell_get_pm_cfg(void) { /* Return the PM configurations */ return &pm_cfg; @@ -182,7 +187,7 @@ struct skip_image skip_im = { .info.test.cp_index = 0, }; -void *plat_get_skip_image_data(void) +void *plat_marvell_get_skip_image_data(void) { /* Return the skip_image configurations */ return &skip_im; |