diff options
Diffstat (limited to 'plat/marvell/a8k')
56 files changed, 512 insertions, 394 deletions
diff --git a/plat/marvell/a8k/a3900/board/dram_port.c b/plat/marvell/a8k/a3900/board/dram_port.c index ba25e55b..9622fce6 100644 --- a/plat/marvell/a8k/a3900/board/dram_port.c +++ b/plat/marvell/a8k/a3900/board/dram_port.c @@ -15,7 +15,7 @@ * based on information recieved from SPD or bootloader * configuration located on non volatile storage */ -void plat_dram_update_topology(void) +void plat_marvell_dram_update_topology(void) { NOTICE("Gathering DRAM information\n"); } @@ -53,9 +53,9 @@ struct mv_ddr_iface dram_iface_ap0 = { MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ { {0} }, /* raw spd data */ {0}, /* timing parameters */ - { /* electrical configuration */ - { /* memory electrical configuration */ - MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */ + { /* electrical configuration */ + { /* memory electrical configuration */ + MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */ { MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ @@ -66,7 +66,7 @@ struct mv_ddr_iface dram_iface_ap0 = { }, MV_DDR_DIC_RZQ_DIV7 /* dic */ }, - { /* phy electrical configuration */ + { /* phy electrical configuration */ MV_DDR_OHM_30, /* data_drv_p */ MV_DDR_OHM_30, /* data_drv_n */ MV_DDR_OHM_30, /* ctrl_drv_p */ @@ -80,7 +80,7 @@ struct mv_ddr_iface dram_iface_ap0 = { MV_DDR_OHM_120 /* odt_n 2cs */ }, }, - { /* mac electrical configuration */ + { /* mac electrical configuration */ MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */ MV_DDR_ODT_CFG_NORMAL /* odtcfg_read */ diff --git a/plat/marvell/a8k/a3900/board/marvell_plat_config.c b/plat/marvell/a8k/a3900/board/marvell_plat_config.c index 9d1681f0..7b91e50c 100644 --- a/plat/marvell/a8k/a3900/board/marvell_plat_config.c +++ b/plat/marvell/a8k/a3900/board/marvell_plat_config.c @@ -5,12 +5,13 @@ * https://spdx.org/licenses */ -#include <plat_config.h> +#include <armada_common.h> +#include <mvebu_def.h> + /* * If bootrom is currently at BLE there's no need to include the memory * maps structure at this point */ -#include <plat_def.h> #ifndef IMAGE_BLE /***************************************************************************** @@ -19,13 +20,14 @@ */ struct addr_map_win *amb_memory_map; -int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { *win = amb_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(amb_memory_map)/sizeof(amb_memory_map[0]); + *size = ARRAY_SIZE(amb_memory_map); return 0; } @@ -53,13 +55,14 @@ uint32_t marvell_get_io_win_gcr_target(int ap_index) return PIDI_TID; } -int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = io_win_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(io_win_memory_map)/sizeof(io_win_memory_map[0]); + *size = ARRAY_SIZE(io_win_memory_map); return 0; } @@ -77,10 +80,11 @@ struct addr_map_win iob_memory_map[] = { {0x00000000c0000000, 0x30000000, PEX0_TID}, }; -int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { *win = iob_memory_map; - *size = sizeof(iob_memory_map)/sizeof(iob_memory_map[0]); + *size = ARRAY_SIZE(iob_memory_map); return 0; } @@ -104,10 +108,11 @@ uint32_t marvell_get_ccu_gcr_target(int ap) return DRAM_0_TID; } -int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = ccu_memory_map; - *size = sizeof(ccu_memory_map)/sizeof(ccu_memory_map[0]); + *size = ARRAY_SIZE(ccu_memory_map); return 0; } diff --git a/plat/marvell/a8k/a3900/plat_def.h b/plat/marvell/a8k/a3900/mvebu_def.h index 075ea9da..075ea9da 100644 --- a/plat/marvell/a8k/a3900/plat_def.h +++ b/plat/marvell/a8k/a3900/mvebu_def.h diff --git a/plat/marvell/a8k/a3900_z1/board/dram_port.c b/plat/marvell/a8k/a3900_z1/board/dram_port.c index 4acff01d..cd8669eb 100644 --- a/plat/marvell/a8k/a3900_z1/board/dram_port.c +++ b/plat/marvell/a8k/a3900_z1/board/dram_port.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses @@ -14,9 +14,8 @@ * based on information received from SPD or bootloader * configuration located on non volatile storage */ -void plat_dram_update_topology(void) +void plat_marvell_dram_update_topology(void) { - NOTICE("Gathering DRAM information\n"); } /* @@ -47,12 +46,12 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ { {0} }, /* raw spd data */ {0}, /* timing parameters */ - { /* electrical configuration */ - { /* memory electrical configuration */ + { /* electrical configuration */ + { /* memory electrical configuration */ MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */ { - MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ - MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ }, { MV_DDR_RTT_WR_DYN_ODT_OFF, /* rtt_wr 1cs */ @@ -60,7 +59,7 @@ static struct mv_ddr_topology_map board_topology_map = { }, MV_DDR_DIC_RZQ_DIV7 /* dic */ }, - { /* phy electrical configuration */ + { /* phy electrical configuration */ MV_DDR_OHM_30, /* data_drv_p */ MV_DDR_OHM_30, /* data_drv_n */ MV_DDR_OHM_30, /* ctrl_drv_p */ @@ -74,10 +73,10 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_OHM_120 /* odt_n 2cs */ }, }, - { /* mac electrical configuration */ - MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ + { /* mac electrical configuration */ + MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */ - MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ + MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ }, } }; diff --git a/plat/marvell/a8k/a3900_z1/board/marvell_plat_config.c b/plat/marvell/a8k/a3900_z1/board/marvell_plat_config.c index 708bca16..f1968c4e 100644 --- a/plat/marvell/a8k/a3900_z1/board/marvell_plat_config.c +++ b/plat/marvell/a8k/a3900_z1/board/marvell_plat_config.c @@ -1,15 +1,17 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -#include <plat_config.h> + +#include <armada_common.h> +#include <mvebu_def.h> + /* * If bootrom is currently at BLE there's no need to include the memory * maps structure at this point */ -#include <plat_def.h> #ifndef IMAGE_BLE /***************************************************************************** @@ -18,13 +20,14 @@ */ struct addr_map_win *amb_memory_map; -int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { *win = amb_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(amb_memory_map)/sizeof(amb_memory_map[0]); + *size = ARRAY_SIZE(amb_memory_map); return 0; } @@ -52,13 +55,14 @@ uint32_t marvell_get_io_win_gcr_target(int ap_index) return PIDI_TID; } -int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = io_win_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(io_win_memory_map)/sizeof(io_win_memory_map[0]); + *size = ARRAY_SIZE(io_win_memory_map); return 0; } @@ -76,10 +80,11 @@ struct addr_map_win iob_memory_map[] = { {0x00000000c0000000, 0x30000000, PEX0_TID}, }; -int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { *win = iob_memory_map; - *size = sizeof(iob_memory_map)/sizeof(iob_memory_map[0]); + *size = ARRAY_SIZE(iob_memory_map); return 0; } @@ -103,10 +108,11 @@ uint32_t marvell_get_ccu_gcr_target(int ap) return DRAM_0_TID; } -int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = ccu_memory_map; - *size = sizeof(ccu_memory_map)/sizeof(ccu_memory_map[0]); + *size = ARRAY_SIZE(ccu_memory_map); return 0; } diff --git a/plat/marvell/a8k/a3900_z1/plat_def.h b/plat/marvell/a8k/a3900_z1/mvebu_def.h index ea74303d..713ce55f 100644 --- a/plat/marvell/a8k/a3900_z1/plat_def.h +++ b/plat/marvell/a8k/a3900_z1/mvebu_def.h @@ -1,9 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #ifndef __MVEBU_DEF_H__ #define __MVEBU_DEF_H__ diff --git a/plat/marvell/a8k/a3900_z1/platform.mk b/plat/marvell/a8k/a3900_z1/platform.mk index 173a44ee..d3a01676 100644 --- a/plat/marvell/a8k/a3900_z1/platform.mk +++ b/plat/marvell/a8k/a3900_z1/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (C) 2016 - 2018 Marvell International Ltd. +# Copyright (C) 2018 Marvell International Ltd. # # SPDX-License-Identifier: BSD-3-Clause # https://spdx.org/licenses diff --git a/plat/marvell/a8k/a70x0/board/dram_port.c b/plat/marvell/a8k/a70x0/board/dram_port.c index b871a29e..c6702589 100644 --- a/plat/marvell/a8k/a70x0/board/dram_port.c +++ b/plat/marvell/a8k/a70x0/board/dram_port.c @@ -1,9 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #include <arch_helpers.h> #include <debug.h> #include <mv_ddr_if.h> @@ -11,12 +12,11 @@ /* * This function may modify the default DRAM parameters - * based on information recieved from SPD or bootloader + * based on information received from SPD or bootloader * configuration located on non volatile storage */ -void plat_dram_update_topology(void) +void plat_marvell_dram_update_topology(void) { - INFO("Gathering DRAM information\n"); } /* @@ -47,12 +47,12 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ { {0} }, /* raw spd data */ {0}, /* timing parameters */ - { /* electrical configuration */ - { /* memory electrical configuration */ + { /* electrical configuration */ + { /* memory electrical configuration */ MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */ { - MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ - MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ }, { MV_DDR_RTT_WR_DYN_ODT_OFF, /* rtt_wr 1cs */ @@ -60,7 +60,7 @@ static struct mv_ddr_topology_map board_topology_map = { }, MV_DDR_DIC_RZQ_DIV7 /* dic */ }, - { /* phy electrical configuration */ + { /* phy electrical configuration */ MV_DDR_OHM_30, /* data_drv_p */ MV_DDR_OHM_30, /* data_drv_n */ MV_DDR_OHM_30, /* ctrl_drv_p */ @@ -74,10 +74,10 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_OHM_120 /* odt_n 2cs */ }, }, - { /* mac electrical configuration */ - MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ + { /* mac electrical configuration */ + MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */ - MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ + MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ }, } }; diff --git a/plat/marvell/a8k/a70x0/board/marvell_plat_config.c b/plat/marvell/a8k/a70x0/board/marvell_plat_config.c index 6d904fec..d126f556 100644 --- a/plat/marvell/a8k/a70x0/board/marvell_plat_config.c +++ b/plat/marvell/a8k/a70x0/board/marvell_plat_config.c @@ -1,15 +1,17 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -#include <plat_config.h> + +#include <armada_common.h> + /* * If bootrom is currently at BLE there's no need to include the memory * maps structure at this point */ -#include <plat_def.h> +#include <mvebu_def.h> #ifndef IMAGE_BLE /***************************************************************************** @@ -21,13 +23,14 @@ struct addr_map_win amb_memory_map[] = { {0xf900, 0x1000000, AMB_SPI1_CS0_ID}, }; -int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_amb_memory_map(struct addr_map_win **win, + uint32_t *size, uintptr_t base) { *win = amb_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(amb_memory_map)/sizeof(amb_memory_map[0]); + *size = ARRAY_SIZE(amb_memory_map); return 0; } @@ -51,13 +54,14 @@ uint32_t marvell_get_io_win_gcr_target(int ap_index) return PIDI_TID; } -int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = io_win_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(io_win_memory_map)/sizeof(io_win_memory_map[0]); + *size = ARRAY_SIZE(io_win_memory_map); return 0; } @@ -80,10 +84,11 @@ struct addr_map_win iob_memory_map[] = { {0x00000000f9000000, 0x1000000, RUNIT_TID}, }; -int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { *win = iob_memory_map; - *size = sizeof(iob_memory_map)/sizeof(iob_memory_map[0]); + *size = ARRAY_SIZE(iob_memory_map); return 0; } @@ -108,10 +113,11 @@ uint32_t marvell_get_ccu_gcr_target(int ap) return DRAM_0_TID; } -int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = ccu_memory_map; - *size = sizeof(ccu_memory_map)/sizeof(ccu_memory_map[0]); + *size = ARRAY_SIZE(ccu_memory_map); return 0; } @@ -130,7 +136,7 @@ struct skip_image skip_im = { .info.test.cp_index = 0, }; -void *plat_get_skip_image_data(void) +void *plat_marvell_get_skip_image_data(void) { /* Return the skip_image configurations */ return &skip_im; diff --git a/plat/marvell/a8k/a70x0/plat_def.h b/plat/marvell/a8k/a70x0/mvebu_def.h index 129d9332..a7c5abbb 100644 --- a/plat/marvell/a8k/a70x0/plat_def.h +++ b/plat/marvell/a8k/a70x0/mvebu_def.h @@ -1,10 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ - + #ifndef __MVEBU_DEF_H__ #define __MVEBU_DEF_H__ diff --git a/plat/marvell/a8k/a70x0/platform.mk b/plat/marvell/a8k/a70x0/platform.mk index 173a44ee..d3a01676 100644 --- a/plat/marvell/a8k/a70x0/platform.mk +++ b/plat/marvell/a8k/a70x0/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (C) 2016 - 2018 Marvell International Ltd. +# Copyright (C) 2018 Marvell International Ltd. # # SPDX-License-Identifier: BSD-3-Clause # https://spdx.org/licenses diff --git a/plat/marvell/a8k/a70x0_amc/board/dram_port.c b/plat/marvell/a8k/a70x0_amc/board/dram_port.c index 8481fa7e..ab1df465 100644 --- a/plat/marvell/a8k/a70x0_amc/board/dram_port.c +++ b/plat/marvell/a8k/a70x0_amc/board/dram_port.c @@ -1,9 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #include <arch_helpers.h> #include <debug.h> #include <mv_ddr_if.h> @@ -14,9 +15,8 @@ * based on information received from SPD or bootloader * configuration located on non volatile storage */ -void plat_dram_update_topology(void) +void plat_marvell_dram_update_topology(void) { - INFO("Gathering DRAM information\n"); } /* @@ -47,12 +47,12 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ { {0} }, /* raw spd data */ {0}, /* timing parameters */ - { /* electrical configuration */ - { /* memory electrical configuration */ + { /* electrical configuration */ + { /* memory electrical configuration */ MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */ { - MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ - MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ }, { MV_DDR_RTT_WR_DYN_ODT_OFF, /* rtt_wr 1cs */ @@ -60,7 +60,7 @@ static struct mv_ddr_topology_map board_topology_map = { }, MV_DDR_DIC_RZQ_DIV7 /* dic */ }, - { /* phy electrical configuration */ + { /* phy electrical configuration */ MV_DDR_OHM_30, /* data_drv_p */ MV_DDR_OHM_30, /* data_drv_n */ MV_DDR_OHM_30, /* ctrl_drv_p */ @@ -74,10 +74,10 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_OHM_120 /* odt_n 2cs */ }, }, - { /* mac electrical configuration */ - MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ + { /* mac electrical configuration */ + MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */ - MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ + MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ }, } }; diff --git a/plat/marvell/a8k/a70x0_amc/board/marvell_plat_config.c b/plat/marvell/a8k/a70x0_amc/board/marvell_plat_config.c index d3bcee60..f8a1c40b 100644 --- a/plat/marvell/a8k/a70x0_amc/board/marvell_plat_config.c +++ b/plat/marvell/a8k/a70x0_amc/board/marvell_plat_config.c @@ -1,15 +1,17 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -#include <plat_config.h> + +#include <armada_common.h> + /* * If bootrom is currently at BLE there's no need to include the memory * maps structure at this point */ -#include <plat_def.h> +#include <mvebu_def.h> #ifndef IMAGE_BLE /***************************************************************************** @@ -18,13 +20,14 @@ */ struct addr_map_win *amb_memory_map; -int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { *win = amb_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(amb_memory_map)/sizeof(amb_memory_map[0]); + *size = ARRAY_SIZE(amb_memory_map); return 0; } @@ -48,13 +51,14 @@ uint32_t marvell_get_io_win_gcr_target(int ap_index) return PIDI_TID; } -int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = io_win_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(io_win_memory_map)/sizeof(io_win_memory_map[0]); + *size = ARRAY_SIZE(io_win_memory_map); return 0; } @@ -71,10 +75,11 @@ struct addr_map_win iob_memory_map[] = { {0x0000000800000000, 0x200000000, PEX0_TID}, }; -int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { *win = iob_memory_map; - *size = sizeof(iob_memory_map)/sizeof(iob_memory_map[0]); + *size = ARRAY_SIZE(iob_memory_map); return 0; } @@ -99,10 +104,11 @@ uint32_t marvell_get_ccu_gcr_target(int ap) return DRAM_0_TID; } -int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = ccu_memory_map; - *size = sizeof(ccu_memory_map)/sizeof(ccu_memory_map[0]); + *size = ARRAY_SIZE(ccu_memory_map); return 0; } @@ -127,7 +133,7 @@ struct skip_image skip_im = { .info.test.cp_index = 0, }; -void *plat_get_skip_image_data(void) +void *plat_marvell_get_skip_image_data(void) { /* Return the skip_image configurations */ return &skip_im; diff --git a/plat/marvell/a8k/a70x0_amc/plat_def.h b/plat/marvell/a8k/a70x0_amc/mvebu_def.h index e8bbc154..5c665528 100644 --- a/plat/marvell/a8k/a70x0_amc/plat_def.h +++ b/plat/marvell/a8k/a70x0_amc/mvebu_def.h @@ -1,9 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #ifndef __MVEBU_DEF_H__ #define __MVEBU_DEF_H__ @@ -13,7 +14,7 @@ /*********************************************************************** * Required platform porting definitions common to all - * Mangement Compute SubSystems (MSS) + * Management Compute SubSystems (MSS) *********************************************************************** */ /* @@ -23,7 +24,7 @@ * it is discarded and BL31 is loaded over the top. */ #ifdef SCP_IMAGE -#define SCP_BL2_BASE BL31_BASE +#define SCP_BL2_BASE BL31_BASE #endif diff --git a/plat/marvell/a8k/a70x0_amc/platform.mk b/plat/marvell/a8k/a70x0_amc/platform.mk index 173a44ee..d3a01676 100644 --- a/plat/marvell/a8k/a70x0_amc/platform.mk +++ b/plat/marvell/a8k/a70x0_amc/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (C) 2016 - 2018 Marvell International Ltd. +# Copyright (C) 2018 Marvell International Ltd. # # SPDX-License-Identifier: BSD-3-Clause # https://spdx.org/licenses diff --git a/plat/marvell/a8k/a70x0_cust/board/dram_port.c b/plat/marvell/a8k/a70x0_cust/board/dram_port.c index fdcb0bfc..1acf742e 100644 --- a/plat/marvell/a8k/a70x0_cust/board/dram_port.c +++ b/plat/marvell/a8k/a70x0_cust/board/dram_port.c @@ -1,15 +1,16 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #include <arch_helpers.h> #include <a8k_i2c.h> #include <debug.h> #include <mmio.h> #include <mv_ddr_if.h> -#include <plat_def.h> +#include <mvebu_def.h> #include <plat_marvell.h> /* @@ -40,12 +41,12 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ { {0} }, /* raw spd data */ {0}, /* timing parameters */ - { /* electrical configuration */ - { /* memory electrical configuration */ + { /* electrical configuration */ + { /* memory electrical configuration */ MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */ { - MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ - MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ }, { MV_DDR_RTT_WR_DYN_ODT_OFF, /* rtt_wr 1cs */ @@ -53,7 +54,7 @@ static struct mv_ddr_topology_map board_topology_map = { }, MV_DDR_DIC_RZQ_DIV7 /* dic */ }, - { /* phy electrical configuration */ + { /* phy electrical configuration */ MV_DDR_OHM_30, /* data_drv_p */ MV_DDR_OHM_30, /* data_drv_n */ MV_DDR_OHM_30, /* ctrl_drv_p */ @@ -67,10 +68,10 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_OHM_120 /* odt_n 2cs */ }, }, - { /* mac electrical configuration */ - MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ + { /* mac electrical configuration */ + MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */ - MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ + MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ }, } }; @@ -95,7 +96,7 @@ static void mpp_config(void) * based on information received from SPD or bootloader * configuration located on non volatile storage */ -void plat_dram_update_topology(void) +void plat_marvell_dram_update_topology(void) { struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); diff --git a/plat/marvell/a8k/a70x0_cust/board/marvell_plat_config.c b/plat/marvell/a8k/a70x0_cust/board/marvell_plat_config.c index 9c7d6c20..ea133b6f 100644 --- a/plat/marvell/a8k/a70x0_cust/board/marvell_plat_config.c +++ b/plat/marvell/a8k/a70x0_cust/board/marvell_plat_config.c @@ -1,15 +1,17 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -#include <plat_config.h> + +#include <armada_common.h> +#include <mvebu_def.h> + /* * If bootrom is currently at BLE there's no need to include the memory * maps structure at this point */ -#include <plat_def.h> #ifndef IMAGE_BLE /***************************************************************************** @@ -20,13 +22,14 @@ struct addr_map_win amb_memory_map[] = { {0xf900, 0x1000000, AMB_DEV_CS0_ID}, /* Device Bus window */ }; -int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_amb_memory_map(struct addr_map_win **win, + uint32_t *size, uintptr_t base) { *win = amb_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(amb_memory_map)/sizeof(amb_memory_map[0]); + *size = ARRAY_SIZE(amb_memory_map); return 0; } @@ -50,13 +53,14 @@ uint32_t marvell_get_io_win_gcr_target(int ap_index) return PIDI_TID; } -int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = io_win_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(io_win_memory_map)/sizeof(io_win_memory_map[0]); + *size = ARRAY_SIZE(io_win_memory_map); return 0; } @@ -75,10 +79,11 @@ struct addr_map_win iob_memory_map[] = { {0x00000000f6000000, 0x1000000, PEX0_TID}, }; -int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { *win = iob_memory_map; - *size = sizeof(iob_memory_map)/sizeof(iob_memory_map[0]); + *size = ARRAY_SIZE(iob_memory_map); return 0; } @@ -101,10 +106,11 @@ uint32_t marvell_get_ccu_gcr_target(int ap) return DRAM_0_TID; } -int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = ccu_memory_map; - *size = sizeof(ccu_memory_map)/sizeof(ccu_memory_map[0]); + *size = ARRAY_SIZE(ccu_memory_map); return 0; } diff --git a/plat/marvell/a8k/a70x0_cust/plat_def.h b/plat/marvell/a8k/a70x0_cust/mvebu_def.h index 419ae84e..026bc61b 100644 --- a/plat/marvell/a8k/a70x0_cust/plat_def.h +++ b/plat/marvell/a8k/a70x0_cust/mvebu_def.h @@ -1,9 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #ifndef __MVEBU_DEF_H__ #define __MVEBU_DEF_H__ diff --git a/plat/marvell/a8k/a70x0_cust/platform.mk b/plat/marvell/a8k/a70x0_cust/platform.mk index 173a44ee..d3a01676 100644 --- a/plat/marvell/a8k/a70x0_cust/platform.mk +++ b/plat/marvell/a8k/a70x0_cust/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (C) 2016 - 2018 Marvell International Ltd. +# Copyright (C) 2018 Marvell International Ltd. # # SPDX-License-Identifier: BSD-3-Clause # https://spdx.org/licenses diff --git a/plat/marvell/a8k/a70x0_pcac/board/dram_port.c b/plat/marvell/a8k/a70x0_pcac/board/dram_port.c index 44488372..fccc532f 100644 --- a/plat/marvell/a8k/a70x0_pcac/board/dram_port.c +++ b/plat/marvell/a8k/a70x0_pcac/board/dram_port.c @@ -1,9 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #include <arch_helpers.h> #include <debug.h> #include <mv_ddr_if.h> @@ -14,9 +15,8 @@ * based on information received from SPD or bootloader * configuration located on non volatile storage */ -void plat_dram_update_topology(void) +void plat_marvell_dram_update_topology(void) { - INFO("Gathering DRAM information\n"); } /* @@ -47,12 +47,12 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ { {0} }, /* raw spd data */ {0}, /* timing parameters */ - { /* electrical configuration */ - { /* memory electrical configuration */ + { /* electrical configuration */ + { /* memory electrical configuration */ MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */ { - MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ - MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ }, { MV_DDR_RTT_WR_DYN_ODT_OFF, /* rtt_wr 1cs */ @@ -60,7 +60,7 @@ static struct mv_ddr_topology_map board_topology_map = { }, MV_DDR_DIC_RZQ_DIV7 /* dic */ }, - { /* phy electrical configuration */ + { /* phy electrical configuration */ MV_DDR_OHM_30, /* data_drv_p */ MV_DDR_OHM_30, /* data_drv_n */ MV_DDR_OHM_30, /* ctrl_drv_p */ @@ -74,7 +74,7 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_OHM_120 /* odt_n 2cs */ }, }, - { /* mac electrical configuration */ + { /* mac electrical configuration */ MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */ MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ diff --git a/plat/marvell/a8k/a70x0_pcac/board/marvell_plat_config.c b/plat/marvell/a8k/a70x0_pcac/board/marvell_plat_config.c index 0b7996a9..aa13c38f 100644 --- a/plat/marvell/a8k/a70x0_pcac/board/marvell_plat_config.c +++ b/plat/marvell/a8k/a70x0_pcac/board/marvell_plat_config.c @@ -1,16 +1,18 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -#include <plat_config.h> +#include <armada_common.h> +#include <mvebu_def.h> +#include <pci_ep.h> + /* * If bootrom is currently at BLE there's no need to include the memory * maps structure at this point */ -#include <plat_def.h> #ifndef IMAGE_BLE /***************************************************************************** @@ -19,7 +21,8 @@ */ struct addr_map_win *amb_memory_map; -int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { *win = amb_memory_map; if (*win == NULL) @@ -49,7 +52,8 @@ uint32_t marvell_get_io_win_gcr_target(int ap_index) return PIDI_TID; } -int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = io_win_memory_map; if (*win == NULL) @@ -74,7 +78,8 @@ struct addr_map_win iob_memory_map[] = { {0x0000008000000000, 0x80000000000, PEX0_TID}, }; -int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { *win = iob_memory_map; *size = sizeof(iob_memory_map)/sizeof(iob_memory_map[0]); @@ -101,7 +106,8 @@ uint32_t marvell_get_ccu_gcr_target(int ap) return DRAM_0_TID; } -int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = ccu_memory_map; *size = sizeof(ccu_memory_map)/sizeof(ccu_memory_map[0]); diff --git a/plat/marvell/a8k/a70x0_pcac/plat_def.h b/plat/marvell/a8k/a70x0_pcac/mvebu_def.h index 5f227133..cd0cdc15 100644 --- a/plat/marvell/a8k/a70x0_pcac/plat_def.h +++ b/plat/marvell/a8k/a70x0_pcac/mvebu_def.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses diff --git a/plat/marvell/a8k/a70x0_pcac/platform.mk b/plat/marvell/a8k/a70x0_pcac/platform.mk index bc8c878f..c7d44f19 100644 --- a/plat/marvell/a8k/a70x0_pcac/platform.mk +++ b/plat/marvell/a8k/a70x0_pcac/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (C) 2016 - 2018 Marvell International Ltd. +# Copyright (C) 2018 Marvell International Ltd. # # SPDX-License-Identifier: BSD-3-Clause # https://spdx.org/licenses diff --git a/plat/marvell/a8k/a80x0/board/dram_port.c b/plat/marvell/a8k/a80x0/board/dram_port.c index a1eff474..54c4883c 100644 --- a/plat/marvell/a8k/a80x0/board/dram_port.c +++ b/plat/marvell/a8k/a80x0/board/dram_port.c @@ -1,15 +1,16 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #include <arch_helpers.h> #include <a8k_i2c.h> #include <debug.h> #include <mmio.h> #include <mv_ddr_if.h> -#include <plat_def.h> +#include <mvebu_def.h> #include <plat_marvell.h> #define MVEBU_AP_MPP_CTRL0_7_REG MVEBU_AP_MPP_REGS(0) @@ -54,12 +55,12 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_CFG_SPD, /* ddr configuration data source */ { {0} }, /* raw spd data */ {0}, /* timing parameters */ - { /* electrical configuration */ - { /* memory electrical configuration */ + { /* electrical configuration */ + { /* memory electrical configuration */ MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */ { - MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ - MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ }, { MV_DDR_RTT_WR_DYN_ODT_OFF, /* rtt_wr 1cs */ @@ -67,7 +68,7 @@ static struct mv_ddr_topology_map board_topology_map = { }, MV_DDR_DIC_RZQ_DIV7 /* dic */ }, - { /* phy electrical configuration */ + { /* phy electrical configuration */ MV_DDR_OHM_30, /* data_drv_p */ MV_DDR_OHM_30, /* data_drv_n */ MV_DDR_OHM_30, /* ctrl_drv_p */ @@ -81,10 +82,10 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_OHM_120 /* odt_n 2cs */ }, }, - { /* mac electrical configuration */ - MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ + { /* mac electrical configuration */ + MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */ - MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ + MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ }, } }; @@ -117,7 +118,7 @@ static void mpp_config(void) * based on information received from SPD or bootloader * configuration located on non volatile storage */ -void plat_dram_update_topology(void) +void plat_marvell_dram_update_topology(void) { struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); diff --git a/plat/marvell/a8k/a80x0/board/marvell_plat_config.c b/plat/marvell/a8k/a80x0/board/marvell_plat_config.c index 65684434..836c9b40 100644 --- a/plat/marvell/a8k/a80x0/board/marvell_plat_config.c +++ b/plat/marvell/a8k/a80x0/board/marvell_plat_config.c @@ -1,16 +1,17 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -#include <plat_config.h> +#include <armada_common.h> + /* * If bootrom is currently at BLE there's no need to include the memory * maps structure at this point */ -#include <plat_def.h> +#include <mvebu_def.h> #ifndef IMAGE_BLE /***************************************************************************** @@ -22,13 +23,14 @@ struct addr_map_win amb_memory_map[] = { {0xf900, 0x1000000, AMB_SPI1_CS0_ID}, }; -int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { *win = amb_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(amb_memory_map)/sizeof(amb_memory_map[0]); + *size = ARRAY_SIZE(amb_memory_map); return 0; } @@ -60,13 +62,14 @@ uint32_t marvell_get_io_win_gcr_target(int ap_index) return PIDI_TID; } -int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = io_win_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(io_win_memory_map)/sizeof(io_win_memory_map[0]); + *size = ARRAY_SIZE(io_win_memory_map); return 0; } @@ -100,16 +103,17 @@ struct addr_map_win iob_memory_map_cp1[] = { {0x00000000fa000000, 0x1000000, PEX0_TID} }; -int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { switch (base) { case MVEBU_CP_REGS_BASE(0): *win = iob_memory_map_cp0; - *size = sizeof(iob_memory_map_cp0)/sizeof(iob_memory_map_cp0[0]); + *size = ARRAY_SIZE(iob_memory_map_cp0); return 0; case MVEBU_CP_REGS_BASE(1): *win = iob_memory_map_cp1; - *size = sizeof(iob_memory_map_cp1)/sizeof(iob_memory_map_cp1[0]); + *size = ARRAY_SIZE(iob_memory_map_cp1); return 0; default: *size = 0; @@ -138,10 +142,11 @@ uint32_t marvell_get_ccu_gcr_target(int ap) return DRAM_0_TID; } -int marvell_get_ccu_memory_map(int ap, struct addr_map_win **win, uint32_t *size) +int marvell_get_ccu_memory_map(int ap, struct addr_map_win **win, + uint32_t *size) { *win = ccu_memory_map; - *size = sizeof(ccu_memory_map)/sizeof(ccu_memory_map[0]); + *size = ARRAY_SIZE(ccu_memory_map); return 0; } @@ -161,7 +166,7 @@ struct power_off_method pm_cfg = { .cfg.gpio.delay_ms = 10, }; -void *plat_get_pm_cfg(void) +void *plat_marvell_get_pm_cfg(void) { /* Return the PM configurations */ return &pm_cfg; @@ -182,7 +187,7 @@ struct skip_image skip_im = { .info.test.cp_index = 0, }; -void *plat_get_skip_image_data(void) +void *plat_marvell_get_skip_image_data(void) { /* Return the skip_image configurations */ return &skip_im; diff --git a/plat/marvell/a8k/a80x0_32bit_ddr/plat_def.h b/plat/marvell/a8k/a80x0/mvebu_def.h index 7686aa20..5bff12ce 100644 --- a/plat/marvell/a8k/a80x0_32bit_ddr/plat_def.h +++ b/plat/marvell/a8k/a80x0/mvebu_def.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses diff --git a/plat/marvell/a8k/a80x0/platform.mk b/plat/marvell/a8k/a80x0/platform.mk index 4b96ae3f..00d24b27 100644 --- a/plat/marvell/a8k/a80x0/platform.mk +++ b/plat/marvell/a8k/a80x0/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (C) 2016 - 2018 Marvell International Ltd. +# Copyright (C) 2018 Marvell International Ltd. # # SPDX-License-Identifier: BSD-3-Clause # https://spdx.org/licenses diff --git a/plat/marvell/a8k/a80x0_32bit_ddr/board/dram_port.c b/plat/marvell/a8k/a80x0_32bit_ddr/board/dram_port.c index 7b9e4ab5..8eb8810e 100644 --- a/plat/marvell/a8k/a80x0_32bit_ddr/board/dram_port.c +++ b/plat/marvell/a8k/a80x0_32bit_ddr/board/dram_port.c @@ -1,15 +1,16 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #include <arch_helpers.h> #include <a8k_i2c.h> #include <debug.h> #include <mmio.h> #include <mv_ddr_if.h> -#include <plat_def.h> +#include <mvebu_def.h> #include <plat_marvell.h> #define MVEBU_AP_MPP_CTRL0_7_REG MVEBU_AP_MPP_REGS(0) @@ -54,12 +55,12 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ { {0} }, /* raw spd data */ {0}, /* timing parameters */ - { /* electrical configuration */ - { /* memory electrical configuration */ + { /* electrical configuration */ + { /* memory electrical configuration */ MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */ { - MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ - MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ }, { MV_DDR_RTT_WR_DYN_ODT_OFF, /* rtt_wr 1cs */ @@ -67,7 +68,7 @@ static struct mv_ddr_topology_map board_topology_map = { }, MV_DDR_DIC_RZQ_DIV7 /* dic */ }, - { /* phy electrical configuration */ + { /* phy electrical configuration */ MV_DDR_OHM_30, /* data_drv_p */ MV_DDR_OHM_30, /* data_drv_n */ MV_DDR_OHM_30, /* ctrl_drv_p */ @@ -81,10 +82,10 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_OHM_120 /* odt_n 2cs */ }, }, - { /* mac electrical configuration */ - MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ + { /* mac electrical configuration */ + MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */ - MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ + MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ }, } }; @@ -117,7 +118,7 @@ static void mpp_config(void) * based on information received from SPD or bootloader * configuration located on non volatile storage */ -void plat_dram_update_topology(void) +void plat_marvell_dram_update_topology(void) { struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); diff --git a/plat/marvell/a8k/a80x0_32bit_ddr/board/marvell_plat_config.c b/plat/marvell/a8k/a80x0_32bit_ddr/board/marvell_plat_config.c index a154fb0f..c0742b0e 100644 --- a/plat/marvell/a8k/a80x0_32bit_ddr/board/marvell_plat_config.c +++ b/plat/marvell/a8k/a80x0_32bit_ddr/board/marvell_plat_config.c @@ -1,16 +1,17 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -#include <plat_config.h> +#include <armada_common.h> +#include <mvebu_def.h> + /* * If bootrom is currently at BLE there's no need to include the memory * maps structure at this point */ -#include <plat_def.h> #ifndef IMAGE_BLE /***************************************************************************** @@ -22,7 +23,8 @@ struct addr_map_win amb_memory_map[] = { {0xf900, 0x1000000, AMB_SPI1_CS0_ID}, }; -int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { *win = amb_memory_map; if (*win == NULL) @@ -60,7 +62,8 @@ uint32_t marvell_get_io_win_gcr_target(int ap_index) return PIDI_TID; } -int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = io_win_memory_map; if (*win == NULL) @@ -98,7 +101,8 @@ struct addr_map_win iob_memory_map_cp1[] = { {0x00000000fa000000, 0x1000000, PEX0_TID} }; -int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { switch (base) { case MVEBU_CP_REGS_BASE(0): @@ -134,7 +138,8 @@ uint32_t marvell_get_ccu_gcr_target(int ap) return DRAM_0_TID; } -int marvell_get_ccu_memory_map(int ap, struct addr_map_win **win, uint32_t *size) +int marvell_get_ccu_memory_map(int ap, struct addr_map_win **win, + uint32_t *size) { *win = ccu_memory_map; *size = ARRAY_SIZE(ccu_memory_map); diff --git a/plat/marvell/a8k/a80x0_mcbin/plat_def.h b/plat/marvell/a8k/a80x0_32bit_ddr/mvebu_def.h index 3fb268cf..5bff12ce 100644 --- a/plat/marvell/a8k/a80x0_mcbin/plat_def.h +++ b/plat/marvell/a8k/a80x0_32bit_ddr/mvebu_def.h @@ -1,9 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #ifndef __MVEBU_DEF_H__ #define __MVEBU_DEF_H__ diff --git a/plat/marvell/a8k/a80x0_32bit_ddr/platform.mk b/plat/marvell/a8k/a80x0_32bit_ddr/platform.mk index 142d987b..34818c13 100644 --- a/plat/marvell/a8k/a80x0_32bit_ddr/platform.mk +++ b/plat/marvell/a8k/a80x0_32bit_ddr/platform.mk @@ -1,9 +1,16 @@ # -# Copyright (C) 2016 - 2018 Marvell International Ltd. +# Copyright (C) 2018 Marvell International Ltd. # # SPDX-License-Identifier: BSD-3-Clause # https://spdx.org/licenses +PCI_EP_SUPPORT := 0 + +DOIMAGE_SEC := tools/doimage/secure/sec_img_8K.cfg + +MARVELL_MOCHI_DRV := drivers/marvell/mochi/apn806_setup.c + + CP_NUM := 2 $(eval $(call add_define,CP_NUM)) diff --git a/plat/marvell/a8k/a80x0_mcbin/board/dram_port.c b/plat/marvell/a8k/a80x0_mcbin/board/dram_port.c index b0150086..4be98f7b 100644 --- a/plat/marvell/a8k/a80x0_mcbin/board/dram_port.c +++ b/plat/marvell/a8k/a80x0_mcbin/board/dram_port.c @@ -1,15 +1,16 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #include <arch_helpers.h> #include <a8k_i2c.h> #include <debug.h> #include <mmio.h> #include <mv_ddr_if.h> -#include <plat_def.h> +#include <mvebu_def.h> #include <plat_marvell.h> #define MVEBU_CP_MPP_CTRL37_OFFS 20 @@ -48,12 +49,12 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_CFG_SPD, /* ddr configuration data source */ { {0} }, /* raw spd data */ {0}, /* timing parameters */ - { /* electrical configuration */ - { /* memory electrical configuration */ + { /* electrical configuration */ + { /* memory electrical configuration */ MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */ { - MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ - MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ }, { MV_DDR_RTT_WR_DYN_ODT_OFF, /* rtt_wr 1cs */ @@ -61,7 +62,7 @@ static struct mv_ddr_topology_map board_topology_map = { }, MV_DDR_DIC_RZQ_DIV7 /* dic */ }, - { /* phy electrical configuration */ + { /* phy electrical configuration */ MV_DDR_OHM_30, /* data_drv_p */ MV_DDR_OHM_30, /* data_drv_n */ MV_DDR_OHM_30, /* ctrl_drv_p */ @@ -75,10 +76,10 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_OHM_120 /* odt_n 2cs */ }, }, - { /* mac electrical configuration */ - MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ + { /* mac electrical configuration */ + MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */ - MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ + MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ }, } }; @@ -108,7 +109,7 @@ static void mpp_config(void) * based on information received from SPD or bootloader * configuration located on non volatile storage */ -void plat_dram_update_topology(void) +void plat_marvell_dram_update_topology(void) { struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); diff --git a/plat/marvell/a8k/a80x0_mcbin/board/marvell_plat_config.c b/plat/marvell/a8k/a80x0_mcbin/board/marvell_plat_config.c index fbe7ce9e..384d0f54 100644 --- a/plat/marvell/a8k/a80x0_mcbin/board/marvell_plat_config.c +++ b/plat/marvell/a8k/a80x0_mcbin/board/marvell_plat_config.c @@ -1,18 +1,19 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ +#include <armada_common.h> #include <delay_timer.h> #include <mmio.h> -#include <plat_config.h> + /* * If bootrom is currently at BLE there's no need to include the memory * maps structure at this point */ -#include <plat_def.h> +#include <mvebu_def.h> #ifndef IMAGE_BLE /***************************************************************************** @@ -55,13 +56,14 @@ struct addr_map_win amb_memory_map[] = { {0xf900, 0x1000000, AMB_SPI1_CS0_ID}, }; -int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { *win = amb_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(amb_memory_map)/sizeof(amb_memory_map[0]); + *size = ARRAY_SIZE(amb_memory_map); return 0; } @@ -93,13 +95,14 @@ uint32_t marvell_get_io_win_gcr_target(int ap_index) return PIDI_TID; } -int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = io_win_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(io_win_memory_map)/sizeof(io_win_memory_map[0]); + *size = ARRAY_SIZE(io_win_memory_map); return 0; } @@ -133,16 +136,17 @@ struct addr_map_win iob_memory_map_cp1[] = { {0x00000000fa000000, 0x1000000, PEX0_TID} }; -int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { switch (base) { case MVEBU_CP_REGS_BASE(0): *win = iob_memory_map_cp0; - *size = sizeof(iob_memory_map_cp0)/sizeof(iob_memory_map_cp0[0]); + *size = ARRAY_SIZE(iob_memory_map_cp0); return 0; case MVEBU_CP_REGS_BASE(1): *win = iob_memory_map_cp1; - *size = sizeof(iob_memory_map_cp1)/sizeof(iob_memory_map_cp1[0]); + *size = ARRAY_SIZE(iob_memory_map_cp1); return 0; default: *size = 0; @@ -171,10 +175,11 @@ uint32_t marvell_get_ccu_gcr_target(int ap) return DRAM_0_TID; } -int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = ccu_memory_map; - *size = sizeof(ccu_memory_map)/sizeof(ccu_memory_map[0]); + *size = ARRAY_SIZE(ccu_memory_map); return 0; } @@ -185,7 +190,7 @@ int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, uint32_t * SKIP IMAGE Configuration ***************************************************************************** */ -void *plat_get_skip_image_data(void) +void *plat_marvell_get_skip_image_data(void) { /* No recovery button on A8k-MCBIN board */ return NULL; diff --git a/plat/marvell/a8k/a80x0/plat_def.h b/plat/marvell/a8k/a80x0_mcbin/mvebu_def.h index 8b98cc70..5bff12ce 100644 --- a/plat/marvell/a8k/a80x0/plat_def.h +++ b/plat/marvell/a8k/a80x0_mcbin/mvebu_def.h @@ -1,10 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ - + #ifndef __MVEBU_DEF_H__ #define __MVEBU_DEF_H__ diff --git a/plat/marvell/a8k/a80x0_mcbin/platform.mk b/plat/marvell/a8k/a80x0_mcbin/platform.mk index 667f1d27..3749c378 100644 --- a/plat/marvell/a8k/a80x0_mcbin/platform.mk +++ b/plat/marvell/a8k/a80x0_mcbin/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (C) 2016 - 2018 Marvell International Ltd. +# Copyright (C) 2018 Marvell International Ltd. # # SPDX-License-Identifier: BSD-3-Clause # https://spdx.org/licenses diff --git a/plat/marvell/a8k/a80x0_ocp/board/dram_port.c b/plat/marvell/a8k/a80x0_ocp/board/dram_port.c index 4c836707..e4acc98c 100644 --- a/plat/marvell/a8k/a80x0_ocp/board/dram_port.c +++ b/plat/marvell/a8k/a80x0_ocp/board/dram_port.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses @@ -7,10 +7,10 @@ #include <arch_helpers.h> #include <a8k_i2c.h> #include <debug.h> +#include <mvebu_def.h> #include <mmio.h> #include <mv_ddr_if.h> #include <plat_marvell.h> -#include <plat_def.h> /* * This struct provides the DRAM training code with @@ -40,12 +40,12 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ { {0} }, /* raw spd data */ {0}, /* timing parameters */ - { /* electrical configuration */ - { /* memory electrical configuration */ + { /* electrical configuration */ + { /* memory electrical configuration */ MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */ { - MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ - MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ }, { MV_DDR_RTT_WR_DYN_ODT_OFF, /* rtt_wr 1cs */ @@ -53,7 +53,7 @@ static struct mv_ddr_topology_map board_topology_map = { }, MV_DDR_DIC_RZQ_DIV7 /* dic */ }, - { /* phy electrical configuration */ + { /* phy electrical configuration */ MV_DDR_OHM_30, /* data_drv_p */ MV_DDR_OHM_30, /* data_drv_n */ MV_DDR_OHM_30, /* ctrl_drv_p */ @@ -67,10 +67,10 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_OHM_120 /* odt_n 2cs */ }, }, - { /* mac electrical configuration */ - MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ + { /* mac electrical configuration */ + MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */ - MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ + MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ }, } }; @@ -86,6 +86,6 @@ struct mv_ddr_topology_map *mv_ddr_topology_map_get(void) * based on information received from SPD or bootloader * configuration located on non volatile storage */ -void plat_dram_update_topology(void) +void plat_marvell_dram_update_topology(void) { } diff --git a/plat/marvell/a8k/a80x0_ocp/board/marvell_plat_config.c b/plat/marvell/a8k/a80x0_ocp/board/marvell_plat_config.c index 833ba7c7..2c10ca88 100644 --- a/plat/marvell/a8k/a80x0_ocp/board/marvell_plat_config.c +++ b/plat/marvell/a8k/a80x0_ocp/board/marvell_plat_config.c @@ -1,15 +1,18 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -#include <plat_config.h> + +#include <armada_common.h> +#include <mvebu_def.h> +#include <pci_ep.h> + /* * If bootrom is currently at BLE there's no need to include the memory * maps structure at this point */ -#include <plat_def.h> #ifndef IMAGE_BLE /***************************************************************************** @@ -18,13 +21,14 @@ */ struct addr_map_win *amb_memory_map; -int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { *win = amb_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(amb_memory_map)/sizeof(amb_memory_map[0]); + *size = ARRAY_SIZE(amb_memory_map); return 0; } @@ -50,13 +54,14 @@ uint32_t marvell_get_io_win_gcr_target(int ap_index) return PIDI_TID; } -int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = io_win_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(io_win_memory_map)/sizeof(io_win_memory_map[0]); + *size = ARRAY_SIZE(io_win_memory_map); return 0; } @@ -72,12 +77,13 @@ struct addr_map_win iob_memory_map_cp0[] = { {0x0000008000000000, 0x800000000, PEX0_TID} }; -int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { switch (base) { case MVEBU_CP_REGS_BASE(0): *win = iob_memory_map_cp0; - *size = sizeof(iob_memory_map_cp0)/sizeof(iob_memory_map_cp0[0]); + *size = ARRAY_SIZE(iob_memory_map_cp0); return 0; case MVEBU_CP_REGS_BASE(1): *size = 0; @@ -109,10 +115,11 @@ uint32_t marvell_get_ccu_gcr_target(int ap) return DRAM_0_TID; } -int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = ccu_memory_map; - *size = sizeof(ccu_memory_map)/sizeof(ccu_memory_map[0]); + *size = ARRAY_SIZE(ccu_memory_map); return 0; } diff --git a/plat/marvell/a8k/a80x0_ocp/plat_def.h b/plat/marvell/a8k/a80x0_ocp/mvebu_def.h index 51b0ee8f..51b0ee8f 100644 --- a/plat/marvell/a8k/a80x0_ocp/plat_def.h +++ b/plat/marvell/a8k/a80x0_ocp/mvebu_def.h diff --git a/plat/marvell/a8k/common/a8k_common.mk b/plat/marvell/a8k/common/a8k_common.mk index 64886ea4..b032b19d 100644 --- a/plat/marvell/a8k/common/a8k_common.mk +++ b/plat/marvell/a8k/common/a8k_common.mk @@ -13,6 +13,8 @@ PLAT_COMMON_BASE := $(PLAT_FAMILY_BASE)/common MARVELL_DRV_BASE := drivers/marvell MARVELL_COMMON_BASE := plat/marvell/common +$(eval $(call add_define,PLAT_FAMILY)) + ERRATA_A72_859971 := 1 # Enable MSS support for a8k family @@ -61,15 +63,15 @@ BLE_PORTING_SOURCES := $(PLAT_FAMILY_BASE)/$(PLAT)/board/dram_port.c \ MARVELL_MOCHI_DRV += $(MARVELL_DRV_BASE)/mochi/cp110_setup.c -BLE_SOURCES := $(PLAT_COMMON_BASE)/plat_ble_setup.c \ - $(MARVELL_MOCHI_DRV) \ - $(MARVELL_DRV_BASE)/i2c/a8k_i2c.c \ - $(PLAT_COMMON_BASE)/plat_pm.c \ - $(MARVELL_DRV_BASE)/aro.c \ - $(MARVELL_DRV_BASE)/thermal.c \ - $(PLAT_COMMON_BASE)/plat_thermal.c \ - $(BLE_PORTING_SOURCES) \ - $(MARVELL_DRV_BASE)/ccu.c \ +BLE_SOURCES := $(PLAT_COMMON_BASE)/plat_ble_setup.c \ + $(MARVELL_MOCHI_DRV) \ + $(MARVELL_DRV_BASE)/i2c/a8k_i2c.c \ + $(PLAT_COMMON_BASE)/plat_pm.c \ + $(MARVELL_DRV_BASE)/aro.c \ + $(MARVELL_DRV_BASE)/thermal.c \ + $(PLAT_COMMON_BASE)/plat_thermal.c \ + $(BLE_PORTING_SOURCES) \ + $(MARVELL_DRV_BASE)/ccu.c \ $(MARVELL_DRV_BASE)/io_win.c ifeq (${PCI_EP_SUPPORT}, 1) diff --git a/plat/marvell/a8k/common/aarch64/a8k_common.c b/plat/marvell/a8k/common/aarch64/a8k_common.c index 86814320..b9e02cb9 100644 --- a/plat/marvell/a8k/common/aarch64/a8k_common.c +++ b/plat/marvell/a8k/common/aarch64/a8k_common.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses diff --git a/plat/marvell/a8k/common/aarch64/plat_arch_config.c b/plat/marvell/a8k/common/aarch64/plat_arch_config.c index 131421be..86673314 100644 --- a/plat/marvell/a8k/common/aarch64/plat_arch_config.c +++ b/plat/marvell/a8k/common/aarch64/plat_arch_config.c @@ -1,10 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ - + #include <platform.h> #include <arch_helpers.h> #include <mmio.h> @@ -16,7 +16,7 @@ #define MVEBU_IO_AFFINITY (0xF00) -void plat_enable_affinity(void) +static void plat_enable_affinity(void) { int cluster_id; int affinity; @@ -27,10 +27,10 @@ void plat_enable_affinity(void) mmio_write_32(CCU_HTC_ASET, affinity); /* set barier */ - __asm__ volatile("isb"); + isb(); } -void psci_arch_init(int die_index) +void marvell_psci_arch_init(int die_index) { #if LLC_ENABLE /* check if LLC is in exclusive mode diff --git a/plat/marvell/a8k/common/aarch64/plat_helpers.S b/plat/marvell/a8k/common/aarch64/plat_helpers.S index e6a8eed8..fadc4c26 100644 --- a/plat/marvell/a8k/common/aarch64/plat_helpers.S +++ b/plat/marvell/a8k/common/aarch64/plat_helpers.S @@ -1,10 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ - + #include <asm_macros.S> #include <platform_def.h> #include <marvell_pm.h> @@ -38,11 +38,12 @@ endfunc plat_secondary_cold_boot_setup * --------------------------------------------------------------------- */ func plat_get_my_entrypoint - mov_imm x0, PLAT_MARVELL_MAILBOX_BASE /* Read first word and compare it with magic num */ + /* Read first word and compare it with magic num */ + mov_imm x0, PLAT_MARVELL_MAILBOX_BASE ldr x1, [x0] mov_imm x2, MVEBU_MAILBOX_MAGIC_NUM cmp x1, x2 - beq warm_boot /* If compare failed, return 0, i.e. cold boot */ + beq warm_boot /* If compare failed, return 0, i.e. cold boot */ mov x0, #0 ret warm_boot: diff --git a/plat/marvell/a8k/common/include/a8k_plat_def.h b/plat/marvell/a8k/common/include/a8k_plat_def.h index 80607d93..95f8c417 100644 --- a/plat/marvell/a8k/common/include/a8k_plat_def.h +++ b/plat/marvell/a8k/common/include/a8k_plat_def.h @@ -1,12 +1,12 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -#ifndef __MVEBU_A8K_DEF_H__ -#define __MVEBU_A8K_DEF_H__ +#ifndef __A8K_PLAT_DEF_H__ +#define __A8K_PLAT_DEF_H__ #include <marvell_def.h> @@ -55,9 +55,11 @@ #define MVEBU_PM_MPP_REGS(cp_index, n) (MVEBU_CP_REGS_BASE(cp_index) + \ 0x440000 + ((n / 8) << 2)) #define MVEBU_CP_GPIO_DATA_OUT(cp_index, n) \ - (MVEBU_CP_REGS_BASE(cp_index) + 0x440100 + ((n > 32) ? 0x40 : 0x00)) + (MVEBU_CP_REGS_BASE(cp_index) + \ + 0x440100 + ((n > 32) ? 0x40 : 0x00)) #define MVEBU_CP_GPIO_DATA_OUT_EN(cp_index, n) \ - (MVEBU_CP_REGS_BASE(cp_index) + 0x440104 + ((n > 32) ? 0x40 : 0x00)) + (MVEBU_CP_REGS_BASE(cp_index) + \ + 0x440104 + ((n > 32) ? 0x40 : 0x00)) #define MVEBU_CP_GPIO_DATA_IN(cp_index, n) (MVEBU_CP_REGS_BASE(cp_index) + \ 0x440110 + ((n > 32) ? 0x40 : 0x00)) #define MVEBU_AP_MPP_REGS(n) (MVEBU_RFU_BASE + 0x4000 + ((n) << 2)) @@ -67,40 +69,47 @@ #define MVEBU_CP0_I2C_BASE (MVEBU_CP_REGS_BASE(0) + 0x701000) #define MVEBU_AP_EXT_TSEN_BASE (MVEBU_RFU_BASE + 0x8084) -#define MVEBU_AP_MC_TRUSTZONE_REG_LOW(ap, win) (MVEBU_REGS_BASE_AP(ap) + 0x20080 + ((win) * 0x8)) -#define MVEBU_AP_MC_TRUSTZONE_REG_HIGH(ap, win) (MVEBU_REGS_BASE_AP(ap) + 0x20084 + ((win) * 0x8)) +#define MVEBU_AP_MC_TRUSTZONE_REG_LOW(ap, win) (MVEBU_REGS_BASE_AP(ap) + \ + 0x20080 + ((win) * 0x8)) +#define MVEBU_AP_MC_TRUSTZONE_REG_HIGH(ap, win) (MVEBU_REGS_BASE_AP(ap) + \ + 0x20084 + ((win) * 0x8)) /* MCI indirect access definitions */ #define MCI_MAX_UNIT_ID 2 /* SoC RFU / IHBx4 Control */ -#define MCIX4_REG_START_ADDRESS_REG(unit_id) (MVEBU_RFU_BASE + 0x4218 + (unit_id * 0x20)) +#define MCIX4_REG_START_ADDRESS_REG(unit_id) (MVEBU_RFU_BASE + \ + 0x4218 + (unit_id * 0x20)) #define MCI_REMAP_OFF_SHIFT 8 -#define MVEBU_MCI_REG_BASE_REMAP(index) (0xFD000000 + ((index) * 0x1000000)) +#define MVEBU_MCI_REG_BASE_REMAP(index) (0xFD000000 + \ + ((index) * 0x1000000)) #define MVEBU_PCIE_X4_MAC_BASE(x) (MVEBU_CP_REGS_BASE(x) + 0x600000) #define MVEBU_COMPHY_BASE(x) (MVEBU_CP_REGS_BASE(x) + 0x441000) #define MVEBU_HPIPE_BASE(x) (MVEBU_CP_REGS_BASE(x) + 0x120000) #define MVEBU_CP_DFX_OFFSET (0x400200) -/******************************************************************************* +/***************************************************************************** * MVEBU memory map related constants - ******************************************************************************/ + ***************************************************************************** + */ /* Aggregate of all devices in the first GB */ #define DEVICE0_BASE MVEBU_REGS_BASE #define DEVICE0_SIZE 0x10000000 /******************************************************************************* * GIC-400 & interrupt handling related constants - ******************************************************************************/ + ***************************************************************************** + */ /* Base MVEBU compatible GIC memory map */ #define MVEBU_GICD_BASE 0x210000 #define MVEBU_GICC_BASE 0x220000 -/******************************************************************************* +/***************************************************************************** * AXI Configuration - ******************************************************************************/ + ***************************************************************************** + */ #define MVEBU_AXI_ATTR_ARCACHE_OFFSET 4 #define MVEBU_AXI_ATTR_ARCACHE_MASK (0xF << \ MVEBU_AXI_ATTR_ARCACHE_OFFSET) @@ -133,9 +142,9 @@ #define DOMAIN_OUTER_SHAREABLE 0x2 #define DOMAIN_SYSTEM_SHAREABLE 0x3 -/************************************************************************* +/************************************************************************ * Required platform porting definitions common to all - * Mangement Compute SubSystems (MSS) + * Management Compute SubSystems (MSS) ************************************************************************ */ /* diff --git a/plat/marvell/a8k/common/include/ddr_info.h b/plat/marvell/a8k/common/include/ddr_info.h index ae90dbd0..e19036a2 100644 --- a/plat/marvell/a8k/common/include/ddr_info.h +++ b/plat/marvell/a8k/common/include/ddr_info.h @@ -1,4 +1,3 @@ - /* * Copyright (C) 2018 Marvell International Ltd. * diff --git a/plat/marvell/a8k/common/include/plat_macros.S b/plat/marvell/a8k/common/include/plat_macros.S index b082208d..2a6ccf27 100644 --- a/plat/marvell/a8k/common/include/plat_macros.S +++ b/plat/marvell/a8k/common/include/plat_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses diff --git a/plat/marvell/a8k/common/include/platform_def.h b/plat/marvell/a8k/common/include/platform_def.h index ac65c662..45650ef6 100644 --- a/plat/marvell/a8k/common/include/platform_def.h +++ b/plat/marvell/a8k/common/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses @@ -11,7 +11,7 @@ #include <board_marvell_def.h> #include <gic_common.h> #include <interrupt_props.h> -#include <plat_def.h> +#include <mvebu_def.h> #ifndef __ASSEMBLY__ #include <stdio.h> #endif /* __ASSEMBLY__ */ @@ -137,8 +137,8 @@ GIC_INTR_CFG_LEVEL) #define PLAT_MARVELL_G1S_IRQ_PROPS(grp) \ - INTR_PROP_DESC(MARVELL_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(MARVELL_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL), \ INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ GIC_INTR_CFG_LEVEL), \ INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ @@ -191,8 +191,11 @@ /* System timer related constants */ #define PLAT_MARVELL_NSTIMER_FRAME_ID 1 -/* Mailbox base address (note the lower memory space are reserved for BLE data) */ -#define PLAT_MARVELL_MAILBOX_BASE (MARVELL_TRUSTED_SRAM_BASE + 0x400) +/* Mailbox base address (note the lower memory space + * is reserved for BLE data) + */ +#define PLAT_MARVELL_MAILBOX_BASE (MARVELL_TRUSTED_SRAM_BASE \ + + 0x400) #define PLAT_MARVELL_MAILBOX_SIZE 0x100 #define PLAT_MARVELL_MAILBOX_MAGIC_NUM 0x6D72766C /* mrvl */ diff --git a/plat/marvell/a8k/common/mss/mss_a8k.mk b/plat/marvell/a8k/common/mss/mss_a8k.mk index 7ca9132f..58f23d8d 100644 --- a/plat/marvell/a8k/common/mss/mss_a8k.mk +++ b/plat/marvell/a8k/common/mss/mss_a8k.mk @@ -1,18 +1,18 @@ # -# Copyright (C) 2016 - 2018 Marvell International Ltd. +# Copyright (C) 2018 Marvell International Ltd. # # SPDX-License-Identifier: BSD-3-Clause # https://spdx.org/licenses # -PLAT_MARVELL := plat/marvell -A8K_MSS_SOURCE := $(PLAT_MARVELL)/a8k/common/mss +PLAT_MARVELL := plat/marvell +A8K_MSS_SOURCE := $(PLAT_MARVELL)/a8k/common/mss BL2_SOURCES += $(A8K_MSS_SOURCE)/mss_bl2_setup.c BL31_SOURCES += $(A8K_MSS_SOURCE)/mss_pm_ipc.c -PLAT_INCLUDES += -I$(A8K_MSS_SOURCE) +PLAT_INCLUDES += -I$(A8K_MSS_SOURCE) ifneq (${SCP_BL2},) # This define is used to inidcate the SCP image is present diff --git a/plat/marvell/a8k/common/mss/mss_bl2_setup.c b/plat/marvell/a8k/common/mss/mss_bl2_setup.c index df73a886..58a9472b 100644 --- a/plat/marvell/a8k/common/mss/mss_bl2_setup.c +++ b/plat/marvell/a8k/common/mss/mss_bl2_setup.c @@ -1,17 +1,18 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + +#include <armada_common.h> #include <bl_common.h> #include <ccu.h> #include <cp110_setup.h> #include <debug.h> +#include <marvell_plat_priv.h> /* timer functionality */ #include <mmio.h> -#include <plat_config.h> #include <platform_def.h> -#include <plat_private.h> /* timer functionality */ #include "mss_scp_bootloader.h" @@ -53,7 +54,7 @@ static int bl2_plat_mmap_init(void) { int cfg_num, win_id, cfg_idx; - cfg_num = sizeof(ccu_mem_map) / sizeof(ccu_mem_map[0]); + cfg_num = ARRAY_SIZE(ccu_mem_map); /* CCU window-0 should not be counted - it's already used */ if (cfg_num > (MVEBU_CCU_MAX_WINS - 1)) { @@ -77,10 +78,11 @@ static int bl2_plat_mmap_init(void) return 0; } -/******************************************************************************* +/***************************************************************************** * Transfer SCP_BL2 from Trusted RAM using the SCP Download protocol. * Return 0 on success, -1 otherwise. - ******************************************************************************/ + ***************************************************************************** + */ int bl2_plat_handle_scp_bl2(image_info_t *scp_bl2_image_info) { int ret; @@ -122,7 +124,8 @@ uint32_t bl2_plat_get_cp_count(int ap_idx) /* A8040: two CPs. * A7040: one CP. */ - if (revision == MVEBU_80X0_DEV_ID || revision == MVEBU_80X0_CP115_DEV_ID) + if (revision == MVEBU_80X0_DEV_ID || + revision == MVEBU_80X0_CP115_DEV_ID) return 2; else return 1; diff --git a/plat/marvell/a8k/common/mss/mss_pm_ipc.c b/plat/marvell/a8k/common/mss/mss_pm_ipc.c index 0088f8c1..6ff4abcc 100644 --- a/plat/marvell/a8k/common/mss/mss_pm_ipc.c +++ b/plat/marvell/a8k/common/mss/mss_pm_ipc.c @@ -1,9 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #include <debug.h> #include <mmio.h> #include <psci.h> @@ -12,14 +13,14 @@ #include <mss_pm_ipc.h> /* -** SISR is 32 bit interrupt register representing 32 interrupts -** -** +======+=============+=============+ -** + Bits + 31 + 30 - 00 + -** +======+=============+=============+ -** + Desc + MSS Msg Int + Reserved + -** +======+=============+=============+ -*/ + * SISR is 32 bit interrupt register representing 32 interrupts + * + * +======+=============+=============+ + * + Bits + 31 + 30 - 00 + + * +======+=============+=============+ + * + Desc + MSS Msg Int + Reserved + + * +======+=============+=============+ + */ #define MSS_SISR (MVEBU_REGS_BASE + 0x5800D0) #define MSS_SISTR (MVEBU_REGS_BASE + 0x5800D8) @@ -27,16 +28,20 @@ #define MSS_TIMER_BASE (MVEBU_REGS_BASE_MASK + 0x580110) #define MSS_TRIGGER_TIMEOUT (1000) -/******************************************************************************* -* mss_pm_ipc_msg_send -* -* DESCRIPTION: create and transmit IPC message -*******************************************************************************/ -int mss_pm_ipc_msg_send(unsigned int channel_id, unsigned int msg_id, const psci_power_state_t *target_state) +/***************************************************************************** + * mss_pm_ipc_msg_send + * + * DESCRIPTION: create and transmit IPC message + ***************************************************************************** + */ +int mss_pm_ipc_msg_send(unsigned int channel_id, unsigned int msg_id, + const psci_power_state_t *target_state) { /* Transmit IPC message */ #ifndef DISABLE_CLUSTER_LEVEL - mv_pm_ipc_msg_tx(channel_id, msg_id, (unsigned int)target_state->pwr_domain_state[MPIDR_AFFLVL1]); + mv_pm_ipc_msg_tx(channel_id, msg_id, + (unsigned int)target_state->pwr_domain_state[ + MPIDR_AFFLVL1]); #else mv_pm_ipc_msg_tx(channel_id, msg_id, 0); #endif @@ -44,11 +49,12 @@ int mss_pm_ipc_msg_send(unsigned int channel_id, unsigned int msg_id, const psci return 0; } -/******************************************************************************* -* mss_pm_ipc_msg_trigger -* -* DESCRIPTION: Trigger IPC message interrupt to MSS -*******************************************************************************/ +/***************************************************************************** + * mss_pm_ipc_msg_trigger + * + * DESCRIPTION: Trigger IPC message interrupt to MSS + ***************************************************************************** + */ int mss_pm_ipc_msg_trigger(void) { unsigned int timeout; @@ -65,7 +71,8 @@ int mss_pm_ipc_msg_trigger(void) /* check timeout */ t_end = mmio_read_32(MSS_TIMER_BASE); - timeout = ((t_start > t_end) ? (t_start - t_end) : (t_end - t_start)); + timeout = ((t_start > t_end) ? + (t_start - t_end) : (t_end - t_start)); if (timeout > MSS_TRIGGER_TIMEOUT) { ERROR("PM MSG Trigger Timeout\n"); break; diff --git a/plat/marvell/a8k/common/mss/mss_pm_ipc.h b/plat/marvell/a8k/common/mss/mss_pm_ipc.h index b1b9cfc6..0f694570 100644 --- a/plat/marvell/a8k/common/mss/mss_pm_ipc.h +++ b/plat/marvell/a8k/common/mss/mss_pm_ipc.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses @@ -15,19 +15,20 @@ /***************************************************************************** -* mss_pm_ipc_msg_send -* -* DESCRIPTION: create and transmit IPC message -****************************************************************************** -*/ -int mss_pm_ipc_msg_send(unsigned int channel_id, unsigned int msg_id, const psci_power_state_t *target_state); + * mss_pm_ipc_msg_send + * + * DESCRIPTION: create and transmit IPC message + ***************************************************************************** + */ +int mss_pm_ipc_msg_send(unsigned int channel_id, unsigned int msg_id, + const psci_power_state_t *target_state); /***************************************************************************** -* mss_pm_ipc_msg_trigger -* -* DESCRIPTION: Trigger IPC message interrupt to MSS -****************************************************************************** -*/ + * mss_pm_ipc_msg_trigger + * + * DESCRIPTION: Trigger IPC message interrupt to MSS + ***************************************************************************** + */ int mss_pm_ipc_msg_trigger(void); diff --git a/plat/marvell/a8k/common/plat_bl1_setup.c b/plat/marvell/a8k/common/plat_bl1_setup.c index ba8a4f78..5d851027 100644 --- a/plat/marvell/a8k/common/plat_bl1_setup.c +++ b/plat/marvell/a8k/common/plat_bl1_setup.c @@ -1,10 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ - + #include <mmio.h> #include <plat_marvell.h> diff --git a/plat/marvell/a8k/common/plat_bl31_setup.c b/plat/marvell/a8k/common/plat_bl31_setup.c index 7d510645..7985e1d9 100644 --- a/plat/marvell/a8k/common/plat_bl31_setup.c +++ b/plat/marvell/a8k/common/plat_bl31_setup.c @@ -1,19 +1,19 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ +#include <armada_common.h> #include <ap_setup.h> #include <cp110_setup.h> #include <debug.h> +#include <marvell_plat_priv.h> #include <marvell_pm.h> #include <mmio.h> #include <mci.h> -#include <plat_config.h> #include <plat_marvell.h> -#include <plat_private.h> #include <mc_trustzone/mc_trustzone.h> #include <mss_ipc_drv.h> @@ -57,7 +57,7 @@ void marvell_bl31_mss_init(void) (struct mss_pm_ctrl_block *)MSS_SRAM_PM_CONTROL_BASE; /* Check that the image was loaded successfully */ - if (mss_pm_crtl->handshake != HOST_ACKNOWLEDGEMENT) { + if (mss_pm_crtl->handshake != HOST_ACKNOWLEDGMENT) { NOTICE("MSS PM is not supported in this build\n"); return; } diff --git a/plat/marvell/a8k/common/plat_ble_setup.c b/plat/marvell/a8k/common/plat_ble_setup.c index 359524e5..29d896a3 100644 --- a/plat/marvell/a8k/common/plat_ble_setup.c +++ b/plat/marvell/a8k/common/plat_ble_setup.c @@ -1,19 +1,19 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ #include <ap_setup.h> +#include <armada_common.h> #include <aro.h> #include <ccu.h> #include <cp110_setup.h> #include <debug.h> #include <io_win.h> #include <mv_ddr_if.h> -#include <plat_config.h> -#include <plat_def.h> +#include <mvebu_def.h> #include <plat_marvell.h> /* Register for skip image use */ @@ -84,18 +84,18 @@ #define AP807_CPU_ARO_SEL_PLL_MASK (0x1 << AP807_CPU_ARO_SEL_PLL_OFFSET) /* - - AVS work points in the LD0 eFuse: - SVC1 work point: LD0[88:81] - SVC2 work point: LD0[96:89] - SVC3 work point: LD0[104:97] - SVC4 work point: LD0[112:105] - - Identification information in the LD-0 eFuse: - DRO: LD0[74:65] - Not used by the SW - Revision: LD0[78:75] - Not used by the SW - Bin: LD0[80:79] - Not used by the SW - SW Revision: LD0[115:113] - Cluster 1 PWR: LD0[193] - if set to 1, power down CPU Cluster-1 - resulting in 2 CPUs active only (7020) + * - AVS work points in the LD0 eFuse: + * SVC1 work point: LD0[88:81] + * SVC2 work point: LD0[96:89] + * SVC3 work point: LD0[104:97] + * SVC4 work point: LD0[112:105] + * - Identification information in the LD-0 eFuse: + * DRO: LD0[74:65] - Not used by the SW + * Revision: LD0[78:75] - Not used by the SW + * Bin: LD0[80:79] - Not used by the SW + * SW Revision: LD0[115:113] + * Cluster 1 PWR: LD0[193] - if set to 1, power down CPU Cluster-1 + * resulting in 2 CPUs active only (7020) */ #define MVEBU_AP_LD_EFUSE_BASE (MVEBU_AP_GEN_MGMT_BASE + 0xF00) /* Bits [94:63] - 32 data bits total */ @@ -128,7 +128,8 @@ static unsigned int ble_get_ap_type(void) unsigned int chip_rev_id; chip_rev_id = mmio_read_32(MVEBU_CSS_GWD_CTRL_IIDR2_REG); - chip_rev_id = ((chip_rev_id & GWD_IIDR2_CHIP_ID_MASK) >> GWD_IIDR2_CHIP_ID_OFFSET); + chip_rev_id = ((chip_rev_id & GWD_IIDR2_CHIP_ID_MASK) >> + GWD_IIDR2_CHIP_ID_OFFSET); return chip_rev_id; } @@ -136,15 +137,15 @@ static unsigned int ble_get_ap_type(void) /****************************************************************************** * The routine allows to save the CCU and IO windows configuration during DRAM * setup and restore them afterwards before exiting the BLE stage. - * Such window configuration is requred since not all default settings coming - * from the HW and the BootROM allow access to periferals connected to + * Such window configuration is required since not all default settings coming + * from the HW and the BootROM allow access to peripherals connected to * all available CPn components. * For instance, when the boot device is located on CP0, the IO window to CP1 * is not opened automatically by the HW and if the DRAM SPD is located on CP1 * i2c channel, it cannot be read at BLE stage. * Therefore the DRAM init procedure have to provide access to all available - * CPn periferals during the BLE stage by setting the CCU IO window to all CPn - * addresses and by enabling the IO windows accordingly. + * CPn peripherals during the BLE stage by setting the CCU IO window to all + * CPnph addresses and by enabling the IO windows accordingly. * Additionally this function configures the CCU GCR to DRAM, which allows * usage or more than 4GB DRAM as it configured by the default CCU DRAM window. * @@ -163,28 +164,30 @@ static void ble_plat_mmap_config(int restore) /* Restore CCU */ iow_restore_win_all(MVEBU_AP0); return; - } else { + } + /* Store original values */ ccu_save_win_all(MVEBU_AP0); /* Save CCU */ iow_save_win_all(MVEBU_AP0); - } init_ccu(MVEBU_AP0); /* The configuration saved, now all the changes can be done */ init_io_win(MVEBU_AP0); } -/****************************************************************************** +/**************************************************************************** * Setup Adaptive Voltage Switching - this is required for some platforms - *****************************************************************************/ + **************************************************************************** + */ static void ble_plat_avs_config(void) { uint32_t reg_val, device_id; /* Due to a bug in A3900 device_id we need a special handling here */ if (ble_get_ap_type() == CHIP_ID_AP807) { - VERBOSE("AVS: Setting AP807 AVS CTRL to 0x%x\n", AVS_A3900_CLK_VALUE); + VERBOSE("AVS: Setting AP807 AVS CTRL to 0x%x\n", + AVS_A3900_CLK_VALUE); mmio_write_32(AVS_EN_CTRL_REG, AVS_A3900_CLK_VALUE); return; } @@ -213,16 +216,18 @@ static void ble_plat_avs_config(void) } } -/****************************************************************************** +/**************************************************************************** * SVC flow - v0.10 - * The feature is inteded to configure AVS value according to eFuse values + * The feature is intended to configure AVS value according to eFuse values * that are burned individually for each SoC during the test process. - * Primary AVS value is stored in HD efuse and processed on power on by the HW engine + * Primary AVS value is stored in HD efuse and processed on power on + * by the HW engine * Secondary AVS value is located in LD efuse and contains 4 work points for * various CPU frequencies. * The Secondary AVS value is only taken into account if the SW Revision stored * in the efuse is greater than 0 and the CPU is running in a certain speed. - *****************************************************************************/ + **************************************************************************** + */ static void ble_plat_svc_config(void) { uint32_t reg_val, avs_workpoint, freq_pidi_mode; @@ -468,7 +473,7 @@ static int ble_skip_current_image(void) struct skip_image *skip_im; /*fetching skip image info*/ - skip_im = (struct skip_image *)plat_get_skip_image_data(); + skip_im = (struct skip_image *)plat_marvell_get_skip_image_data(); if (skip_im == NULL) return 0; @@ -526,7 +531,7 @@ int ble_plat_setup(int *skip) /* * Save the current CCU configuration and make required changes: * - Allow access to DRAM larger than 4GB - * - Open memory access to all CPn periferals + * - Open memory access to all CPn peripherals */ ble_plat_mmap_config(MMAP_SAVE_AND_CONFIG); @@ -557,7 +562,7 @@ int ble_plat_setup(int *skip) ap_ble_init(); /* Update DRAM topology (scan DIMM SPDs) */ - plat_dram_update_topology(); + plat_marvell_dram_update_topology(); /* Kick it in */ ret = dram_init(); diff --git a/plat/marvell/a8k/common/plat_pm.c b/plat/marvell/a8k/common/plat_pm.c index 7fcbfa36..f57d18a6 100644 --- a/plat/marvell/a8k/common/plat_pm.c +++ b/plat/marvell/a8k/common/plat_pm.c @@ -5,6 +5,7 @@ * https://spdx.org/licenses */ +#include <armada_common.h> #include <assert.h> #include <bakery_lock.h> #include <debug.h> @@ -15,7 +16,6 @@ #include <marvell_pm.h> #include <mmio.h> #include <mss_pm_ipc.h> -#include <plat_config.h> #include <plat_marvell.h> #include <platform.h> #include <plat_pm_trace.h> @@ -58,7 +58,7 @@ DEFINE_BAKERY_LOCK(pm_sys_lock); /* Weak definitions may be overridden in specific board */ -#pragma weak plat_get_pm_cfg +#pragma weak plat_marvell_get_pm_cfg /* AP806 CPU power down /power up definitions */ enum CPU_ID { @@ -70,9 +70,11 @@ enum CPU_ID { #define REG_WR_VALIDATE_TIMEOUT (2000) -#define FEATURE_DISABLE_STATUS_REG (MVEBU_REGS_BASE + 0x6F8230) +#define FEATURE_DISABLE_STATUS_REG \ + (MVEBU_REGS_BASE + 0x6F8230) #define FEATURE_DISABLE_STATUS_CPU_CLUSTER_OFFSET 4 -#define FEATURE_DISABLE_STATUS_CPU_CLUSTER_MASK (0x1 << FEATURE_DISABLE_STATUS_CPU_CLUSTER_OFFSET) +#define FEATURE_DISABLE_STATUS_CPU_CLUSTER_MASK \ + (0x1 << FEATURE_DISABLE_STATUS_CPU_CLUSTER_OFFSET) #ifdef MVEBU_SOC_AP807 #define PWRC_CPUN_CR_PWR_DN_RQ_OFFSET 1 @@ -82,21 +84,29 @@ enum CPU_ID { #define PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET 31 #endif -#define PWRC_CPUN_CR_REG(cpu_id) (MVEBU_REGS_BASE + 0x680000 + (cpu_id * 0x10)) -#define PWRC_CPUN_CR_PWR_DN_RQ_MASK (0x1 << PWRC_CPUN_CR_PWR_DN_RQ_OFFSET) +#define PWRC_CPUN_CR_REG(cpu_id) \ + (MVEBU_REGS_BASE + 0x680000 + (cpu_id * 0x10)) +#define PWRC_CPUN_CR_PWR_DN_RQ_MASK \ + (0x1 << PWRC_CPUN_CR_PWR_DN_RQ_OFFSET) #define PWRC_CPUN_CR_ISO_ENABLE_OFFSET 16 -#define PWRC_CPUN_CR_ISO_ENABLE_MASK (0x1 << PWRC_CPUN_CR_ISO_ENABLE_OFFSET) -#define PWRC_CPUN_CR_LDO_BYPASS_RDY_MASK (0x1 << PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET) +#define PWRC_CPUN_CR_ISO_ENABLE_MASK \ + (0x1 << PWRC_CPUN_CR_ISO_ENABLE_OFFSET) +#define PWRC_CPUN_CR_LDO_BYPASS_RDY_MASK \ + (0x1 << PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET) -#define CCU_B_PRCRN_REG(cpu_id) (MVEBU_REGS_BASE + 0x1A50 + \ +#define CCU_B_PRCRN_REG(cpu_id) \ + (MVEBU_REGS_BASE + 0x1A50 + \ ((cpu_id / 2) * (0x400)) + ((cpu_id % 2) * 4)) #define CCU_B_PRCRN_CPUPORESET_STATIC_OFFSET 0 -#define CCU_B_PRCRN_CPUPORESET_STATIC_MASK (0x1 << CCU_B_PRCRN_CPUPORESET_STATIC_OFFSET) +#define CCU_B_PRCRN_CPUPORESET_STATIC_MASK \ + (0x1 << CCU_B_PRCRN_CPUPORESET_STATIC_OFFSET) /* power switch fingers */ -#define AP807_PWRC_LDO_CR0_REG (MVEBU_REGS_BASE + 0x680000 + 0x100) +#define AP807_PWRC_LDO_CR0_REG \ + (MVEBU_REGS_BASE + 0x680000 + 0x100) #define AP807_PWRC_LDO_CR0_OFFSET 16 -#define AP807_PWRC_LDO_CR0_MASK (0xff << AP807_PWRC_LDO_CR0_OFFSET) +#define AP807_PWRC_LDO_CR0_MASK \ + (0xff << AP807_PWRC_LDO_CR0_OFFSET) #define AP807_PWRC_LDO_CR0_VAL 0xfd /* @@ -456,7 +466,7 @@ static void a8k_pwr_domain_off(const psci_power_state_t *target_state) } /* Get PM config to power off the SoC */ -void *plat_get_pm_cfg(void) +void *plat_marvell_get_pm_cfg(void) { return NULL; } @@ -468,9 +478,9 @@ void *plat_get_pm_cfg(void) * the system recovery * */ -static void plat_exit_bootrom(void) +static void plat_marvell_exit_bootrom(void) { - exit_bootrom(PLAT_MARVELL_TRUSTED_ROM_BASE); + marvell_exit_bootrom(PLAT_MARVELL_TRUSTED_ROM_BASE); } /* @@ -607,12 +617,13 @@ static void a8k_pwr_domain_suspend(const psci_power_state_t *target_state) gicv2_cpuif_disable(); mailbox[MBOX_IDX_SUSPEND_MAGIC] = MVEBU_MAILBOX_SUSPEND_STATE; - mailbox[MBOX_IDX_ROM_EXIT_ADDR] = (uintptr_t)&plat_exit_bootrom; + mailbox[MBOX_IDX_ROM_EXIT_ADDR] = + (uintptr_t)&plat_marvell_exit_bootrom; #if PLAT_MARVELL_SHARED_RAM_CACHED flush_dcache_range(PLAT_MARVELL_MAILBOX_BASE + - MBOX_IDX_SUSPEND_MAGIC * sizeof(uintptr_t), - 2 * sizeof(uintptr_t)); + MBOX_IDX_SUSPEND_MAGIC * sizeof(uintptr_t), + 2 * sizeof(uintptr_t)); #endif /* Flush and disable LLC before going off-power */ llc_disable(0); @@ -636,7 +647,7 @@ static void a8k_pwr_domain_suspend(const psci_power_state_t *target_state) static void a8k_pwr_domain_on_finish(const psci_power_state_t *target_state) { /* arch specific configuration */ - psci_arch_init(0); + marvell_psci_arch_init(0); /* Interrupt initialization */ gicv2_pcpu_distif_init(); @@ -656,11 +667,12 @@ static void a8k_pwr_domain_on_finish(const psci_power_state_t *target_state) * context. Need to implement a separate suspend finisher. ***************************************************************************** */ -static void a8k_pwr_domain_suspend_finish(const psci_power_state_t *target_state) +static void a8k_pwr_domain_suspend_finish( + const psci_power_state_t *target_state) { if (is_pm_fw_running()) { /* arch specific configuration */ - psci_arch_init(0); + marvell_psci_arch_init(0); /* Interrupt initialization */ gicv2_cpuif_enable(); @@ -714,7 +726,7 @@ static void __dead2 a8k_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state) { const struct power_off_method *pm_cfg = - (const struct power_off_method *)plat_get_pm_cfg(); + (const struct power_off_method *)plat_marvell_get_pm_cfg(); unsigned int srcmd; unsigned int sdram_reg; register_t gpio_data = 0, gpio_addr = 0; @@ -782,9 +794,6 @@ static void __dead2 a8k_system_off(void) { ERROR("%s: needs to be implemented\n", __func__); panic(); - wfi(); - ERROR("%s: operation not handled.\n", __func__); - panic(); } void plat_marvell_system_reset(void) diff --git a/plat/marvell/a8k/common/plat_pm_trace.c b/plat/marvell/a8k/common/plat_pm_trace.c index b797f77e..683e56f6 100644 --- a/plat/marvell/a8k/common/plat_pm_trace.c +++ b/plat/marvell/a8k/common/plat_pm_trace.c @@ -1,9 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #include <mmio.h> #include <mss_mem.h> #include <platform.h> diff --git a/plat/marvell/a8k/common/plat_thermal.c b/plat/marvell/a8k/common/plat_thermal.c index fe6de66b..02fe8209 100644 --- a/plat/marvell/a8k/common/plat_thermal.c +++ b/plat/marvell/a8k/common/plat_thermal.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2017 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses @@ -8,22 +8,27 @@ #include <debug.h> #include <delay_timer.h> #include <mmio.h> -#include <plat_def.h> +#include <mvebu_def.h> #include <thermal.h> #define THERMAL_TIMEOUT 1200 #define THERMAL_SEN_CTRL_LSB_STRT_OFFSET 0 -#define THERMAL_SEN_CTRL_LSB_STRT_MASK (0x1 << THERMAL_SEN_CTRL_LSB_STRT_OFFSET) +#define THERMAL_SEN_CTRL_LSB_STRT_MASK \ + (0x1 << THERMAL_SEN_CTRL_LSB_STRT_OFFSET) #define THERMAL_SEN_CTRL_LSB_RST_OFFSET 1 -#define THERMAL_SEN_CTRL_LSB_RST_MASK (0x1 << THERMAL_SEN_CTRL_LSB_RST_OFFSET) +#define THERMAL_SEN_CTRL_LSB_RST_MASK \ + (0x1 << THERMAL_SEN_CTRL_LSB_RST_OFFSET) #define THERMAL_SEN_CTRL_LSB_EN_OFFSET 2 -#define THERMAL_SEN_CTRL_LSB_EN_MASK (0x1 << THERMAL_SEN_CTRL_LSB_EN_OFFSET) +#define THERMAL_SEN_CTRL_LSB_EN_MASK \ + (0x1 << THERMAL_SEN_CTRL_LSB_EN_OFFSET) #define THERMAL_SEN_CTRL_STATS_VALID_OFFSET 16 -#define THERMAL_SEN_CTRL_STATS_VALID_MASK (0x1 << THERMAL_SEN_CTRL_STATS_VALID_OFFSET) +#define THERMAL_SEN_CTRL_STATS_VALID_MASK \ + (0x1 << THERMAL_SEN_CTRL_STATS_VALID_OFFSET) #define THERMAL_SEN_CTRL_STATS_TEMP_OUT_OFFSET 0 -#define THERMAL_SEN_CTRL_STATS_TEMP_OUT_MASK (0x3FF << THERMAL_SEN_CTRL_STATS_TEMP_OUT_OFFSET) +#define THERMAL_SEN_CTRL_STATS_TEMP_OUT_MASK \ + (0x3FF << THERMAL_SEN_CTRL_STATS_TEMP_OUT_OFFSET) #define THERMAL_SEN_OUTPUT_MSB 512 #define THERMAL_SEN_OUTPUT_COMP 1024 @@ -55,7 +60,8 @@ static int ext_tsen_probe(struct tsen_config *tsen_cfg) mmio_write_32((uintptr_t)&base->ext_tsen_ctrl_lsb, reg); reg = mmio_read_32((uintptr_t)&base->ext_tsen_status); - while ((reg & THERMAL_SEN_CTRL_STATS_VALID_MASK) == 0 && timeout < THERMAL_TIMEOUT) { + while ((reg & THERMAL_SEN_CTRL_STATS_VALID_MASK) == 0 && + timeout < THERMAL_TIMEOUT) { udelay(100); reg = mmio_read_32((uintptr_t)&base->ext_tsen_status); timeout++; @@ -68,7 +74,7 @@ static int ext_tsen_probe(struct tsen_config *tsen_cfg) tsen_cfg->tsen_ready = 1; - INFO("thermal sensor was initialized\n"); + VERBOSE("thermal sensor was initialized\n"); return 0; } @@ -85,7 +91,8 @@ static int ext_tsen_read(struct tsen_config *tsen_cfg, int *temp) base = (struct tsen_regs *)tsen_cfg->regs_base; reg = mmio_read_32((uintptr_t)&base->ext_tsen_status); - reg = ((reg & THERMAL_SEN_CTRL_STATS_TEMP_OUT_MASK) >> THERMAL_SEN_CTRL_STATS_TEMP_OUT_OFFSET); + reg = ((reg & THERMAL_SEN_CTRL_STATS_TEMP_OUT_MASK) >> + THERMAL_SEN_CTRL_STATS_TEMP_OUT_OFFSET); /* * TSEN output format is signed as a 2s complement number |