diff options
Diffstat (limited to 'plat')
| -rw-r--r-- | plat/marvell/a8k/common/a8k_common.mk | 12 | ||||
| -rw-r--r-- | plat/marvell/a8k/common/plat_ble_setup.c | 23 |
2 files changed, 10 insertions, 25 deletions
diff --git a/plat/marvell/a8k/common/a8k_common.mk b/plat/marvell/a8k/common/a8k_common.mk index b9df51c9..c5224b2c 100644 --- a/plat/marvell/a8k/common/a8k_common.mk +++ b/plat/marvell/a8k/common/a8k_common.mk @@ -62,12 +62,14 @@ PLAT_BL_COMMON_SOURCES := $(PLAT_COMMON_BASE)/aarch64/a8k_common.c \ BLE_PORTING_SOURCES := $(PLAT_FAMILY_BASE)/$(PLAT)/board/dram_port.c \ $(PLAT_FAMILY_BASE)/$(PLAT)/board/marvell_plat_config.c -BLE_SOURCES := plat/marvell/common/sys_info.c \ - plat/marvell/a8k/common/plat_ble_setup.c \ - $(MARVELL_DRV_BASE)/mochi/cp110_setup.c \ - $(MARVELL_DRV_BASE)/i2c/a8k_i2c.c \ - $(PLAT_COMMON_BASE)/plat_pm.c \ +BLE_SOURCES := plat/marvell/common/sys_info.c \ + plat/marvell/a8k/common/plat_ble_setup.c \ + $(MARVELL_DRV_BASE)/mochi/cp110_setup.c \ + $(MARVELL_DRV_BASE)/i2c/a8k_i2c.c \ + $(PLAT_COMMON_BASE)/plat_pm.c \ + $(MARVELL_DRV_BASE)/aro.c \ $(BLE_PORTING_SOURCES) + ifeq (${PCI_EP_SUPPORT}, 1) BLE_SOURCES += plat/marvell/common/pci_ep_setup.c \ $(MARVELL_DRV_BASE)/dw-pcie-ep.c \ diff --git a/plat/marvell/a8k/common/plat_ble_setup.c b/plat/marvell/a8k/common/plat_ble_setup.c index 8815051a..7203a11d 100644 --- a/plat/marvell/a8k/common/plat_ble_setup.c +++ b/plat/marvell/a8k/common/plat_ble_setup.c @@ -39,6 +39,7 @@ #include <sys_info.h> #include <dram_if.h> #include <ccu.h> +#include <aro.h> #include <rfu.h> #include <apn806_setup.h> #include <cp110_setup.h> @@ -143,26 +144,6 @@ #define EFUSE_SVC_REVISION_ID_0 0x8 #define EFUSE_SVC_BIN_PREMIUM 0x1 -enum cpu_clock_freq_mode { - CPU_2000_DDR_1200_RCLK_1200 = 0x0, - CPU_2000_DDR_1050_RCLK_1050 = 0x1, - CPU_1600_DDR_800_RCLK_800 = 0x4, - CPU_1800_DDR_1200_RCLK_1200 = 0x6, - CPU_1800_DDR_1050_RCLK_1050 = 0x7, - CPU_1600_DDR_900_RCLK_900 = 0x0B, - CPU_1600_DDR_1050_RCLK_1050 = 0x0D, - CPU_1600_DDR_900_RCLK_900_2 = 0x0E, - CPU_1000_DDR_650_RCLK_650 = 0x13, - CPU_1300_DDR_800_RCLK_800 = 0x14, - CPU_1300_DDR_650_RCLK_650 = 0x17, - CPU_1200_DDR_800_RCLK_800 = 0x19, - CPU_1400_DDR_800_RCLK_800 = 0x1a, - CPU_600_DDR_800_RCLK_800 = 0x1B, - CPU_800_DDR_800_RCLK_800 = 0x1C, - CPU_1000_DDR_800_RCLK_800 = 0x1D, - CPU_DDR_RCLK_INVALID -}; - /* Notify bootloader on DRAM setup */ void pass_dram_sys_info(struct dram_config *cfg) { @@ -504,6 +485,8 @@ int ble_plat_setup(int *skip) /* Setup AVS */ ble_plat_svc_config(); + init_aro(); + /* Get dram data from platform */ cfg = (struct dram_config *)plat_get_dram_data(); |