diff options
Diffstat (limited to 'plat')
113 files changed, 1231 insertions, 1099 deletions
diff --git a/plat/marvell/a3700/a3700/board/pm_src.c b/plat/marvell/a3700/a3700/board/pm_src.c index 1c4958c6..bc48ce8c 100644 --- a/plat/marvell/a3700/a3700/board/pm_src.c +++ b/plat/marvell/a3700/a3700/board/pm_src.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses diff --git a/plat/marvell/a3700/a3700/plat_def.h b/plat/marvell/a3700/a3700/mvebu_def.h index 6a1ff0fa..c58f06bb 100644 --- a/plat/marvell/a3700/a3700/plat_def.h +++ b/plat/marvell/a3700/a3700/mvebu_def.h @@ -1,9 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * - * SPDX-License-Identifier: BSD-3-Clause + * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #ifndef __MVEBU_DEF_H__ #define __MVEBU_DEF_H__ diff --git a/plat/marvell/a3700/a3700/plat_bl31_setup.c b/plat/marvell/a3700/a3700/plat_bl31_setup.c index 1e813f32..a37af930 100644 --- a/plat/marvell/a3700/a3700/plat_bl31_setup.c +++ b/plat/marvell/a3700/a3700/plat_bl31_setup.c @@ -1,16 +1,17 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #include <a3700_dram_cs.h> +#include <armada_common.h> #include <dram_win.h> #include <io_addr_dec.h> #include <mmio.h> -#include <plat_config.h> +#include <marvell_plat_priv.h> #include <plat_marvell.h> -#include <plat_private.h> #include <sys_info.h> /* This function passes DRAM cpu decode window information in ATF to sys info */ @@ -47,7 +48,8 @@ static void marvell_bl31_mpp_init(void) * And anyway, this bit value should be 1 in all modes, * so here we does not judge boot mode and set this bit to 1 always. */ - mmio_setbits_32(MVEBU_NB_GPIO_OUTPUT_EN_HIGH_REG, 1 << MVEBU_GPIO_NB_SPI_PIN_MODE_OFF); + mmio_setbits_32(MVEBU_NB_GPIO_OUTPUT_EN_HIGH_REG, + 1 << MVEBU_GPIO_NB_SPI_PIN_MODE_OFF); } /* This function overruns the same function in marvell_bl31_setup.c */ diff --git a/plat/marvell/a3700/a3700/platform.mk b/plat/marvell/a3700/a3700/platform.mk index d2316f67..4f7ac08c 100644 --- a/plat/marvell/a3700/a3700/platform.mk +++ b/plat/marvell/a3700/a3700/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (C) 2016 - 2018 Marvell International Ltd. +# Copyright (C) 2018 Marvell International Ltd. # # SPDX-License-Identifier: BSD-3-Clause # https://spdx.org/licenses diff --git a/plat/marvell/a3700/common/a3700_common.mk b/plat/marvell/a3700/common/a3700_common.mk index d963284a..54f8bdaa 100644 --- a/plat/marvell/a3700/common/a3700_common.mk +++ b/plat/marvell/a3700/common/a3700_common.mk @@ -1,5 +1,5 @@ # -# Copyright (C) 2016 Marvell International Ltd. +# Copyright (C) 2018 Marvell International Ltd. # # SPDX-License-Identifier: BSD-3-Clause # https://spdx.org/licenses @@ -36,16 +36,19 @@ endif #MARVELL_SECURE_BOOT TIMBUILD := $(DOIMAGEPATH)/script/buildtim.sh TIM2IMG := $(DOIMAGEPATH)/script/tim2img.pl -# WTMI_IMG is used to specify the customized RTOS image runing over CM3 processor. By default, it -# points to a baremetal binary of fuse programming in A3700_utils. +# WTMI_IMG is used to specify the customized RTOS image runing over +# Service CPU (CM3 processor). By the default, it points to a +# baremetal binary of fuse programming in A3700_utils. WTMI_IMG := $(DOIMAGEPATH)/wtmi/fuse/build/fuse.bin -# WTMI_SYSINIT_IMG is used for the system early initialization, such as AVS settings, clock-tree -# setup and dynamic DDR PHY training. After the initialization is done, this image will be wiped out +# WTMI_SYSINIT_IMG is used for the system early initialization, +# such as AVS settings, clock-tree setup and dynamic DDR PHY training. +# After the initialization is done, this image will be wiped out # from the memory and CM3 will continue with RTOS image or other application. WTMI_SYSINIT_IMG := $(DOIMAGEPATH)/wtmi/sys_init/build/sys_init.bin -# WTMI_MULTI_IMG is composed of CM3 RTOS image (WTMI_IMG) and sys-init image (WTMI_SYSINIT_IMG). +# WTMI_MULTI_IMG is composed of CM3 RTOS image (WTMI_IMG) +# and sys-init image (WTMI_SYSINIT_IMG). WTMI_MULTI_IMG := $(DOIMAGEPATH)/wtmi/build/wtmi.bin WTMI_ENC_IMG := $(DOIMAGEPATH)/wtmi/build/wtmi-enc.bin @@ -84,31 +87,31 @@ MARVELL_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \ ATF_INCLUDES := -Iinclude/common/tbbr \ -Iinclude/drivers -PLAT_INCLUDES := -I$(PLAT_FAMILY_BASE)/$(PLAT) \ - -I$(PLAT_COMMON_BASE)/include \ - -I$(PLAT_INCLUDE_BASE)/common \ - -I$(MARVELL_DRV_BASE)/uart \ - -I$/drivers/arm/gic/common/ \ +PLAT_INCLUDES := -I$(PLAT_FAMILY_BASE)/$(PLAT) \ + -I$(PLAT_COMMON_BASE)/include \ + -I$(PLAT_INCLUDE_BASE)/common \ + -I$(MARVELL_DRV_BASE)/uart \ + -I$/drivers/arm/gic/common/ \ $(ATF_INCLUDES) -PLAT_BL_COMMON_SOURCES := $(PLAT_COMMON_BASE)/aarch64/a3700_common.c \ - drivers/console/aarch64/console.S \ - plat/marvell/common/marvell_cci.c \ +PLAT_BL_COMMON_SOURCES := $(PLAT_COMMON_BASE)/aarch64/a3700_common.c \ + drivers/console/aarch64/console.S \ + plat/marvell/common/marvell_cci.c \ $(MARVELL_DRV_BASE)/uart/a3700_console.S -BL1_SOURCES += $(PLAT_COMMON_BASE)/aarch64/plat_helpers.S \ +BL1_SOURCES += $(PLAT_COMMON_BASE)/aarch64/plat_helpers.S \ lib/cpus/aarch64/cortex_a53.S BL31_PORTING_SOURCES := $(PLAT_FAMILY_BASE)/$(PLAT)/board/pm_src.c BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \ - $(PLAT_COMMON_BASE)/aarch64/plat_helpers.S \ + $(PLAT_COMMON_BASE)/aarch64/plat_helpers.S \ $(PLAT_COMMON_BASE)/plat_pm.c \ $(PLAT_COMMON_BASE)/a3700_dram_cs.c \ $(PLAT_COMMON_BASE)/dram_win.c \ $(PLAT_COMMON_BASE)/io_addr_dec.c \ - $(PLAT_COMMON_BASE)/marvell_plat_config.c \ - $(PLAT_FAMILY_BASE)/$(PLAT)/plat_bl31_setup.c \ + $(PLAT_COMMON_BASE)/marvell_plat_config.c \ + $(PLAT_FAMILY_BASE)/$(PLAT)/plat_bl31_setup.c \ plat/marvell/common/sys_info.c \ plat/marvell/common/marvell_gicv3.c \ $(MARVELL_GIC_SOURCES) \ @@ -154,11 +157,13 @@ ifeq ($(MARVELL_SECURE_BOOT),1) @echo -e "\t Secure boot. Encrypting wtmi and boot-image \n"; @echo -e "\t=======================================================\n"; @truncate -s %16 $(WTMI_MULTI_IMG) - @openssl enc -aes-256-cbc -e -in $(WTMI_MULTI_IMG) -out $(WTMI_ENC_IMG) \ + @openssl enc -aes-256-cbc -e -in $(WTMI_MULTI_IMG) \ + -out $(WTMI_ENC_IMG) \ -K `cat $(IMAGESPATH)/aes-256.txt` -k 0 -nosalt \ -iv `cat $(IMAGESPATH)/iv.txt` -p @truncate -s %16 $(BUILD_PLAT)/$(BOOT_IMAGE); - @openssl enc -aes-256-cbc -e -in $(BUILD_PLAT)/$(BOOT_IMAGE) -out $(BUILD_PLAT)/$(BOOT_ENC_IMAGE) \ + @openssl enc -aes-256-cbc -e -in $(BUILD_PLAT)/$(BOOT_IMAGE) \ + -out $(BUILD_PLAT)/$(BOOT_ENC_IMAGE) \ -K `cat $(IMAGESPATH)/aes-256.txt` -k 0 -nosalt \ -iv `cat $(IMAGESPATH)/iv.txt` -p endif diff --git a/plat/marvell/a3700/common/a3700_dram_cs.c b/plat/marvell/a3700/common/a3700_dram_cs.c index 400eea06..d894f1d5 100644 --- a/plat/marvell/a3700/common/a3700_dram_cs.c +++ b/plat/marvell/a3700/common/a3700_dram_cs.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses @@ -76,13 +76,18 @@ static struct dram_cs_addr_len_to_size dram_cs_addr_len_to_size_map[] = { {0x1A, TB_2_MB(4) } }; -static int marvell_dram_cs_get_size_by_addr_len(uint32_t addr_len_value, uint32_t *size_mbytes) +static int marvell_dram_cs_get_size_by_addr_len(uint32_t addr_len_value, + uint32_t *size_mbytes) { int i; - for (i = 0; i < sizeof(dram_cs_addr_len_to_size_map)/sizeof(struct dram_cs_addr_len_to_size); i++) { - if (dram_cs_addr_len_to_size_map[i].addr_len_value == addr_len_value) { - *size_mbytes = dram_cs_addr_len_to_size_map[i].size_mbytes; + for (i = 0; i < sizeof(dram_cs_addr_len_to_size_map)/ + sizeof(struct dram_cs_addr_len_to_size); i++) { + + if (dram_cs_addr_len_to_size_map[i].addr_len_value == + addr_len_value) { + *size_mbytes = + dram_cs_addr_len_to_size_map[i].size_mbytes; return 0; } } @@ -121,9 +126,11 @@ int marvell_get_dram_cs_base_size(uint32_t cs_num, if (!(cs_mmap_reg & MVEBU_CS_MMAP_ENABLE)) return -ENODEV; - *base_low = (cs_mmap_reg & MVEBU_CS_MMAP_START_ADDR_LOW_MASK) >> MVEBU_CS_MMAP_START_ADDR_LOW_OFFS; + *base_low = (cs_mmap_reg & MVEBU_CS_MMAP_START_ADDR_LOW_MASK) >> + MVEBU_CS_MMAP_START_ADDR_LOW_OFFS; *base_high = mmio_read_32(MVEBU_CS_MMAP_HIGH(cs_num)); - area_len = (cs_mmap_reg & MVEBU_CS_MMAP_AREA_LEN_MASK) >> MVEBU_CS_MMAP_AREA_LEN_OFFS; + area_len = (cs_mmap_reg & MVEBU_CS_MMAP_AREA_LEN_MASK) >> + MVEBU_CS_MMAP_AREA_LEN_OFFS; if (marvell_dram_cs_get_size_by_addr_len(area_len, size_mbytes)) return -EFAULT; diff --git a/plat/marvell/a3700/common/aarch64/a3700_common.c b/plat/marvell/a3700/common/aarch64/a3700_common.c index 07a3a2f6..e7840094 100644 --- a/plat/marvell/a3700/common/aarch64/a3700_common.c +++ b/plat/marvell/a3700/common/aarch64/a3700_common.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses diff --git a/plat/marvell/a3700/common/aarch64/plat_helpers.S b/plat/marvell/a3700/common/aarch64/plat_helpers.S index 9da72ad3..c132dcdd 100644 --- a/plat/marvell/a3700/common/aarch64/plat_helpers.S +++ b/plat/marvell/a3700/common/aarch64/plat_helpers.S @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses @@ -27,7 +27,7 @@ endfunc plat_secondary_cold_boot_setup /* --------------------------------------------------------------------- * unsigned long plat_get_my_entrypoint (void); * - * Main job of this routine is to distinguish between a cold and warm boot + * Main job of this routine is to distinguish between cold and warm boot * For a cold boot, return 0. * For a warm boot, read the mailbox and return the address it contains. * A magic number is placed before entrypoint to avoid mistake caused by @@ -35,16 +35,19 @@ endfunc plat_secondary_cold_boot_setup * --------------------------------------------------------------------- */ func plat_get_my_entrypoint - mov_imm x0, PLAT_MARVELL_MAILBOX_BASE /* Read first word and compare it with magic num */ - ldr x1, [x0] + /* Read first word and compare it with magic num */ + mov_imm x0, PLAT_MARVELL_MAILBOX_BASE + ldr x1, [x0] mov_imm x2, PLAT_MARVELL_MAILBOX_MAGIC_NUM - cmp x1, x2 - beq entrypoint /* If compare failed, return 0, i.e. cold boot */ - mov x0, #0 + cmp x1, x2 + /* If compare failed, return 0, i.e. cold boot */ + beq entrypoint + mov x0, #0 ret entrypoint: - add x0, x0, #8 /* Second word contains the jump address */ - ldr x0, [x0] + /* Second word contains the jump address */ + add x0, x0, #8 + ldr x0, [x0] ret endfunc plat_get_my_entrypoint diff --git a/plat/marvell/a3700/common/dram_win.c b/plat/marvell/a3700/common/dram_win.c index e623362e..3ffc98cd 100644 --- a/plat/marvell/a3700/common/dram_win.c +++ b/plat/marvell/a3700/common/dram_win.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses @@ -134,7 +134,8 @@ void dram_win_map_build(struct dram_win_map *win_map) memset(win_map, 0, sizeof(struct dram_win_map)); for (win_id = 0; win_id < DRAM_WIN_MAP_NUM_MAX; win_id++) { ctrl_reg = mmio_read_32(CPU_DEC_WIN_CTRL_REG(win_id)); - target = (ctrl_reg & CPU_DEC_CR_WIN_TARGET_MASK) >> CPU_DEC_CR_WIN_TARGET_OFFS; + target = (ctrl_reg & CPU_DEC_CR_WIN_TARGET_MASK) >> + CPU_DEC_CR_WIN_TARGET_OFFS; enabled = ctrl_reg & CPU_DEC_CR_WIN_ENABLE; /* Ignore invalid and non-dram windows*/ if ((enabled == 0) || (target != DRAM_CPU_DEC_TARGET_NUM)) @@ -144,15 +145,19 @@ void dram_win_map_build(struct dram_win_map *win_map) base_reg = mmio_read_32(CPU_DEC_WIN_BASE_REG(win_id)); size_reg = mmio_read_32(CPU_DEC_WIN_SIZE_REG(win_id)); /* Base reg [15:0] corresponds to transaction address [39:16] */ - win->base_addr = (base_reg & CPU_DEC_BR_BASE_MASK) >> CPU_DEC_BR_BASE_OFFS; + win->base_addr = (base_reg & CPU_DEC_BR_BASE_MASK) >> + CPU_DEC_BR_BASE_OFFS; win->base_addr *= CPU_DEC_CR_WIN_SIZE_ALIGNMENT; /* - * Size reg [15:0] is programmed from LSB to MSB as a sequence of 1s followed by a sequence of 0s, - * and the number of 1s specifies the size of the window in 64 KB granularity, + * Size reg [15:0] is programmed from LSB to MSB as a sequence + * of 1s followed by a sequence of 0s and the number of 1s + * specifies the size of the window in 64 KB granularity, * for example, a value of 00FFh specifies 256 x 64 KB = 16 MB */ - win->win_size = (size_reg & CPU_DEC_CR_WIN_SIZE_MASK) >> CPU_DEC_CR_WIN_SIZE_OFFS; - win->win_size = (win->win_size + 1) * CPU_DEC_CR_WIN_SIZE_ALIGNMENT; + win->win_size = (size_reg & CPU_DEC_CR_WIN_SIZE_MASK) >> + CPU_DEC_CR_WIN_SIZE_OFFS; + win->win_size = (win->win_size + 1) * + CPU_DEC_CR_WIN_SIZE_ALIGNMENT; win_map->dram_win_num++; } @@ -174,13 +179,17 @@ static void cpu_win_set(uint32_t win_id, struct cpu_win_configuration *win_cfg) return; /* Set Base Register */ - base_reg = (uint32_t)(win_cfg->base_addr / CPU_DEC_CR_WIN_SIZE_ALIGNMENT); + base_reg = (uint32_t)(win_cfg->base_addr / + CPU_DEC_CR_WIN_SIZE_ALIGNMENT); base_reg <<= CPU_DEC_BR_BASE_OFFS; base_reg &= CPU_DEC_BR_BASE_MASK; mmio_write_32(CPU_DEC_WIN_BASE_REG(win_id), base_reg); - /* Set Remap Register with the same value as the <Base> field in Base Register */ - remap_reg = (uint32_t)(win_cfg->remap_addr / CPU_DEC_CR_WIN_SIZE_ALIGNMENT); + /* Set Remap Register with the same value + * as the <Base> field in Base Register + */ + remap_reg = (uint32_t)(win_cfg->remap_addr / + CPU_DEC_CR_WIN_SIZE_ALIGNMENT); remap_reg <<= CPU_DEC_RLR_REMAP_LOW_OFFS; remap_reg &= CPU_DEC_RLR_REMAP_LOW_MASK; mmio_write_32(CPU_DEC_REMAP_LOW_REG(win_id), remap_reg); @@ -200,10 +209,12 @@ static void cpu_win_set(uint32_t win_id, struct cpu_win_configuration *win_cfg) void cpu_wins_init(void) { - uint32_t cfg_idx, win_id, cs_id, base_low, base_high, size_mbytes, total_mbytes = 0; + uint32_t cfg_idx, win_id, cs_id; + uint32_t base_low, base_high, size_mbytes, total_mbytes = 0; for (cs_id = 0; cs_id < MVEBU_MAX_CS_MMAP_NUM; cs_id++) - if (!marvell_get_dram_cs_base_size(cs_id, &base_low, &base_high, &size_mbytes)) + if (!marvell_get_dram_cs_base_size(cs_id, &base_low, + &base_high, &size_mbytes)) total_mbytes += size_mbytes; if (total_mbytes <= 2048) @@ -211,7 +222,9 @@ void cpu_wins_init(void) else cfg_idx = CPU_WIN_CONFIG_DRAM_4GB; - /* Window 0 is configured always for DRAM in tim header already, no need to configure it again here */ + /* Window 0 is configured always for DRAM in tim header + * already, no need to configure it again here + */ for (win_id = 1; win_id < MV_CPU_WIN_NUM; win_id++) cpu_win_set(win_id, &mv_cpu_wins[cfg_idx][win_id]); } diff --git a/plat/marvell/a3700/common/include/a3700_dram_cs.h b/plat/marvell/a3700/common/include/a3700_dram_cs.h index 6a9edaf4..4ce64dec 100644 --- a/plat/marvell/a3700/common/include/a3700_dram_cs.h +++ b/plat/marvell/a3700/common/include/a3700_dram_cs.h @@ -1,9 +1,10 @@ /* - * Copyright (C) 2016 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #ifndef __MVEBU_A3700_DRAM_CS_H__ #define __MVEBU_A3700_DRAM_CS_H__ diff --git a/plat/marvell/a3700/common/include/a3700_plat_def.h b/plat/marvell/a3700/common/include/a3700_plat_def.h index 05c71351..e145c532 100644 --- a/plat/marvell/a3700/common/include/a3700_plat_def.h +++ b/plat/marvell/a3700/common/include/a3700_plat_def.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses diff --git a/plat/marvell/a3700/common/include/a3700_pm.h b/plat/marvell/a3700/common/include/a3700_pm.h index 3ab7c736..a3dac274 100644 --- a/plat/marvell/a3700/common/include/a3700_pm.h +++ b/plat/marvell/a3700/common/include/a3700_pm.h @@ -4,6 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #ifndef __MVEBU_A3700_PM_H__ #define __MVEBU_A3700_PM_H__ diff --git a/plat/marvell/a3700/common/include/dram_win.h b/plat/marvell/a3700/common/include/dram_win.h index 8191b298..4537f916 100644 --- a/plat/marvell/a3700/common/include/dram_win.h +++ b/plat/marvell/a3700/common/include/dram_win.h @@ -1,9 +1,10 @@ /* - * Copyright (C) 2016 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #ifndef _DRAM_WIN_H_ #define _DRAM_WIN_H_ diff --git a/plat/marvell/a3700/common/include/io_addr_dec.h b/plat/marvell/a3700/common/include/io_addr_dec.h index d77e9c18..2e4183cd 100644 --- a/plat/marvell/a3700/common/include/io_addr_dec.h +++ b/plat/marvell/a3700/common/include/io_addr_dec.h @@ -1,9 +1,10 @@ /* - * Copyright (C) 2016 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #ifndef _IO_ADDR_DEC_H_ #define _IO_ADDR_DEC_H_ @@ -23,10 +24,15 @@ */ struct dec_win_config { uint32_t dec_reg_base; /* IO address decoder register base address */ - uint32_t win_attr; /* IO address decoder windows attributes */ - uint32_t max_dram_win; /* How many configurable dram decoder windows that this unit has; */ - uint32_t max_remap; /* The decoder windows number including remapping that this unit has */ - uint32_t win_offset; /* The offset between continuous decode windows within the same unit, typically 0x10 */ + uint32_t win_attr; /* IO address decoder windows attributes */ + /* How many configurable dram decoder windows that this unit has; */ + uint32_t max_dram_win; + /* The decoder windows number including remapping that this unit has */ + uint32_t max_remap; + /* The offset between continuous decode windows + * within the same unit, typically 0x10 + */ + uint32_t win_offset; }; struct dram_win { @@ -53,7 +59,9 @@ struct dram_win_map { * * @return: 0 on success and others on failure */ -int init_io_addr_dec(struct dram_win_map *dram_wins_map, struct dec_win_config *io_dec_config, uint32_t io_unit_num); +int init_io_addr_dec(struct dram_win_map *dram_wins_map, + struct dec_win_config *io_dec_config, + uint32_t io_unit_num); #endif /* _IO_ADDR_DEC_H_ */ diff --git a/plat/marvell/a3700/common/include/plat_macros.S b/plat/marvell/a3700/common/include/plat_macros.S index af084882..12f0d6f9 100644 --- a/plat/marvell/a3700/common/include/plat_macros.S +++ b/plat/marvell/a3700/common/include/plat_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses diff --git a/plat/marvell/a3700/common/include/platform_def.h b/plat/marvell/a3700/common/include/platform_def.h index 9e90e0dc..7da1fa14 100644 --- a/plat/marvell/a3700/common/include/platform_def.h +++ b/plat/marvell/a3700/common/include/platform_def.h @@ -8,7 +8,7 @@ #define __PLATFORM_DEF_H__ #include <board_marvell_def.h> -#include <plat_def.h> +#include <mvebu_def.h> #ifndef __ASSEMBLY__ #include <stdio.h> #endif /* __ASSEMBLY__ */ @@ -94,9 +94,9 @@ Trusted SRAM section 0x4000000..0x4200000: #define PLAT_MARVELL_CPU_ENTRY_ADDR BL1_RO_BASE /* GIC related definitions */ -#define PLAT_MARVELL_GICD_BASE (MVEBU_REGS_BASE + MVEBU_GICD_BASE) -#define PLAT_MARVELL_GICR_BASE (MVEBU_REGS_BASE + MVEBU_GICR_BASE) -#define PLAT_MARVELL_GICC_BASE (MVEBU_REGS_BASE + MVEBU_GICC_BASE) +#define PLAT_MARVELL_GICD_BASE (MVEBU_REGS_BASE + MVEBU_GICD_BASE) +#define PLAT_MARVELL_GICR_BASE (MVEBU_REGS_BASE + MVEBU_GICR_BASE) +#define PLAT_MARVELL_GICC_BASE (MVEBU_REGS_BASE + MVEBU_GICC_BASE) #define PLAT_MARVELL_G0_IRQ_PROPS(grp) \ INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \ diff --git a/plat/marvell/a3700/common/io_addr_dec.c b/plat/marvell/a3700/common/io_addr_dec.c index e40fac97..c1c404aa 100644 --- a/plat/marvell/a3700/common/io_addr_dec.c +++ b/plat/marvell/a3700/common/io_addr_dec.c @@ -9,9 +9,12 @@ #include <mmio.h> #include <io_addr_dec.h> -#define MVEBU_DEC_WIN_CTRL_REG(base, win, off) (MVEBU_REGS_BASE + base + (win * off)) -#define MVEBU_DEC_WIN_BASE_REG(base, win, off) (MVEBU_REGS_BASE + base + (win * off) + 0x4) -#define MVEBU_DEC_WIN_REMAP_REG(base, win, off) (MVEBU_REGS_BASE + base + (win * off) + 0x8) +#define MVEBU_DEC_WIN_CTRL_REG(base, win, off) (MVEBU_REGS_BASE + base + \ + (win * off)) +#define MVEBU_DEC_WIN_BASE_REG(base, win, off) (MVEBU_REGS_BASE + base + \ + (win * off) + 0x4) +#define MVEBU_DEC_WIN_REMAP_REG(base, win, off) (MVEBU_REGS_BASE + base + \ + (win * off) + 0x8) #define MVEBU_DEC_WIN_CTRL_SIZE_OFF (16) #define MVEBU_DEC_WIN_ENABLE (0x1) @@ -22,65 +25,81 @@ #define MVEBU_WIN_BASE_SIZE_ALIGNMENT (0x10000) -/* There are up to 14 IO unit which need address deocode in Armada-3700 */ +/* There are up to 14 IO unit which need address decode in Armada-3700 */ #define IO_UNIT_NUM_MAX (14) #define MVEBU_MAX_ADDRSS_4GB (0x100000000ULL) -static void set_io_addr_dec_win(int win_id, uintptr_t base_addr, uintptr_t win_size, struct dec_win_config *dec_win) +static void set_io_addr_dec_win(int win_id, uintptr_t base_addr, + uintptr_t win_size, + struct dec_win_config *dec_win) { uint32_t ctrl = 0; uint32_t base = 0; /* set size */ - ctrl = ((win_size / MVEBU_WIN_BASE_SIZE_ALIGNMENT) - 1) << MVEBU_DEC_WIN_CTRL_SIZE_OFF; + ctrl = ((win_size / MVEBU_WIN_BASE_SIZE_ALIGNMENT) - 1) << + MVEBU_DEC_WIN_CTRL_SIZE_OFF; /* set attr according to IO decode window */ ctrl |= dec_win->win_attr << MVEBU_DEC_WIN_CTRL_ATTR_OFF; /* set target */ ctrl |= DRAM_CPU_DEC_TARGET_NUM << MVEBU_DEC_WIN_CTRL_TARGET_OFF; /* set base */ - base = (base_addr / MVEBU_WIN_BASE_SIZE_ALIGNMENT) << MVEBU_DEC_WIN_BASE_OFF; + base = (base_addr / MVEBU_WIN_BASE_SIZE_ALIGNMENT) << + MVEBU_DEC_WIN_BASE_OFF; /* set base address*/ - mmio_write_32(MVEBU_DEC_WIN_BASE_REG(dec_win->dec_reg_base, win_id, dec_win->win_offset), base); + mmio_write_32(MVEBU_DEC_WIN_BASE_REG(dec_win->dec_reg_base, + win_id, dec_win->win_offset), + base); /* set remap window, some unit does not have remap window */ if (win_id < dec_win->max_remap) - mmio_write_32(MVEBU_DEC_WIN_REMAP_REG(dec_win->dec_reg_base, win_id, dec_win->win_offset), base); + mmio_write_32(MVEBU_DEC_WIN_REMAP_REG(dec_win->dec_reg_base, + win_id, dec_win->win_offset), base); /* set control register */ - mmio_write_32(MVEBU_DEC_WIN_CTRL_REG(dec_win->dec_reg_base, win_id, dec_win->win_offset), ctrl); + mmio_write_32(MVEBU_DEC_WIN_CTRL_REG(dec_win->dec_reg_base, + win_id, dec_win->win_offset), ctrl); /* enable the address decode window at last to make it effective */ ctrl |= MVEBU_DEC_WIN_ENABLE << MVEBU_DEC_WIN_CTRL_EN_OFF; - mmio_write_32(MVEBU_DEC_WIN_CTRL_REG(dec_win->dec_reg_base, win_id, dec_win->win_offset), ctrl); + mmio_write_32(MVEBU_DEC_WIN_CTRL_REG(dec_win->dec_reg_base, + win_id, dec_win->win_offset), ctrl); INFO("set_io_addr_dec %d result: ctrl(0x%x) base(0x%x)", - win_id, mmio_read_32(MVEBU_DEC_WIN_CTRL_REG(dec_win->dec_reg_base, win_id, dec_win->win_offset)), - mmio_read_32(MVEBU_DEC_WIN_BASE_REG(dec_win->dec_reg_base, win_id, dec_win->win_offset))); + win_id, mmio_read_32(MVEBU_DEC_WIN_CTRL_REG(dec_win->dec_reg_base, + win_id, dec_win->win_offset)), + mmio_read_32(MVEBU_DEC_WIN_BASE_REG(dec_win->dec_reg_base, + win_id, dec_win->win_offset))); if (win_id < dec_win->max_remap) INFO(" remap(%x)\n", - mmio_read_32(MVEBU_DEC_WIN_REMAP_REG(dec_win->dec_reg_base, win_id, dec_win->win_offset))); + mmio_read_32(MVEBU_DEC_WIN_REMAP_REG(dec_win->dec_reg_base, + win_id, dec_win->win_offset))); else INFO("\n"); } /* Set io decode window */ -static int set_io_addr_dec(struct dram_win_map *win_map, struct dec_win_config *dec_win) +static int set_io_addr_dec(struct dram_win_map *win_map, + struct dec_win_config *dec_win) { struct dram_win *win; int id; /* disable all windows first */ for (id = 0; id < dec_win->max_dram_win; id++) - mmio_write_32(MVEBU_DEC_WIN_CTRL_REG(dec_win->dec_reg_base, id, dec_win->win_offset), 0); + mmio_write_32(MVEBU_DEC_WIN_CTRL_REG(dec_win->dec_reg_base, id, + dec_win->win_offset), 0); - /* configure IO decode windows for DRAM, inheritate DRAM size, base and target from CPU-DRAM - * decode window, and others from hard coded IO decode window settings array. + /* configure IO decode windows for DRAM, inheritate DRAM size, + * base and target from CPU-DRAM decode window and others + * from hard coded IO decode window settings array. */ if (win_map->dram_win_num > dec_win->max_dram_win) { /* - * If cpu dram windows number exceeds the io decode windows max number, - * then fill the first io decode window with base(0) and size(4GB). - */ + * If cpu dram windows number exceeds the io decode windows + * max number, then fill the first io decode window + * with base(0) and size(4GB). + */ set_io_addr_dec_win(0, 0, MVEBU_MAX_ADDRSS_4GB, dec_win); return 0; @@ -108,7 +127,8 @@ static int set_io_addr_dec(struct dram_win_map *win_map, struct dec_win_config * * * @return: 0 on success and others on failure */ -int init_io_addr_dec(struct dram_win_map *dram_wins_map, struct dec_win_config *io_dec_config, uint32_t io_unit_num) +int init_io_addr_dec(struct dram_win_map *dram_wins_map, + struct dec_win_config *io_dec_config, uint32_t io_unit_num) { int32_t index; struct dec_win_config *io_dec_win; @@ -122,7 +142,8 @@ int init_io_addr_dec(struct dram_win_map *dram_wins_map, struct dec_win_config * } if (io_unit_num > IO_UNIT_NUM_MAX) { - ERROR("IO address decoder windows number %d is over max number %d\n", io_unit_num, IO_UNIT_NUM_MAX); + ERROR("IO address decoder windows number %d is over max %d\n", + io_unit_num, IO_UNIT_NUM_MAX); return -1; } @@ -133,7 +154,8 @@ int init_io_addr_dec(struct dram_win_map *dram_wins_map, struct dec_win_config * for (index = 0; index < dram_wins_map->dram_win_num; index++) INFO("DRAM mapping %d base(0x%lx) size(0x%lx)\n", - index, dram_wins_map->dram_windows[index].base_addr, dram_wins_map->dram_windows[index].win_size); + index, dram_wins_map->dram_windows[index].base_addr, + dram_wins_map->dram_windows[index].win_size); /* Set address decode window for each IO */ for (index = 0; index < io_unit_num; index++) { @@ -143,9 +165,11 @@ int init_io_addr_dec(struct dram_win_map *dram_wins_map, struct dec_win_config * ERROR("Failed to set IO address decode\n"); return -1; } - INFO("Set IO decode window successfully, base(0x%x)", io_dec_win->dec_reg_base); + INFO("Set IO decode window successfully, base(0x%x)", + io_dec_win->dec_reg_base); INFO(" win_attr(%x) max_dram_win(%d) max_remap(%d) win_offset(%d)\n", - io_dec_win->win_attr, io_dec_win->max_dram_win, io_dec_win->max_remap, io_dec_win->win_offset); + io_dec_win->win_attr, io_dec_win->max_dram_win, + io_dec_win->max_remap, io_dec_win->win_offset); } return 0; diff --git a/plat/marvell/a3700/common/marvell_plat_config.c b/plat/marvell/a3700/common/marvell_plat_config.c index 8501ad5b..8207658c 100644 --- a/plat/marvell/a3700/common/marvell_plat_config.c +++ b/plat/marvell/a3700/common/marvell_plat_config.c @@ -1,12 +1,12 @@ /* - * Copyright (C) 2016 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -#include <types.h> -#include <plat_def.h> #include <io_addr_dec.h> +#include <mvebu_def.h> +#include <types.h> struct dec_win_config io_dec_win_conf[] = { /* dec_reg_base win_attr max_dram_win max_remap win_offset */ diff --git a/plat/marvell/a3700/common/plat_pm.c b/plat/marvell/a3700/common/plat_pm.c index 06da17e4..13df14a1 100644 --- a/plat/marvell/a3700/common/plat_pm.c +++ b/plat/marvell/a3700/common/plat_pm.c @@ -1,22 +1,23 @@ /* - * Copyright (C) 2016 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + +#include <a3700_pm.h> #include <arch_helpers.h> -#include <plat_marvell.h> -#include <plat_private.h> -#include <plat_def.h> -#include <psci.h> +#include <armada_common.h> #include <debug.h> +#include <dram_win.h> +#include <io_addr_dec.h> #include <mmio.h> #include <mvebu.h> +#include <mvebu_def.h> +#include <marvell_plat_priv.h> #include <platform.h> -#include <a3700_pm.h> -#include <io_addr_dec.h> -#include <plat_config.h> -#include <dram_win.h> +#include <plat_marvell.h> +#include <psci.h> #ifdef USE_CCI #include <cci.h> #endif @@ -39,22 +40,36 @@ /* IRQ register */ #define MVEBU_NB_IRQ_STATUS_1_REG (MVEBU_NB_SB_IRQ_REG_BASE) -#define MVEBU_NB_IRQ_STATUS_2_REG (MVEBU_NB_SB_IRQ_REG_BASE + 0x10) -#define MVEBU_NB_IRQ_MASK_2_REG (MVEBU_NB_SB_IRQ_REG_BASE + 0x18) -#define MVEBU_SB_IRQ_STATUS_1_REG (MVEBU_NB_SB_IRQ_REG_BASE + 0x40) -#define MVEBU_SB_IRQ_STATUS_2_REG (MVEBU_NB_SB_IRQ_REG_BASE + 0x50) -#define MVEBU_NB_GPIO_IRQ_MASK_1_REG (MVEBU_NB_SB_IRQ_REG_BASE + 0xC8) -#define MVEBU_NB_GPIO_IRQ_MASK_2_REG (MVEBU_NB_SB_IRQ_REG_BASE + 0xD8) -#define MVEBU_SB_GPIO_IRQ_MASK_REG (MVEBU_NB_SB_IRQ_REG_BASE + 0xE8) +#define MVEBU_NB_IRQ_STATUS_2_REG (MVEBU_NB_SB_IRQ_REG_BASE + \ + 0x10) +#define MVEBU_NB_IRQ_MASK_2_REG (MVEBU_NB_SB_IRQ_REG_BASE + \ + 0x18) +#define MVEBU_SB_IRQ_STATUS_1_REG (MVEBU_NB_SB_IRQ_REG_BASE + \ + 0x40) +#define MVEBU_SB_IRQ_STATUS_2_REG (MVEBU_NB_SB_IRQ_REG_BASE + \ + 0x50) +#define MVEBU_NB_GPIO_IRQ_MASK_1_REG (MVEBU_NB_SB_IRQ_REG_BASE + \ + 0xC8) +#define MVEBU_NB_GPIO_IRQ_MASK_2_REG (MVEBU_NB_SB_IRQ_REG_BASE + \ + 0xD8) +#define MVEBU_SB_GPIO_IRQ_MASK_REG (MVEBU_NB_SB_IRQ_REG_BASE + \ + 0xE8) #define MVEBU_NB_GPIO_IRQ_EN_LOW_REG (MVEBU_NB_GPIO_IRQ_REG_BASE) -#define MVEBU_NB_GPIO_IRQ_EN_HIGH_REG (MVEBU_NB_GPIO_IRQ_REG_BASE + 0x04) -#define MVEBU_NB_GPIO_IRQ_STATUS_LOW_REG (MVEBU_NB_GPIO_IRQ_REG_BASE + 0x10) -#define MVEBU_NB_GPIO_IRQ_STATUS_HIGH_REG (MVEBU_NB_GPIO_IRQ_REG_BASE + 0x14) -#define MVEBU_NB_GPIO_IRQ_WK_LOW_REG (MVEBU_NB_GPIO_IRQ_REG_BASE + 0x18) -#define MVEBU_NB_GPIO_IRQ_WK_HIGH_REG (MVEBU_NB_GPIO_IRQ_REG_BASE + 0x1C) +#define MVEBU_NB_GPIO_IRQ_EN_HIGH_REG (MVEBU_NB_GPIO_IRQ_REG_BASE + \ + 0x04) +#define MVEBU_NB_GPIO_IRQ_STATUS_LOW_REG (MVEBU_NB_GPIO_IRQ_REG_BASE + \ + 0x10) +#define MVEBU_NB_GPIO_IRQ_STATUS_HIGH_REG (MVEBU_NB_GPIO_IRQ_REG_BASE + \ + 0x14) +#define MVEBU_NB_GPIO_IRQ_WK_LOW_REG (MVEBU_NB_GPIO_IRQ_REG_BASE + \ + 0x18) +#define MVEBU_NB_GPIO_IRQ_WK_HIGH_REG (MVEBU_NB_GPIO_IRQ_REG_BASE + \ + 0x1C) #define MVEBU_SB_GPIO_IRQ_EN_REG (MVEBU_SB_GPIO_IRQ_REG_BASE) -#define MVEBU_SB_GPIO_IRQ_STATUS_REG (MVEBU_SB_GPIO_IRQ_REG_BASE + 0x10) -#define MVEBU_SB_GPIO_IRQ_WK_REG (MVEBU_SB_GPIO_IRQ_REG_BASE + 0x18) +#define MVEBU_SB_GPIO_IRQ_STATUS_REG (MVEBU_SB_GPIO_IRQ_REG_BASE + \ + 0x10) +#define MVEBU_SB_GPIO_IRQ_WK_REG (MVEBU_SB_GPIO_IRQ_REG_BASE + \ + 0x18) /* PMU registers */ #define MVEBU_PM_NB_PWR_CTRL_REG (MVEBU_PMSU_REG_BASE) @@ -177,9 +192,8 @@ struct wake_up_src_func_map { wake_up_src_func func; }; -void psci_arch_init(int die_index) +void marvell_psci_arch_init(int die_index) { - return; } static void a3700_pm_ack_irq(void) @@ -221,7 +235,7 @@ static void a3700_pm_ack_irq(void) ***************************************************************************** */ int a3700_validate_power_state(unsigned int power_state, - psci_power_state_t *req_state) + psci_power_state_t *req_state) { ERROR("a3700_validate_power_state needs to be implemented\n"); panic(); @@ -248,7 +262,8 @@ int a3700_pwr_domain_on(u_register_t mpidr) __asm__ volatile("dsb sy"); /* Set the cpu start address to BL1 entry point */ - mmio_write_32(MVEBU_CPU_1_RESET_VECTOR, PLAT_MARVELL_CPU_ENTRY_ADDR >> 2); + mmio_write_32(MVEBU_CPU_1_RESET_VECTOR, + PLAT_MARVELL_CPU_ENTRY_ADDR >> 2); /* Get the cpu out of reset */ mmio_clrbits_32(MVEBU_CPU_1_RESET_REG, BIT(MVEBU_CPU_1_RESET_BIT)); @@ -282,9 +297,12 @@ void a3700_pwr_domain_off(const psci_power_state_t *target_state) * Enable Core VDD OFF, core is supposed to be powered * off by PMU when WFI command is issued. */ - mmio_setbits_32(MVEBU_PM_CPU_0_PWR_CTRL_REG + 4 * cpu_idx, MVEBU_PM_CORE_PD); + mmio_setbits_32(MVEBU_PM_CPU_0_PWR_CTRL_REG + 4 * cpu_idx, + MVEBU_PM_CORE_PD); - /* Core can not be powered down with pending IRQ, acknowledge all the pending IRQ */ + /* Core can not be powered down with pending IRQ, + * acknowledge all the pending IRQ + */ a3700_pm_ack_irq(); } @@ -294,22 +312,22 @@ static void a3700_set_gen_pwr_off_option(void) mmio_setbits_32(MVEBU_PM_NB_CPU_PWR_CTRL_REG, MVEBU_PM_L2_FLUSH_EN); /* - * North bridge cannot be VDD off (always ON). The NB state machine support low power - * mode by its state machine. - * This bit MUST be set for north bridge power down, e.g., OSC input cutoff(NOT TEST), - * SRAM power down, PMIC, etc. + * North bridge cannot be VDD off (always ON). + * The NB state machine support low power mode by its state machine. + * This bit MUST be set for north bridge power down, e.g., + * OSC input cutoff(NOT TEST), SRAM power down, PMIC, etc. * It is not related to CPU VDD OFF!! */ mmio_clrbits_32(MVEBU_PM_NB_PWR_OPTION_REG, MVEBU_PM_CPU_VDDV_OFF_EN); /* * MUST: Switch CPU/AXI clock to OSC - * NB state machine clock is always connected to OSC (slow clock). But Core0/1/processor - * state machine's clock are connected to AXI clock. Now, AXI clock takes the - * TBG as clock source. - * If using AXI clock, Core0/1/processor state machine may much faster than - * NB state machine. It will cause problem in this case if cores are released - * before north bridge gets ready. + * NB state machine clock is always connected to OSC (slow clock). + * But Core0/1/processor state machine's clock are connected to AXI + * clock. Now, AXI clock takes the TBG as clock source. + * If using AXI clock, Core0/1/processor state machine may much faster + * than NB state machine. It will cause problem in this case if cores + * are released before north bridge gets ready. */ mmio_clrbits_32(MVEBU_NB_CLOCK_SEL_REG, MVEBU_A53_CPU_CLK_SEL); @@ -328,9 +346,10 @@ static void a3700_set_gen_pwr_off_option(void) /* * Idle AXI interface in order to get L2_WFI - * L2 WFI is only asserted after CORE-0 and CORE-1 WFI asserted. (only both core-0/1 - * in WFI, L2 WFI will be issued by CORE.) - * Once L2 WFI asserted, this bit is used for signalling assertion to AXI IO masters. + * L2 WFI is only asserted after CORE-0 and CORE-1 WFI asserted. + * (only both core-0/1in WFI, L2 WFI will be issued by CORE.) + * Once L2 WFI asserted, this bit is used for signalling assertion + * to AXI IO masters. */ mmio_setbits_32(MVEBU_PM_NB_PWR_CTRL_REG, MVEBU_PM_INTERFACE_IDLE); @@ -352,37 +371,47 @@ static void a3700_set_gen_pwr_off_option(void) static void a3700_en_ddr_self_refresh(void) { /* - * Both count is 16 bits and configurable. By default, osc stb cnt is 0xFFF for lower 12 bits. + * Both count is 16 bits and configurable. By default, osc stb cnt + * is 0xFFF for lower 12 bits. * Thus, powerdown count is smaller than osc count. * This count is used for exiting DDR SR mode on wakeup event. * The powerdown count also has impact on the following * state changes: idle -> count-down -> ... (power-down, vdd off, etc) * Here, make stable counter shorter - * Use power down count value instead of osc_stb_cnt to speed up DDR self refresh exit + * Use power down count value instead of osc_stb_cnt to speed up + * DDR self refresh exit */ mmio_setbits_32(MVEBU_PM_NB_PWR_CTRL_REG, MVEBU_PM_PWR_DN_CNT_SEL); /* * Enable DDR SR mode => controlled by north bridge state machine - * Therefore, we must powerdown north bridge to trigger the DDR SR mode switching. + * Therefore, we must powerdown north bridge to trigger the DDR SR + * mode switching. */ mmio_setbits_32(MVEBU_PM_NB_PWR_OPTION_REG, MVEBU_PM_DDR_SR_EN); /* Disable DDR clock, otherwise DDR will not enter into SR mode. */ mmio_setbits_32(MVEBU_PM_NB_PWR_OPTION_REG, MVEBU_PM_DDR_CLK_DIS_EN); /* Power down DDR PHY (PAD) */ mmio_setbits_32(MVEBU_PM_NB_PWR_OPTION_REG, MVEBU_PM_DDRPHY_PWRDWN_EN); - mmio_setbits_32(MVEBU_PM_NB_PWR_OPTION_REG, MVEBU_PM_DDRPHY_PAD_PWRDWN_EN); + mmio_setbits_32(MVEBU_PM_NB_PWR_OPTION_REG, + MVEBU_PM_DDRPHY_PAD_PWRDWN_EN); /* Set wait time for DDR ready in ROM code */ - mmio_write_32(MVEBU_PM_CPU_VDD_OFF_INFO_1_REG, MVEBU_PM_WAIT_DDR_RDY_VALUE); + mmio_write_32(MVEBU_PM_CPU_VDD_OFF_INFO_1_REG, + MVEBU_PM_WAIT_DDR_RDY_VALUE); /* DDR flush write buffer - mandatory */ - mmio_write_32(MVEBU_DRAM_CMD_0_REG, MVEBU_DRAM_CH0_CMD0 | MVEBU_DRAM_CS_CMD0 | MVEBU_DRAM_WCB_DRAIN_REQ); - while ((mmio_read_32(MVEBU_DRAM_STATS_CH0_REG) & MVEBU_DRAM_WCP_EMPTY) != MVEBU_DRAM_WCP_EMPTY) + mmio_write_32(MVEBU_DRAM_CMD_0_REG, MVEBU_DRAM_CH0_CMD0 | + MVEBU_DRAM_CS_CMD0 | MVEBU_DRAM_WCB_DRAIN_REQ); + while ((mmio_read_32(MVEBU_DRAM_STATS_CH0_REG) & + MVEBU_DRAM_WCP_EMPTY) != MVEBU_DRAM_WCP_EMPTY) ; - /* Trigger PHY reset after ddr out of self refresh => supply reset pulse for DDR phy after wake up. */ - mmio_setbits_32(MVEBU_DRAM_PWR_CTRL_REG, MVEBU_DRAM_PHY_CLK_GATING_EN | MVEBU_DRAM_PHY_AUTO_AC_OFF_EN); + /* Trigger PHY reset after ddr out of self refresh => + * supply reset pulse for DDR phy after wake up + */ + mmio_setbits_32(MVEBU_DRAM_PWR_CTRL_REG, MVEBU_DRAM_PHY_CLK_GATING_EN | + MVEBU_DRAM_PHY_AUTO_AC_OFF_EN); } static void a3700_pwr_dn_avs(void) @@ -443,7 +472,9 @@ static void a3700_set_pwr_off_option(void) /* Power down TBG */ a3700_pwr_dn_tbg(); - /* Power down south bridge, pay attention south bridge setting should be done before */ + /* Power down south bridge, pay attention south bridge setting + * should be done before + */ a3700_pwr_dn_sb(); } @@ -456,7 +487,8 @@ static void a3700_set_wake_up_option(void) mmio_setbits_32(MVEBU_PM_NB_WAKE_UP_EN_REG, MVEBU_PM_NB_WKP_EN); /* Enable both core0 and core1 wakeup on demand */ - mmio_setbits_32(MVEBU_PM_CPU_WAKE_UP_CONF_REG, MVEBU_PM_CORE1_WAKEUP | MVEBU_PM_CORE0_WAKEUP); + mmio_setbits_32(MVEBU_PM_CPU_WAKE_UP_CONF_REG, + MVEBU_PM_CORE1_WAKEUP | MVEBU_PM_CORE0_WAKEUP); /* Enable warm reset in low power mode */ mmio_setbits_32(MVEBU_PM_NB_PWR_OPTION_REG, MVEBU_PM_WARM_RESET_EN); @@ -479,21 +511,27 @@ static void a3700_pm_en_nb_gpio(uint32_t gpio) mmio_setbits_32(MVEBU_NB_GPIO_IRQ_EN_LOW_REG, BIT(gpio)); } - mmio_setbits_32(MVEBU_NB_STEP_DOWN_INT_EN_REG, MVEBU_NB_GPIO_INT_WAKE_WCPU_CLK); + mmio_setbits_32(MVEBU_NB_STEP_DOWN_INT_EN_REG, + MVEBU_NB_GPIO_INT_WAKE_WCPU_CLK); - /* Enable using GPIO as wakeup event (actually not only for north bridge) */ + /* Enable using GPIO as wakeup event + * (actually not only for north bridge) + */ mmio_setbits_32(MVEBU_PM_NB_WAKE_UP_EN_REG, MVEBU_PM_NB_GPIO_WKP_EN | - MVEBU_PM_NB_WKP_EN | MVEBU_PM_CORE1_FIQ_IRQ_WKP_EN | MVEBU_PM_CORE0_FIQ_IRQ_WKP_EN); + MVEBU_PM_NB_WKP_EN | MVEBU_PM_CORE1_FIQ_IRQ_WKP_EN | + MVEBU_PM_CORE0_FIQ_IRQ_WKP_EN); } static void a3700_pm_en_sb_gpio(uint32_t gpio) { /* Enable using GPIO as wakeup event */ mmio_setbits_32(MVEBU_PM_NB_WAKE_UP_EN_REG, MVEBU_PM_SB_WKP_NB_EN | - MVEBU_PM_NB_WKP_EN | MVEBU_PM_CORE1_FIQ_IRQ_WKP_EN | MVEBU_PM_CORE0_FIQ_IRQ_WKP_EN); + MVEBU_PM_NB_WKP_EN | MVEBU_PM_CORE1_FIQ_IRQ_WKP_EN | + MVEBU_PM_CORE0_FIQ_IRQ_WKP_EN); /* SB GPIO Wake UP | South Bridge Wake Up Enable */ - mmio_setbits_32(MVEBU_PM_SB_WK_EN_REG, MVEBU_PM_SB_GPIO_WKP_EN | MVEBU_PM_SB_GPIO_WKP_EN); + mmio_setbits_32(MVEBU_PM_SB_WK_EN_REG, MVEBU_PM_SB_GPIO_WKP_EN | + MVEBU_PM_SB_GPIO_WKP_EN); /* GPIO int mask */ mmio_clrbits_32(MVEBU_SB_GPIO_IRQ_MASK_REG, BIT(gpio)); @@ -548,7 +586,8 @@ struct wake_up_src_func_map src_func_table[WAKE_UP_SRC_MAX] = { {WAKE_UP_SRC_TIMER, NULL} }; -static wake_up_src_func a3700_get_wake_up_src_func(enum pm_wake_up_src_type type) +static wake_up_src_func a3700_get_wake_up_src_func( + enum pm_wake_up_src_type type) { uint32_t loop; for (loop = 0; loop < WAKE_UP_SRC_MAX; loop++) { @@ -566,7 +605,8 @@ static void a3700_set_wake_up_source(void) wake_up_src = mv_wake_up_src_config_get(); for (loop = 0; loop < wake_up_src->wake_up_src_num; loop++) { - src_func = a3700_get_wake_up_src_func(wake_up_src->wake_up_src[loop].wake_up_src_type); + src_func = a3700_get_wake_up_src_func( + wake_up_src->wake_up_src[loop].wake_up_src_type); if (src_func) src_func(&(wake_up_src->wake_up_src[loop].wake_up_data)); } @@ -577,19 +617,22 @@ static void a3700_set_wake_up_source(void) static void a3700_pm_save_lp_flag(void) { /* Save the flag for enter the low power mode */ - mmio_setbits_32(MVEBU_PM_CPU_VDD_OFF_INFO_2_REG, MVEBU_PM_LOW_POWER_STATE); + mmio_setbits_32(MVEBU_PM_CPU_VDD_OFF_INFO_2_REG, + MVEBU_PM_LOW_POWER_STATE); } static void a3700_pm_clear_lp_flag(void) { /* Clear the flag for enter the low power mode */ - mmio_clrbits_32(MVEBU_PM_CPU_VDD_OFF_INFO_2_REG, MVEBU_PM_LOW_POWER_STATE); + mmio_clrbits_32(MVEBU_PM_CPU_VDD_OFF_INFO_2_REG, + MVEBU_PM_LOW_POWER_STATE); } static uint32_t a3700_pm_get_lp_flag(void) { /* Get the flag for enter the low power mode */ - return mmio_read_32(MVEBU_PM_CPU_VDD_OFF_INFO_2_REG) & MVEBU_PM_LOW_POWER_STATE; + return mmio_read_32(MVEBU_PM_CPU_VDD_OFF_INFO_2_REG) & + MVEBU_PM_LOW_POWER_STATE; } /***************************************************************************** @@ -634,7 +677,7 @@ void a3700_pwr_domain_suspend(const psci_power_state_t *target_state) void a3700_pwr_domain_on_finish(const psci_power_state_t *target_state) { /* arch specific configuration */ - psci_arch_init(0); + marvell_psci_arch_init(0); /* Per-CPU interrupt initialization */ plat_marvell_gic_pcpu_init(); @@ -660,7 +703,7 @@ void a3700_pwr_domain_suspend_finish(const psci_power_state_t *target_state) struct dram_win_map dram_wins_map; /* arch specific configuration */ - psci_arch_init(0); + marvell_psci_arch_init(0); /* Interrupt initialization */ plat_marvell_gic_init(); @@ -726,9 +769,6 @@ static void __dead2 a3700_system_off(void) { ERROR("a3700_system_off needs to be implemented\n"); panic(); - wfi(); - ERROR("A3700 System Off: operation not handled.\n"); - panic(); } /***************************************************************************** @@ -744,7 +784,8 @@ static void __dead2 a3700_system_reset(void) /* Flush data cache if the mail box shared RAM is cached */ #if PLAT_MARVELL_SHARED_RAM_CACHED - flush_dcache_range((uintptr_t)PLAT_MARVELL_MAILBOX_BASE, 2 * sizeof(uint64_t)); + flush_dcache_range((uintptr_t)PLAT_MARVELL_MAILBOX_BASE, + 2 * sizeof(uint64_t)); #endif /* Trigger the warm reset */ diff --git a/plat/marvell/a8k-p/a8xxy/board/dram_port.c b/plat/marvell/a8k-p/a8xxy/board/dram_port.c index fa7ff2e3..b18e2c3e 100644 --- a/plat/marvell/a8k-p/a8xxy/board/dram_port.c +++ b/plat/marvell/a8k-p/a8xxy/board/dram_port.c @@ -4,8 +4,9 @@ * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #include <mv_ddr_if.h> -#include <plat_def.h> +#include <mvebu_def.h> #include <plat_marvell.h> /* DB-88F8160-MODULAR has 4 DIMMs on board that are connected to @@ -16,7 +17,8 @@ * AP1 DIMM1 - 0x56 */ #define I2C_SPD_BASE_ADDR 0x53 -#define I2C_SPD_DATA_ADDR(ap_id, iface) (I2C_SPD_BASE_ADDR + (ap_id * DDR_MAX_UNIT_PER_AP) + (iface)) +#define I2C_SPD_DATA_ADDR(ap_id, iface) (I2C_SPD_BASE_ADDR + \ + (ap_id * DDR_MAX_UNIT_PER_AP) + (iface)) #define I2C_SPD_P0_SEL_ADDR 0x36 /* Select SPD data page 0 */ #define MC_RAR_INTERLEAVE_SZ (128) /* Also possible to set to 4Kb */ diff --git a/plat/marvell/a8k-p/a8xxy/board/marvell_plat_config.c b/plat/marvell/a8k-p/a8xxy/board/marvell_plat_config.c index e6702689..e0a99a05 100644 --- a/plat/marvell/a8k-p/a8xxy/board/marvell_plat_config.c +++ b/plat/marvell/a8k-p/a8xxy/board/marvell_plat_config.c @@ -4,9 +4,10 @@ * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + +#include <armada_common.h> #include <ap810_setup.h> -#include <plat_config.h> -#include <plat_def.h> +#include <mvebu_def.h> /* This array describe how CPx connect to APx, via which MCI interface * For AP0: CP0 connected via MCI3 @@ -85,11 +86,11 @@ int marvell_get_gwin_memory_map(int ap, struct addr_map_win **win, uint32_t *siz if (ap_count < 3) { switch (ap) { case 0: - *size = sizeof(gwin_memory_map2_ap0)/sizeof(gwin_memory_map2_ap0[0]); + *size = ARRAY_SIZE(gwin_memory_map2_ap0); *win = gwin_memory_map2_ap0; return 0; case 1: - *size = sizeof(gwin_memory_map2_ap1)/sizeof(gwin_memory_map2_ap1[0]); + *size = ARRAY_SIZE(gwin_memory_map2_ap1); *win = gwin_memory_map2_ap1; return 0; default: @@ -98,19 +99,19 @@ int marvell_get_gwin_memory_map(int ap, struct addr_map_win **win, uint32_t *siz } else { switch (ap) { case 0: - *size = sizeof(gwin_memory_map4_ap0)/sizeof(gwin_memory_map4_ap0[0]); + *size = ARRAY_SIZE(gwin_memory_map4_ap0); *win = gwin_memory_map4_ap0; return 0; case 1: - *size = sizeof(gwin_memory_map4_ap1)/sizeof(gwin_memory_map4_ap1[0]); + *size = ARRAY_SIZE(gwin_memory_map4_ap1); *win = gwin_memory_map4_ap1; return 0; case 2: - *size = sizeof(gwin_memory_map4_ap2)/sizeof(gwin_memory_map4_ap2[0]); + *size = ARRAY_SIZE(gwin_memory_map4_ap2); *win = gwin_memory_map4_ap2; return 0; case 3: - *size = sizeof(gwin_memory_map4_ap3)/sizeof(gwin_memory_map4_ap3[0]); + *size = ARRAY_SIZE(gwin_memory_map4_ap3); *win = gwin_memory_map4_ap3; return 0; default: @@ -177,11 +178,11 @@ int marvell_get_ccu_memory_map(int ap, struct addr_map_win **win, uint32_t *size if (ap_count < 3) { switch (ap) { case 0: - *size = sizeof(ccu_memory_map2_ap0)/sizeof(ccu_memory_map2_ap0[0]); + *size = ARRAY_SIZE(ccu_memory_map2_ap0); *win = ccu_memory_map2_ap0; return 0; case 1: - *size = sizeof(ccu_memory_map2_ap1)/sizeof(ccu_memory_map2_ap1[0]); + *size = ARRAY_SIZE(ccu_memory_map2_ap1); *win = ccu_memory_map2_ap1; return 0; default: @@ -190,19 +191,19 @@ int marvell_get_ccu_memory_map(int ap, struct addr_map_win **win, uint32_t *size } else { switch (ap) { case 0: - *size = sizeof(ccu_memory_map_ap0)/sizeof(ccu_memory_map_ap0[0]); + *size = ARRAY_SIZE(ccu_memory_map_ap0); *win = ccu_memory_map_ap0; return 0; case 1: - *size = sizeof(ccu_memory_map_ap1)/sizeof(ccu_memory_map_ap1[0]); + *size = ARRAY_SIZE(ccu_memory_map_ap1); *win = ccu_memory_map_ap1; return 0; case 2: - *size = sizeof(ccu_memory_map_ap2)/sizeof(ccu_memory_map_ap2[0]); + *size = ARRAY_SIZE(ccu_memory_map_ap2); *win = ccu_memory_map_ap2; return 0; case 3: - *size = sizeof(ccu_memory_map_ap3)/sizeof(ccu_memory_map_ap3[0]); + *size = ARRAY_SIZE(ccu_memory_map_ap3); *win = ccu_memory_map_ap3; return 0; default: @@ -241,18 +242,19 @@ uint32_t marvell_get_io_win_gcr_target(int ap_index) return STM_TID; } -int marvell_get_io_win_memory_map(int ap, struct addr_map_win **win, uint32_t *size) +int marvell_get_io_win_memory_map(int ap, struct addr_map_win **win, + uint32_t *size) { int ap_count = ap_get_count(); if (ap_count < 3) { switch (ap) { case 0: - *size = sizeof(io_win_memory_map2_ap0)/sizeof(io_win_memory_map2_ap0[0]); + *size = ARRAY_SIZE(io_win_memory_map2_ap0); *win = io_win_memory_map2_ap0; return 0; case 1: - *size = sizeof(io_win_memory_map2_ap1)/sizeof(io_win_memory_map2_ap1[0]); + *size = ARRAY_SIZE(io_win_memory_map2_ap1); *win = io_win_memory_map2_ap1; return 0; default: @@ -488,28 +490,29 @@ struct addr_map_win *iob_map[PLAT_MARVELL_NORTHB_COUNT][PLAT_MARVELL_SOUTHB_COUN uint32_t iob_map_size[PLAT_MARVELL_NORTHB_COUNT][PLAT_MARVELL_SOUTHB_COUNT] = { /* AP0 */ - { sizeof(iob_memory_map_ap0_cp0)/sizeof(iob_memory_map_ap0_cp0[0]), - sizeof(iob_memory_map_ap0_cp1)/sizeof(iob_memory_map_ap0_cp1[0]), - sizeof(iob_memory_map_ap0_cp2)/sizeof(iob_memory_map_ap0_cp2[0]), - sizeof(iob_memory_map_ap0_cp3)/sizeof(iob_memory_map_ap0_cp3[0]) }, + { ARRAY_SIZE(iob_memory_map_ap0_cp0), + ARRAY_SIZE(iob_memory_map_ap0_cp1), + ARRAY_SIZE(iob_memory_map_ap0_cp2), + ARRAY_SIZE(iob_memory_map_ap0_cp3) }, /* AP1 */ - { sizeof(iob_memory_map_ap1_cp0)/sizeof(iob_memory_map_ap1_cp0[0]), - sizeof(iob_memory_map_ap1_cp1)/sizeof(iob_memory_map_ap1_cp1[0]), - sizeof(iob_memory_map_ap1_cp2)/sizeof(iob_memory_map_ap1_cp2[0]), - sizeof(iob_memory_map_ap1_cp3)/sizeof(iob_memory_map_ap1_cp3[0]) }, + { ARRAY_SIZE(iob_memory_map_ap1_cp0), + ARRAY_SIZE(iob_memory_map_ap1_cp1), + ARRAY_SIZE(iob_memory_map_ap1_cp2), + ARRAY_SIZE(iob_memory_map_ap1_cp3) }, /* AP2 */ - { sizeof(iob_memory_map_ap2_cp0)/sizeof(iob_memory_map_ap2_cp0[0]), - sizeof(iob_memory_map_ap2_cp1)/sizeof(iob_memory_map_ap2_cp1[0]), - sizeof(iob_memory_map_ap2_cp2)/sizeof(iob_memory_map_ap2_cp2[0]), - sizeof(iob_memory_map_ap2_cp3)/sizeof(iob_memory_map_ap2_cp3[0]) }, + { ARRAY_SIZE(iob_memory_map_ap2_cp0), + ARRAY_SIZE(iob_memory_map_ap2_cp1), + ARRAY_SIZE(iob_memory_map_ap2_cp2), + ARRAY_SIZE(iob_memory_map_ap2_cp3) }, /* AP3 */ - { sizeof(iob_memory_map_ap3_cp0)/sizeof(iob_memory_map_ap3_cp0[0]), - sizeof(iob_memory_map_ap3_cp1)/sizeof(iob_memory_map_ap3_cp1[0]), - sizeof(iob_memory_map_ap3_cp2)/sizeof(iob_memory_map_ap3_cp2[0]), - sizeof(iob_memory_map_ap3_cp3)/sizeof(iob_memory_map_ap3_cp3[0]) } + { ARRAY_SIZE(iob_memory_map_ap3_cp0), + ARRAY_SIZE(iob_memory_map_ap3_cp1), + ARRAY_SIZE(iob_memory_map_ap3_cp2), + ARRAY_SIZE(iob_memory_map_ap3_cp3) } }; -int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { int ap, cp; @@ -532,7 +535,8 @@ int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, uintpt * AMB Configuration ***************************************************************************** */ -struct addr_map_win *amb_map[PLAT_MARVELL_NORTHB_COUNT][PLAT_MARVELL_SOUTHB_COUNT] = { +struct addr_map_win *amb_map[PLAT_MARVELL_NORTHB_COUNT] + [PLAT_MARVELL_SOUTHB_COUNT] = { /* AP0 */ { NULL, NULL, NULL, NULL }, /* AP1 */ @@ -554,7 +558,8 @@ uint32_t amb_map_size[PLAT_MARVELL_NORTHB_COUNT][PLAT_MARVELL_SOUTHB_COUNT] = { { 0, 0, 0, 0 }, }; -int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { int ap, cp; diff --git a/plat/marvell/a8k-p/a8xxy/plat_def.h b/plat/marvell/a8k-p/a8xxy/mvebu_def.h index 77b5eaee..77b5eaee 100644 --- a/plat/marvell/a8k-p/a8xxy/plat_def.h +++ b/plat/marvell/a8k-p/a8xxy/mvebu_def.h diff --git a/plat/marvell/a8k-p/common/a8kp_common.mk b/plat/marvell/a8k-p/common/a8kp_common.mk index d03f7fe7..d1175a3d 100644 --- a/plat/marvell/a8k-p/common/a8kp_common.mk +++ b/plat/marvell/a8k-p/common/a8kp_common.mk @@ -13,6 +13,8 @@ PLAT_COMMON_BASE := $(PLAT_FAMILY_BASE)/common MARVELL_DRV_BASE := drivers/marvell MARVELL_COMMON_BASE := plat/marvell/common +$(eval $(call add_define,PLAT_FAMILY)) + ERRATA_A72_859971 := 1 # Enable MSS support for a8kp family diff --git a/plat/marvell/a8k-p/common/aarch64/plat_arch_config.c b/plat/marvell/a8k-p/common/aarch64/plat_arch_config.c index 1df6a0cd..d0f3f23d 100644 --- a/plat/marvell/a8k-p/common/aarch64/plat_arch_config.c +++ b/plat/marvell/a8k-p/common/aarch64/plat_arch_config.c @@ -26,7 +26,7 @@ static void plat_enable_affinity(void) __asm__ volatile("isb"); } -void psci_arch_init(int ap_index) +void marvell_psci_arch_init(int ap_index) { #if LLC_ENABLE /* check if LLC is in exclusive mode diff --git a/plat/marvell/a8k-p/common/ap810_init_clocks.c b/plat/marvell/a8k-p/common/ap810_init_clocks.c index 580a2e3e..742caae9 100644 --- a/plat/marvell/a8k-p/common/ap810_init_clocks.c +++ b/plat/marvell/a8k-p/common/ap810_init_clocks.c @@ -12,7 +12,7 @@ #include <errno.h> #include <debug.h> #include <mmio.h> -#include <plat_def.h> +#include <mvebu_def.h> #include <stdio.h> /* PLL's registers with local base address since each AP has its own EAWG*/ diff --git a/plat/marvell/a8k-p/common/include/platform_def.h b/plat/marvell/a8k-p/common/include/platform_def.h index e784058e..a4ee0ae4 100644 --- a/plat/marvell/a8k-p/common/include/platform_def.h +++ b/plat/marvell/a8k-p/common/include/platform_def.h @@ -11,7 +11,7 @@ #include <board_marvell_def.h> #include <gic_common.h> #include <interrupt_props.h> -#include <plat_def.h> +#include <mvebu_def.h> #ifndef __ASSEMBLY__ #include <stdio.h> #endif /* __ASSEMBLY__ */ diff --git a/plat/marvell/a8k-p/common/mss/mss_bl2_setup.c b/plat/marvell/a8k-p/common/mss/mss_bl2_setup.c index e0d74978..a58032d4 100644 --- a/plat/marvell/a8k-p/common/mss/mss_bl2_setup.c +++ b/plat/marvell/a8k-p/common/mss/mss_bl2_setup.c @@ -10,8 +10,8 @@ #include <debug.h> #include <mmio.h> #include "mss_scp_bootloader.h" +#include <marvell_plat_priv.h> #include <platform_def.h> -#include <plat_private.h> /* timer functionality */ #define MSS_AP_REG_BASE 0x580000 #define MSS_CP_REG_BASE 0x280000 diff --git a/plat/marvell/a8k-p/common/plat_bl1_setup.c b/plat/marvell/a8k-p/common/plat_bl1_setup.c index c406c4f3..e573aeeb 100644 --- a/plat/marvell/a8k-p/common/plat_bl1_setup.c +++ b/plat/marvell/a8k-p/common/plat_bl1_setup.c @@ -1,19 +1,18 @@ /* - * Copyright (C) 2017 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -#include <plat_config.h> -#include <plat_marvell.h> -#include <plat_private.h> - +#include <armada_common.h> #include <ap810_setup.h> #include <debug.h> #include <delay_timer.h> #include <mci.h> #include <mmio.h> +#include <marvell_plat_priv.h> +#include <plat_marvell.h> /* MCI related defines */ #define MVEBU_AP_SYSTEM_SOFT_RESET_REG(ap) (MVEBU_AP_MISC_SOC_BASE(ap) + 0x54) diff --git a/plat/marvell/a8k-p/common/plat_bl31_setup.c b/plat/marvell/a8k-p/common/plat_bl31_setup.c index de5a20fa..c6ad538a 100644 --- a/plat/marvell/a8k-p/common/plat_bl31_setup.c +++ b/plat/marvell/a8k-p/common/plat_bl31_setup.c @@ -5,14 +5,13 @@ * https://spdx.org/licenses */ -#include <plat_marvell.h> -#include <plat_private.h> - #include <ap810_setup.h> #include <cache_llc.h> #include <cp110_setup.h> #include <debug.h> #include <marvell_pm.h> +#include <marvell_plat_priv.h> +#include <plat_marvell.h> #define CCU_ROUT_OPT_DIS(ap, stop) (MVEBU_A2_BANKED_STOP_BASE(ap, stop) + 0x8) #define CCU_SFWD_UL_AC_EN_OFFSET 9 diff --git a/plat/marvell/a8k-p/common/plat_ble_setup.c b/plat/marvell/a8k-p/common/plat_ble_setup.c index 8e9358ee..cdd5dbc4 100644 --- a/plat/marvell/a8k-p/common/plat_ble_setup.c +++ b/plat/marvell/a8k-p/common/plat_ble_setup.c @@ -11,8 +11,8 @@ #include <a8kp_plat_def.h> #include <debug.h> #include <mmio.h> +#include <mvebu_def.h> #include <plat_marvell.h> -#include <plat_def.h> #include <plat_dram.h> /* Read Frequency Value from MPPS 15-17 and save diff --git a/plat/marvell/a8k-p/common/plat_dram.c b/plat/marvell/a8k-p/common/plat_dram.c index 36052da1..713dc7a1 100644 --- a/plat/marvell/a8k-p/common/plat_dram.c +++ b/plat/marvell/a8k-p/common/plat_dram.c @@ -4,6 +4,7 @@ * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #include <addr_map.h> #include <a8k_i2c.h> #include <ap810_setup.h> @@ -13,7 +14,7 @@ #include <gwin.h> #include <mmio.h> #include <mv_ddr_if.h> -#include <plat_def.h> +#include <mvebu_def.h> #include <plat_dram.h> #define CCU_RGF_WIN0_REG(ap) (MVEBU_CCU_BASE(ap) + 0x90) @@ -45,7 +46,8 @@ #define REMAP_ENABLE_MASK 0x1 /* iface is 0 or 1 */ -#define DSS_SCR_REG(ap, iface) (MVEBU_AR_RFU_BASE(ap) + 0x208 + ((iface) * 0x4)) +#define DSS_SCR_REG(ap, iface) (MVEBU_AR_RFU_BASE(ap) + 0x208 + \ + ((iface) * 0x4)) #define DSS_PPROT_OFFS 4 #define DSS_PPROT_MASK 0x7 #define DSS_PPROT_PRIV_SECURE_DATA 0x1 @@ -58,7 +60,8 @@ extern struct mv_ddr_iface *ptr_iface; /* Use global varibale to check if i2c initialization done */ int i2c_init_done = 0; -static int plat_dram_ap_ifaces_get(int ap_id, struct mv_ddr_iface **ifaces, uint32_t *size) +static int plat_dram_ap_ifaces_get(int ap_id, struct mv_ddr_iface **ifaces, + uint32_t *size) { /* For now support DRAM on AP0/AP1 - TODO: add support for all APs */ if (ap_id == 0) { @@ -110,8 +113,8 @@ static void mpp_config(void) uint32_t val; /* - * The Ax0x0 A0 DB boards are using the AP0 i2c channel (MPP18 and MPP19) - * for accessing all DIMM SPDs available on board. + * The Ax0x0 A0 DB boards are using the AP0 i2c channel + * (MPP18 and MPP19) for accessing all DIMM SPDs available on board. */ reg = MVEBU_AP_MPP_CTRL16_23_REG; val = mmio_read_32(reg); @@ -143,7 +146,8 @@ void plat_dram_freq_update(enum ddr_freq freq_option) * based on information received from SPD or bootloader * configuration located on non volatile storage */ -static void plat_dram_update_topology(uint32_t ap_id, struct mv_ddr_iface *iface) +static void plat_dram_update_topology(uint32_t ap_id, + struct mv_ddr_iface *iface) { struct mv_ddr_topology_map *tm = &iface->tm; int ret; @@ -195,13 +199,15 @@ static void plat_dram_phy_access_config(uint32_t ap_id, uint32_t iface_id) /* Update PHY destination in RGF window */ reg_val = mmio_read_32(CCU_RGF_WIN0_REG(ap_id)); reg_val &= ~(CCU_RGF_WIN_UNIT_ID_MASK << CCU_RGF_WIN_UNIT_ID_OFFS); - reg_val |= ((dram_target & CCU_RGF_WIN_UNIT_ID_MASK) << CCU_RGF_WIN_UNIT_ID_OFFS); + reg_val |= ((dram_target & CCU_RGF_WIN_UNIT_ID_MASK) << + CCU_RGF_WIN_UNIT_ID_OFFS); mmio_write_32(CCU_RGF_WIN0_REG(ap_id), reg_val); /* Update DSS port access permission to DSS_PHY */ reg_val = mmio_read_32(DSS_SCR_REG(ap_id, iface_id)); reg_val &= ~(DSS_PPROT_MASK << DSS_PPROT_OFFS); - reg_val |= ((DSS_PPROT_PRIV_SECURE_DATA & DSS_PPROT_MASK) << DSS_PPROT_OFFS); + reg_val |= ((DSS_PPROT_PRIV_SECURE_DATA & DSS_PPROT_MASK) << + DSS_PPROT_OFFS); mmio_write_32(DSS_SCR_REG(ap_id, iface_id), reg_val); debug_exit(); @@ -223,8 +229,9 @@ static void plat_dram_rar_mode_set(uint32_t ap_id) mmio_write_32(CCU_MC_ITR_OFFSET(ap_id, DRAM_1_TID), interleave); /* Configure RAR registers: - * For RAR 0: mask = interleave, value = 0x0, target = 0x3, enable =0x1. - * For RAR 1: mask = interleave, value = interleave, target = 0x8, enable =0x1 + * For RAR 0: mask = interleave, value = 0x0, target = 0x3, enable = 0x1 + * For RAR 1: mask = interleave, value = interleave, target = 0x8, + * enable =0x1 */ val = interleave << MC_RAR_ADDR_MASK_OFFSET; val |= (DRAM_0_TID << MC_RAR_TID_OFFSET) | MC_RAR_ENABLE; @@ -238,8 +245,9 @@ static void plat_dram_rar_mode_set(uint32_t ap_id) debug_exit(); } -/* Remap Physical address range to Memory Controller addrress range (PA->MCA) */ -void plat_dram_mca_remap(int ap_index, int dram_tgt, uint64_t from, uint64_t to, uint64_t size) +/* Remap Physical address range to Memory Controller address range (PA->MCA) */ +void plat_dram_mca_remap(int ap_index, int dram_tgt, uint64_t from, + uint64_t to, uint64_t size) { int dram_if[] = { -1, -1 }; int if_idx; @@ -276,14 +284,18 @@ void plat_dram_mca_remap(int ap_index, int dram_tgt, uint64_t from, uint64_t to, /* set mc remap source base to the top of dram */ val = (from & REMAP_ADDR_MASK) << REMAP_ADDR_OFFSET; VERBOSE("AP-%d DRAM%d RSBR(0x%x) <== 0x%x\n", - ap_index, if_idx, CCU_MC_RSBR_OFFSET(ap_index, dram_if[if_idx]), val); - mmio_write_32(CCU_MC_RSBR_OFFSET(ap_index, dram_if[if_idx]), val); + ap_index, if_idx, CCU_MC_RSBR_OFFSET(ap_index, + dram_if[if_idx]), val); + mmio_write_32(CCU_MC_RSBR_OFFSET(ap_index, dram_if[if_idx]), + val); /* set mc remap target base to the overlapped dram region */ val = (to & REMAP_ADDR_MASK) << REMAP_ADDR_OFFSET; VERBOSE("AP-%d DRAM%d RTBR(0x%x) <== 0x%x\n", - ap_index, if_idx, CCU_MC_RTBR_OFFSET(ap_index, dram_if[if_idx]), val); - mmio_write_32(CCU_MC_RTBR_OFFSET(ap_index, dram_if[if_idx]), val); + ap_index, if_idx, CCU_MC_RTBR_OFFSET(ap_index, + dram_if[if_idx]), val); + mmio_write_32(CCU_MC_RTBR_OFFSET(ap_index, + dram_if[if_idx]), val); /* set mc remap size to the size of the overlapped dram region */ /* up to 4GB region for remapping */ @@ -291,8 +303,10 @@ void plat_dram_mca_remap(int ap_index, int dram_tgt, uint64_t from, uint64_t to, /* enable remapping */ val |= REMAP_ENABLE_MASK; VERBOSE("AP-%d DRAM%d RCR(0x%x) <== 0x%x\n", - ap_index, if_idx, CCU_MC_RCR_OFFSET(ap_index, dram_if[if_idx]), val); - mmio_write_32(CCU_MC_RCR_OFFSET(ap_index, dram_if[if_idx]), val); + ap_index, if_idx, CCU_MC_RCR_OFFSET(ap_index, + dram_if[if_idx]), val); + mmio_write_32(CCU_MC_RCR_OFFSET(ap_index, dram_if[if_idx]), + val); } debug_exit(); @@ -324,14 +338,18 @@ static void plat_dram_interfaces_update(void) /* Initialize iface mode with single interface */ iface->iface_mode = MV_DDR_RAR_DIS; /* Update base address of interface */ - iface->iface_base_addr = AP_DRAM_BASE_ADDR(ap_id, ap_cnt); + iface->iface_base_addr = AP_DRAM_BASE_ADDR(ap_id, + ap_cnt); /* Count number of interfaces are ready */ - VERBOSE("Found DRAM on interface %d AP-%d\n", iface->id, ap_id); + VERBOSE("Found DRAM on interface %d AP-%d\n", + iface->id, ap_id); iface_cnt++; } - if (iface_cnt < ifaces_size) - NOTICE("\n\tFound %d out of %d DRAM interface in AP %d. Performance may be degraded!!\n", + if (iface_cnt < ifaces_size) { + NOTICE("\n\tFound %d out of %d DRAM interface in AP %d", iface_cnt, ifaces_size, ap_id); + NOTICE(" Performance may be degraded!!\n"); + } } } @@ -345,8 +363,8 @@ static void plat_dram_temp_addr_decode_cfg(uint32_t ap_id, /* Add a single GWIN entry from AP1 to AP0 enabling remote AP access * Also add a CCU widow which will pass all transactions to SRAM * through the GWIN window. - * These widows are needed for DRAM scrubbing and DRAM validation purpose - * both using XOR which saves descriptors on SRAM located in AP0 + * These widows are needed for DRAM scrubbing and DRAM validation + * purpose both using XOR which saves descriptors on SRAM located in AP0 */ if (ap_id != 0) { ccu_temp_win->base_addr = AP_DRAM_BASE_ADDR(0, ap_cnt); @@ -424,24 +442,33 @@ int plat_dram_init(void) * 1. open relevant CCU widow for each interface * according to dram size and ap base address * for validation\scrubbing purpose - * 2. remap dram widow to end of dram size for ap 0 interfaces. - * the remapping here is per interface according to the - * DRAM size of the current interface for DRAM training purpose. + * 2. remap dram widow to end of dram size for ap 0 + * interfaces. The remapping here is per interface + * according to the DRAM size of the current + * interface for DRAM training purpose. */ - plat_dram_temp_addr_decode_cfg(ap_id, ap_cnt, iface, &gwin_temp_win, - &ccu_dram_win, &ccu_temp_win); - if ((ap_id == 0) && (dram_iface_mem_sz_get() > (3 * _1GB_))) + plat_dram_temp_addr_decode_cfg(ap_id, ap_cnt, + iface, &gwin_temp_win, + &ccu_dram_win, + &ccu_temp_win); + if ((ap_id == 0) && + (dram_iface_mem_sz_get() > (3 * _1GB_))) plat_dram_mca_remap(0, ccu_dram_win.target_id, - dram_iface_mem_sz_get(), 3 * _1GB_, _1GB_); + dram_iface_mem_sz_get(), + 3 * _1GB_, _1GB_); /* Call DRAM init per interface */ ret = dram_init(); if (ret) { - ERROR("DRAM interface %d on AP-%d failed\n", i, ap_id); + ERROR("DRAM interface %d on AP-%d failed\n", + i, ap_id); return ret; } - /* Remove the temporary GWIN and CCU windows configured before DRAM training */ - plat_dram_temp_addr_decode_remove(ap_id, &gwin_temp_win, &ccu_temp_win); + /* Remove the temporary GWIN and CCU windows configured + * before DRAM training + */ + plat_dram_temp_addr_decode_remove(ap_id, &gwin_temp_win, + &ccu_temp_win); iface_cnt++; /* Update status of interface */ @@ -452,19 +479,22 @@ int plat_dram_init(void) plat_dram_ap_ifaces_get(ap_id, &iface, &ifaces_size); for (i = 0; i < iface_cnt; i++, iface++) { plat_dram_iface_set(iface); - /* If the number of interfaces equal to MAX (enable RAR) */ + /* If the number of interfaces == MAX (enable RAR) */ if (iface_cnt == DDR_MAX_UNIT_PER_AP) { - VERBOSE("AP-%d set DRAM%d into RAR mode\n", ap_id, i); + VERBOSE("AP-%d set DRAM%d into RAR mode\n", + ap_id, i); ap_dram_tgt = RAR_TID; /* If the base address not 0x0, need to divide - ** the base address, the dram region will be - ** splitted into dual DRAMs - ** */ + * the base address, the dram region will be + * splitted into dual DRAMs + */ iface->iface_base_addr >>= 1; - if (ap810_rev_id_get(ap_id) == MVEBU_AP810_REV_ID_A0) + if (ap810_rev_id_get(ap_id) == + MVEBU_AP810_REV_ID_A0) /* TODO: add ERRATA */ if (iface->id == 1) - iface->iface_base_addr |= 1UL << 43; + iface->iface_base_addr |= + 1UL << 43; } else { if (iface->id == 1) ap_dram_tgt = DRAM_1_TID; @@ -477,22 +507,29 @@ int plat_dram_init(void) INFO("AP-%d DRAM size is 0x%lx (%lldGB)\n", ap_id, ap_dram_size, ap_dram_size/_1GB_); - /* Remap the physical memory shadowed by the internal registers configuration - * address space to the top of the detected memory area. - * Only the AP0 overlaps this configuration area with the DRAM, so only its memory - * controller has to remap the overlapped region to the upper memory. - * With less than 3GB of DRAM the internal registers space remapping is not needed - * since there is no overlap between DRAM and the configuration address spaces - * The remapping here is for AP0 total DRAM size for operational mode purpose + /* Remap the physical memory shadowed by the internal registers + * configuration address space to the top of the detected memory + * area. + * Only the AP0 overlaps this configuration area with the DRAM, + * so only its memory controller has to remap the overlapped + * region to the upper memory. + * With less than 3GB of DRAM the internal registers space + * remapping is not needed since there is no overlap between + * DRAM and the configuration address spaces + * The remapping here is for AP0 total DRAM size for + * operational mode purpose */ if ((ap_id == 0) && (ap_dram_size > (3 * _1GB_))) - plat_dram_mca_remap(0, ap_dram_tgt, ap_dram_size, 3 * _1GB_, _1GB_); + plat_dram_mca_remap(0, ap_dram_tgt, ap_dram_size, + 3 * _1GB_, _1GB_); if (ap_dram_tgt == RAR_TID) plat_dram_rar_mode_set(ap_id); - /* Restore the original DRAM size before returning to the BootROM. - * The correct DRAM size will be set back by init_ccu() at later stage. + /* Restore the original DRAM size before returning to the + * BootROM. + * The correct DRAM size will be set back by init_ccu() at + * later stage. */ ccu_dram_win.base_addr = AP_DRAM_BASE_ADDR(ap_id, ap_cnt); ccu_dram_win.win_size = AP0_BOOTROM_DRAM_SIZE; diff --git a/plat/marvell/a8k-p/common/plat_marvell_gicv3.c b/plat/marvell/a8k-p/common/plat_marvell_gicv3.c index 75d359c9..f27a31fe 100644 --- a/plat/marvell/a8k-p/common/plat_marvell_gicv3.c +++ b/plat/marvell/a8k-p/common/plat_marvell_gicv3.c @@ -15,13 +15,15 @@ * GICv3 Multi chip initialization **************************************************************************** */ -#define GICD_BASE(chip) (MVEBU_REGS_BASE_AP(chip) + MVEBU_GICD_BASE) +#define GICD_BASE(chip) (MVEBU_REGS_BASE_AP(chip) + \ + MVEBU_GICD_BASE) #define GICD_CHIPSR(chip) (GICD_BASE(chip) + 0xC000) #define GICD_CHIPSR_RTS_OFFSET 4 #define GICD_CHIPSR_RTS_MASK 0x3 #define GICD_DCHIPR(chip) (GICD_BASE(chip) + 0xC004) #define GICD_DCHIPR_PUP_OFFSET 0 -#define GICD_CHIPR(chip) (MVEBU_REGS_BASE_AP(0) + MVEBU_GICD_BASE + 0xC008 + (chip) * 0x8) +#define GICD_CHIPR(chip) (MVEBU_REGS_BASE_AP(0) + \ + MVEBU_GICD_BASE + 0xC008 + (chip) * 0x8) #define GICD_CHIPR_PUP_OFFSET 1 #define GICD_CHIPR_SPI_BLOCKS_OFFSET 5 #define GICD_CHIPR_SPI_BLOCKS_MASK 0x1F @@ -34,8 +36,10 @@ #define GICD_CHIPR_CONFIG_VAL(enable, spi_block_min, spi_blocks, addr) \ ((enable) | \ - (((spi_blocks) & GICD_CHIPR_SPI_BLOCKS_MASK) << GICD_CHIPR_SPI_BLOCKS_OFFSET) | \ - (((spi_block_min) & GICD_CHIPR_SPI_BLOCK_MIN_MASK) << GICD_CHIPR_SPI_BLOCK_MIN_OFFSET) | \ + (((spi_blocks) & GICD_CHIPR_SPI_BLOCKS_MASK) << \ + GICD_CHIPR_SPI_BLOCKS_OFFSET) | \ + (((spi_block_min) & GICD_CHIPR_SPI_BLOCK_MIN_MASK) << \ + GICD_CHIPR_SPI_BLOCK_MIN_OFFSET) | \ (((addr) & GICD_CHIPR_ADDR_MASK) << GICD_CHIPR_ADDR_OFFSET)) @@ -67,8 +71,10 @@ int gic_multi_chip_connection_ready(int ap_id) debug_enter(); do { - pup_in_progress = mmio_read_32(GICD_DCHIPR(ap_id)) & (1 << GICD_DCHIPR_PUP_OFFSET); - write_in_progress = mmio_read_64(GICD_CHIPR(ap_id)) & (1 << GICD_CHIPR_PUP_OFFSET); + pup_in_progress = mmio_read_32(GICD_DCHIPR(ap_id)) & + (1 << GICD_DCHIPR_PUP_OFFSET); + write_in_progress = mmio_read_64(GICD_CHIPR(ap_id)) & + (1 << GICD_CHIPR_PUP_OFFSET); } while ((pup_in_progress || write_in_progress) && (timeout-- > 0)); if (pup_in_progress) { @@ -84,11 +90,13 @@ int gic_multi_chip_connection_ready(int ap_id) #if 0 /* TODO: enable this once CHIPSR reflects the right value */ if (ap_id == 0) { /* Check that the Routing Table status is 'Consistent' */ - int rts_status = (mmio_read_32(GICD_CHIPSR(0)) >> GICD_CHIPSR_RTS_OFFSET) & - GICD_CHIPSR_RTS_MASK; + int rts_status = (mmio_read_32(GICD_CHIPSR(0)) >> + GICD_CHIPSR_RTS_OFFSET) & + GICD_CHIPSR_RTS_MASK; INFO("GICD_CHIPSR: 0x%x\n", mmio_read_32(GICD_CHIPSR(0))); if (rts_status != RTS_CONSISTENT) { - INFO("Routing table status (%d) is not consistent\n", rts_status); + INFO("Routing table status (%d) is not consistent\n", + rts_status); return 1; } } @@ -117,25 +125,33 @@ int gic600_multi_chip_init(void) INFO("Configure AP %d\n", nb_id); spi_block_min = (ap_spi_own[nb_id].spi_start - 32) / 32; - spi_blocks = (ap_spi_own[nb_id].spi_end - ap_spi_own[nb_id].spi_start + 1) / 32; - INFO("spi_block_min = %d - spi_blocks = %d\n", spi_block_min, spi_blocks); + spi_blocks = (ap_spi_own[nb_id].spi_end - + ap_spi_own[nb_id].spi_start + 1) / 32; + INFO("spi_block_min = %d - spi_blocks = %d\n", + spi_block_min, spi_blocks); - reg = GICD_CHIPR_CONFIG_VAL(0x1, spi_block_min, spi_blocks, nb_id); + reg = GICD_CHIPR_CONFIG_VAL(0x1, spi_block_min, + spi_blocks, nb_id); mmio_write_64(GICD_CHIPR(nb_id), reg); val = mmio_read_64(GICD_CHIPR(nb_id)); while (((val >> 1) & 0x1) == 1) val = mmio_read_64(GICD_CHIPR(nb_id)); - INFO("AP %d: GICD_CHIPR(nb_id) = %x - GICD_CHIPR: 0x%lx -- val = %x\n", - nb_id, GICD_CHIPR(nb_id), mmio_read_64(GICD_CHIPR(nb_id)), reg); + INFO("AP%d: GICD_CHIPR(nb_id)=%x GICD_CHIPR: 0x%lx val=%x\n", + nb_id, GICD_CHIPR(nb_id), mmio_read_64(GICD_CHIPR(nb_id)), + reg); if (nb_id == 0) { - INFO("GICD_CHIPSR = %x\n", mmio_read_32(GICD_CHIPSR(nb_id))); - INFO("GICD_CHIPR = %x\n", mmio_read_32(GICD_CHIPR(nb_id))); + INFO("GICD_CHIPSR = %x\n", + mmio_read_32(GICD_CHIPSR(nb_id))); + INFO("GICD_CHIPR = %x\n", + mmio_read_32(GICD_CHIPR(nb_id))); } else { - /* check that write was accepted and connection is ready */ + /* check that write was accepted + * and connection is ready + */ if (gic_multi_chip_connection_ready(nb_id)) return 1; } diff --git a/plat/marvell/a8k-p/common/plat_pm.c b/plat/marvell/a8k-p/common/plat_pm.c index 3dbc1eac..ba68f8bb 100644 --- a/plat/marvell/a8k-p/common/plat_pm.c +++ b/plat/marvell/a8k-p/common/plat_pm.c @@ -7,16 +7,16 @@ #include <debug.h> #include <gicv3.h> #include <mmio.h> +#include <marvell_plat_priv.h> #include <platform.h> #include <plat_marvell.h> -#include <plat_private.h> -#define MVEBU_CCU_RVBAR(ap, clus, cpu) (MVEBU_REGS_BASE_AP(ap) + 0x1800 + \ - (0x400 * clus) + 0x240 + (cpu * 0x4)) -#define MVEBU_CCU_PRCR(ap, clus, cpu) (MVEBU_REGS_BASE_AP(ap) + 0x1800 + \ - (0x400 * clus) + 0x250 + (cpu * 0x4)) +#define MVEBU_CCU_RVBAR(ap, clus, cpu) (MVEBU_REGS_BASE_AP(ap) + 0x1800 + \ + (0x400 * clus) + 0x240 + (cpu * 0x4)) +#define MVEBU_CCU_PRCR(ap, clus, cpu) (MVEBU_REGS_BASE_AP(ap) + 0x1800 + \ + (0x400 * clus) + 0x250 + (cpu * 0x4)) -#define MVEBU_RFU_GLOBL_SW_RST 0x184 +#define MVEBU_RFU_GLOBL_SW_RST 0x184 int ap_init_status[PLAT_MARVELL_NORTHB_COUNT]; @@ -37,7 +37,8 @@ static int plat_marvell_cpu_on(u_register_t mpidr) cpu_id = MPIDR_CPU_ID_GET(mpidr); /* Set the cpu start address to BL1 entry point (align to 0x10000) */ - mmio_write_32(MVEBU_CCU_RVBAR(ap_id, clust_id, cpu_id), PLAT_MARVELL_CPU_ENTRY_ADDR >> 16); + mmio_write_32(MVEBU_CCU_RVBAR(ap_id, clust_id, cpu_id), + PLAT_MARVELL_CPU_ENTRY_ADDR >> 16); /* Get the cpu out of reset */ mmio_write_32(MVEBU_CCU_PRCR(ap_id, clust_id, cpu_id), 0x10001); @@ -165,7 +166,7 @@ static void a8kp_pwr_domain_on_finish(const psci_power_state_t *target_state) } /* arch specific configuration */ - psci_arch_init(ap_id); + marvell_psci_arch_init(ap_id); /* Per-CPU interrupt initialization */ plat_marvell_gic_pcpu_init(); @@ -180,7 +181,8 @@ static void a8kp_pwr_domain_on_finish(const psci_power_state_t *target_state) * context. Need to implement a separate suspend finisher. ***************************************************************************** */ -static void a8kp_pwr_domain_suspend_finish(const psci_power_state_t *target_state) +static void a8kp_pwr_domain_suspend_finish(const psci_power_state_t + *target_state) { ERROR("%s: needs to be implemented\n", __func__); panic(); @@ -208,9 +210,6 @@ static void __dead2 a8kp_system_off(void) { ERROR("%s: needs to be implemented\n", __func__); panic(); - wfi(); - ERROR("%s: operation not handled.\n", __func__); - panic(); } void plat_marvell_system_reset(void) diff --git a/plat/marvell/a8k-p/common/plat_pm_trace.c b/plat/marvell/a8k-p/common/plat_pm_trace.c index 0a2d343b..03cb4e19 100644 --- a/plat/marvell/a8k-p/common/plat_pm_trace.c +++ b/plat/marvell/a8k-p/common/plat_pm_trace.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2017 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses diff --git a/plat/marvell/a8k/a3900/board/dram_port.c b/plat/marvell/a8k/a3900/board/dram_port.c index ba25e55b..9622fce6 100644 --- a/plat/marvell/a8k/a3900/board/dram_port.c +++ b/plat/marvell/a8k/a3900/board/dram_port.c @@ -15,7 +15,7 @@ * based on information recieved from SPD or bootloader * configuration located on non volatile storage */ -void plat_dram_update_topology(void) +void plat_marvell_dram_update_topology(void) { NOTICE("Gathering DRAM information\n"); } @@ -53,9 +53,9 @@ struct mv_ddr_iface dram_iface_ap0 = { MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ { {0} }, /* raw spd data */ {0}, /* timing parameters */ - { /* electrical configuration */ - { /* memory electrical configuration */ - MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */ + { /* electrical configuration */ + { /* memory electrical configuration */ + MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */ { MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ @@ -66,7 +66,7 @@ struct mv_ddr_iface dram_iface_ap0 = { }, MV_DDR_DIC_RZQ_DIV7 /* dic */ }, - { /* phy electrical configuration */ + { /* phy electrical configuration */ MV_DDR_OHM_30, /* data_drv_p */ MV_DDR_OHM_30, /* data_drv_n */ MV_DDR_OHM_30, /* ctrl_drv_p */ @@ -80,7 +80,7 @@ struct mv_ddr_iface dram_iface_ap0 = { MV_DDR_OHM_120 /* odt_n 2cs */ }, }, - { /* mac electrical configuration */ + { /* mac electrical configuration */ MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */ MV_DDR_ODT_CFG_NORMAL /* odtcfg_read */ diff --git a/plat/marvell/a8k/a3900/board/marvell_plat_config.c b/plat/marvell/a8k/a3900/board/marvell_plat_config.c index 9d1681f0..7b91e50c 100644 --- a/plat/marvell/a8k/a3900/board/marvell_plat_config.c +++ b/plat/marvell/a8k/a3900/board/marvell_plat_config.c @@ -5,12 +5,13 @@ * https://spdx.org/licenses */ -#include <plat_config.h> +#include <armada_common.h> +#include <mvebu_def.h> + /* * If bootrom is currently at BLE there's no need to include the memory * maps structure at this point */ -#include <plat_def.h> #ifndef IMAGE_BLE /***************************************************************************** @@ -19,13 +20,14 @@ */ struct addr_map_win *amb_memory_map; -int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { *win = amb_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(amb_memory_map)/sizeof(amb_memory_map[0]); + *size = ARRAY_SIZE(amb_memory_map); return 0; } @@ -53,13 +55,14 @@ uint32_t marvell_get_io_win_gcr_target(int ap_index) return PIDI_TID; } -int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = io_win_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(io_win_memory_map)/sizeof(io_win_memory_map[0]); + *size = ARRAY_SIZE(io_win_memory_map); return 0; } @@ -77,10 +80,11 @@ struct addr_map_win iob_memory_map[] = { {0x00000000c0000000, 0x30000000, PEX0_TID}, }; -int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { *win = iob_memory_map; - *size = sizeof(iob_memory_map)/sizeof(iob_memory_map[0]); + *size = ARRAY_SIZE(iob_memory_map); return 0; } @@ -104,10 +108,11 @@ uint32_t marvell_get_ccu_gcr_target(int ap) return DRAM_0_TID; } -int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = ccu_memory_map; - *size = sizeof(ccu_memory_map)/sizeof(ccu_memory_map[0]); + *size = ARRAY_SIZE(ccu_memory_map); return 0; } diff --git a/plat/marvell/a8k/a3900/plat_def.h b/plat/marvell/a8k/a3900/mvebu_def.h index 075ea9da..075ea9da 100644 --- a/plat/marvell/a8k/a3900/plat_def.h +++ b/plat/marvell/a8k/a3900/mvebu_def.h diff --git a/plat/marvell/a8k/a3900_z1/board/dram_port.c b/plat/marvell/a8k/a3900_z1/board/dram_port.c index 4acff01d..cd8669eb 100644 --- a/plat/marvell/a8k/a3900_z1/board/dram_port.c +++ b/plat/marvell/a8k/a3900_z1/board/dram_port.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses @@ -14,9 +14,8 @@ * based on information received from SPD or bootloader * configuration located on non volatile storage */ -void plat_dram_update_topology(void) +void plat_marvell_dram_update_topology(void) { - NOTICE("Gathering DRAM information\n"); } /* @@ -47,12 +46,12 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ { {0} }, /* raw spd data */ {0}, /* timing parameters */ - { /* electrical configuration */ - { /* memory electrical configuration */ + { /* electrical configuration */ + { /* memory electrical configuration */ MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */ { - MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ - MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ }, { MV_DDR_RTT_WR_DYN_ODT_OFF, /* rtt_wr 1cs */ @@ -60,7 +59,7 @@ static struct mv_ddr_topology_map board_topology_map = { }, MV_DDR_DIC_RZQ_DIV7 /* dic */ }, - { /* phy electrical configuration */ + { /* phy electrical configuration */ MV_DDR_OHM_30, /* data_drv_p */ MV_DDR_OHM_30, /* data_drv_n */ MV_DDR_OHM_30, /* ctrl_drv_p */ @@ -74,10 +73,10 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_OHM_120 /* odt_n 2cs */ }, }, - { /* mac electrical configuration */ - MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ + { /* mac electrical configuration */ + MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */ - MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ + MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ }, } }; diff --git a/plat/marvell/a8k/a3900_z1/board/marvell_plat_config.c b/plat/marvell/a8k/a3900_z1/board/marvell_plat_config.c index 708bca16..f1968c4e 100644 --- a/plat/marvell/a8k/a3900_z1/board/marvell_plat_config.c +++ b/plat/marvell/a8k/a3900_z1/board/marvell_plat_config.c @@ -1,15 +1,17 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -#include <plat_config.h> + +#include <armada_common.h> +#include <mvebu_def.h> + /* * If bootrom is currently at BLE there's no need to include the memory * maps structure at this point */ -#include <plat_def.h> #ifndef IMAGE_BLE /***************************************************************************** @@ -18,13 +20,14 @@ */ struct addr_map_win *amb_memory_map; -int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { *win = amb_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(amb_memory_map)/sizeof(amb_memory_map[0]); + *size = ARRAY_SIZE(amb_memory_map); return 0; } @@ -52,13 +55,14 @@ uint32_t marvell_get_io_win_gcr_target(int ap_index) return PIDI_TID; } -int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = io_win_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(io_win_memory_map)/sizeof(io_win_memory_map[0]); + *size = ARRAY_SIZE(io_win_memory_map); return 0; } @@ -76,10 +80,11 @@ struct addr_map_win iob_memory_map[] = { {0x00000000c0000000, 0x30000000, PEX0_TID}, }; -int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { *win = iob_memory_map; - *size = sizeof(iob_memory_map)/sizeof(iob_memory_map[0]); + *size = ARRAY_SIZE(iob_memory_map); return 0; } @@ -103,10 +108,11 @@ uint32_t marvell_get_ccu_gcr_target(int ap) return DRAM_0_TID; } -int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = ccu_memory_map; - *size = sizeof(ccu_memory_map)/sizeof(ccu_memory_map[0]); + *size = ARRAY_SIZE(ccu_memory_map); return 0; } diff --git a/plat/marvell/a8k/a3900_z1/plat_def.h b/plat/marvell/a8k/a3900_z1/mvebu_def.h index ea74303d..713ce55f 100644 --- a/plat/marvell/a8k/a3900_z1/plat_def.h +++ b/plat/marvell/a8k/a3900_z1/mvebu_def.h @@ -1,9 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #ifndef __MVEBU_DEF_H__ #define __MVEBU_DEF_H__ diff --git a/plat/marvell/a8k/a3900_z1/platform.mk b/plat/marvell/a8k/a3900_z1/platform.mk index 173a44ee..d3a01676 100644 --- a/plat/marvell/a8k/a3900_z1/platform.mk +++ b/plat/marvell/a8k/a3900_z1/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (C) 2016 - 2018 Marvell International Ltd. +# Copyright (C) 2018 Marvell International Ltd. # # SPDX-License-Identifier: BSD-3-Clause # https://spdx.org/licenses diff --git a/plat/marvell/a8k/a70x0/board/dram_port.c b/plat/marvell/a8k/a70x0/board/dram_port.c index b871a29e..c6702589 100644 --- a/plat/marvell/a8k/a70x0/board/dram_port.c +++ b/plat/marvell/a8k/a70x0/board/dram_port.c @@ -1,9 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #include <arch_helpers.h> #include <debug.h> #include <mv_ddr_if.h> @@ -11,12 +12,11 @@ /* * This function may modify the default DRAM parameters - * based on information recieved from SPD or bootloader + * based on information received from SPD or bootloader * configuration located on non volatile storage */ -void plat_dram_update_topology(void) +void plat_marvell_dram_update_topology(void) { - INFO("Gathering DRAM information\n"); } /* @@ -47,12 +47,12 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ { {0} }, /* raw spd data */ {0}, /* timing parameters */ - { /* electrical configuration */ - { /* memory electrical configuration */ + { /* electrical configuration */ + { /* memory electrical configuration */ MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */ { - MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ - MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ }, { MV_DDR_RTT_WR_DYN_ODT_OFF, /* rtt_wr 1cs */ @@ -60,7 +60,7 @@ static struct mv_ddr_topology_map board_topology_map = { }, MV_DDR_DIC_RZQ_DIV7 /* dic */ }, - { /* phy electrical configuration */ + { /* phy electrical configuration */ MV_DDR_OHM_30, /* data_drv_p */ MV_DDR_OHM_30, /* data_drv_n */ MV_DDR_OHM_30, /* ctrl_drv_p */ @@ -74,10 +74,10 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_OHM_120 /* odt_n 2cs */ }, }, - { /* mac electrical configuration */ - MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ + { /* mac electrical configuration */ + MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */ - MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ + MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ }, } }; diff --git a/plat/marvell/a8k/a70x0/board/marvell_plat_config.c b/plat/marvell/a8k/a70x0/board/marvell_plat_config.c index 6d904fec..d126f556 100644 --- a/plat/marvell/a8k/a70x0/board/marvell_plat_config.c +++ b/plat/marvell/a8k/a70x0/board/marvell_plat_config.c @@ -1,15 +1,17 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -#include <plat_config.h> + +#include <armada_common.h> + /* * If bootrom is currently at BLE there's no need to include the memory * maps structure at this point */ -#include <plat_def.h> +#include <mvebu_def.h> #ifndef IMAGE_BLE /***************************************************************************** @@ -21,13 +23,14 @@ struct addr_map_win amb_memory_map[] = { {0xf900, 0x1000000, AMB_SPI1_CS0_ID}, }; -int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_amb_memory_map(struct addr_map_win **win, + uint32_t *size, uintptr_t base) { *win = amb_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(amb_memory_map)/sizeof(amb_memory_map[0]); + *size = ARRAY_SIZE(amb_memory_map); return 0; } @@ -51,13 +54,14 @@ uint32_t marvell_get_io_win_gcr_target(int ap_index) return PIDI_TID; } -int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = io_win_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(io_win_memory_map)/sizeof(io_win_memory_map[0]); + *size = ARRAY_SIZE(io_win_memory_map); return 0; } @@ -80,10 +84,11 @@ struct addr_map_win iob_memory_map[] = { {0x00000000f9000000, 0x1000000, RUNIT_TID}, }; -int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { *win = iob_memory_map; - *size = sizeof(iob_memory_map)/sizeof(iob_memory_map[0]); + *size = ARRAY_SIZE(iob_memory_map); return 0; } @@ -108,10 +113,11 @@ uint32_t marvell_get_ccu_gcr_target(int ap) return DRAM_0_TID; } -int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = ccu_memory_map; - *size = sizeof(ccu_memory_map)/sizeof(ccu_memory_map[0]); + *size = ARRAY_SIZE(ccu_memory_map); return 0; } @@ -130,7 +136,7 @@ struct skip_image skip_im = { .info.test.cp_index = 0, }; -void *plat_get_skip_image_data(void) +void *plat_marvell_get_skip_image_data(void) { /* Return the skip_image configurations */ return &skip_im; diff --git a/plat/marvell/a8k/a70x0/plat_def.h b/plat/marvell/a8k/a70x0/mvebu_def.h index 129d9332..a7c5abbb 100644 --- a/plat/marvell/a8k/a70x0/plat_def.h +++ b/plat/marvell/a8k/a70x0/mvebu_def.h @@ -1,10 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ - + #ifndef __MVEBU_DEF_H__ #define __MVEBU_DEF_H__ diff --git a/plat/marvell/a8k/a70x0/platform.mk b/plat/marvell/a8k/a70x0/platform.mk index 173a44ee..d3a01676 100644 --- a/plat/marvell/a8k/a70x0/platform.mk +++ b/plat/marvell/a8k/a70x0/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (C) 2016 - 2018 Marvell International Ltd. +# Copyright (C) 2018 Marvell International Ltd. # # SPDX-License-Identifier: BSD-3-Clause # https://spdx.org/licenses diff --git a/plat/marvell/a8k/a70x0_amc/board/dram_port.c b/plat/marvell/a8k/a70x0_amc/board/dram_port.c index 8481fa7e..ab1df465 100644 --- a/plat/marvell/a8k/a70x0_amc/board/dram_port.c +++ b/plat/marvell/a8k/a70x0_amc/board/dram_port.c @@ -1,9 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #include <arch_helpers.h> #include <debug.h> #include <mv_ddr_if.h> @@ -14,9 +15,8 @@ * based on information received from SPD or bootloader * configuration located on non volatile storage */ -void plat_dram_update_topology(void) +void plat_marvell_dram_update_topology(void) { - INFO("Gathering DRAM information\n"); } /* @@ -47,12 +47,12 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ { {0} }, /* raw spd data */ {0}, /* timing parameters */ - { /* electrical configuration */ - { /* memory electrical configuration */ + { /* electrical configuration */ + { /* memory electrical configuration */ MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */ { - MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ - MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ }, { MV_DDR_RTT_WR_DYN_ODT_OFF, /* rtt_wr 1cs */ @@ -60,7 +60,7 @@ static struct mv_ddr_topology_map board_topology_map = { }, MV_DDR_DIC_RZQ_DIV7 /* dic */ }, - { /* phy electrical configuration */ + { /* phy electrical configuration */ MV_DDR_OHM_30, /* data_drv_p */ MV_DDR_OHM_30, /* data_drv_n */ MV_DDR_OHM_30, /* ctrl_drv_p */ @@ -74,10 +74,10 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_OHM_120 /* odt_n 2cs */ }, }, - { /* mac electrical configuration */ - MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ + { /* mac electrical configuration */ + MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */ - MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ + MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ }, } }; diff --git a/plat/marvell/a8k/a70x0_amc/board/marvell_plat_config.c b/plat/marvell/a8k/a70x0_amc/board/marvell_plat_config.c index d3bcee60..f8a1c40b 100644 --- a/plat/marvell/a8k/a70x0_amc/board/marvell_plat_config.c +++ b/plat/marvell/a8k/a70x0_amc/board/marvell_plat_config.c @@ -1,15 +1,17 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -#include <plat_config.h> + +#include <armada_common.h> + /* * If bootrom is currently at BLE there's no need to include the memory * maps structure at this point */ -#include <plat_def.h> +#include <mvebu_def.h> #ifndef IMAGE_BLE /***************************************************************************** @@ -18,13 +20,14 @@ */ struct addr_map_win *amb_memory_map; -int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { *win = amb_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(amb_memory_map)/sizeof(amb_memory_map[0]); + *size = ARRAY_SIZE(amb_memory_map); return 0; } @@ -48,13 +51,14 @@ uint32_t marvell_get_io_win_gcr_target(int ap_index) return PIDI_TID; } -int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = io_win_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(io_win_memory_map)/sizeof(io_win_memory_map[0]); + *size = ARRAY_SIZE(io_win_memory_map); return 0; } @@ -71,10 +75,11 @@ struct addr_map_win iob_memory_map[] = { {0x0000000800000000, 0x200000000, PEX0_TID}, }; -int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { *win = iob_memory_map; - *size = sizeof(iob_memory_map)/sizeof(iob_memory_map[0]); + *size = ARRAY_SIZE(iob_memory_map); return 0; } @@ -99,10 +104,11 @@ uint32_t marvell_get_ccu_gcr_target(int ap) return DRAM_0_TID; } -int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = ccu_memory_map; - *size = sizeof(ccu_memory_map)/sizeof(ccu_memory_map[0]); + *size = ARRAY_SIZE(ccu_memory_map); return 0; } @@ -127,7 +133,7 @@ struct skip_image skip_im = { .info.test.cp_index = 0, }; -void *plat_get_skip_image_data(void) +void *plat_marvell_get_skip_image_data(void) { /* Return the skip_image configurations */ return &skip_im; diff --git a/plat/marvell/a8k/a70x0_amc/plat_def.h b/plat/marvell/a8k/a70x0_amc/mvebu_def.h index e8bbc154..5c665528 100644 --- a/plat/marvell/a8k/a70x0_amc/plat_def.h +++ b/plat/marvell/a8k/a70x0_amc/mvebu_def.h @@ -1,9 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #ifndef __MVEBU_DEF_H__ #define __MVEBU_DEF_H__ @@ -13,7 +14,7 @@ /*********************************************************************** * Required platform porting definitions common to all - * Mangement Compute SubSystems (MSS) + * Management Compute SubSystems (MSS) *********************************************************************** */ /* @@ -23,7 +24,7 @@ * it is discarded and BL31 is loaded over the top. */ #ifdef SCP_IMAGE -#define SCP_BL2_BASE BL31_BASE +#define SCP_BL2_BASE BL31_BASE #endif diff --git a/plat/marvell/a8k/a70x0_amc/platform.mk b/plat/marvell/a8k/a70x0_amc/platform.mk index 173a44ee..d3a01676 100644 --- a/plat/marvell/a8k/a70x0_amc/platform.mk +++ b/plat/marvell/a8k/a70x0_amc/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (C) 2016 - 2018 Marvell International Ltd. +# Copyright (C) 2018 Marvell International Ltd. # # SPDX-License-Identifier: BSD-3-Clause # https://spdx.org/licenses diff --git a/plat/marvell/a8k/a70x0_cust/board/dram_port.c b/plat/marvell/a8k/a70x0_cust/board/dram_port.c index fdcb0bfc..1acf742e 100644 --- a/plat/marvell/a8k/a70x0_cust/board/dram_port.c +++ b/plat/marvell/a8k/a70x0_cust/board/dram_port.c @@ -1,15 +1,16 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #include <arch_helpers.h> #include <a8k_i2c.h> #include <debug.h> #include <mmio.h> #include <mv_ddr_if.h> -#include <plat_def.h> +#include <mvebu_def.h> #include <plat_marvell.h> /* @@ -40,12 +41,12 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ { {0} }, /* raw spd data */ {0}, /* timing parameters */ - { /* electrical configuration */ - { /* memory electrical configuration */ + { /* electrical configuration */ + { /* memory electrical configuration */ MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */ { - MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ - MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ }, { MV_DDR_RTT_WR_DYN_ODT_OFF, /* rtt_wr 1cs */ @@ -53,7 +54,7 @@ static struct mv_ddr_topology_map board_topology_map = { }, MV_DDR_DIC_RZQ_DIV7 /* dic */ }, - { /* phy electrical configuration */ + { /* phy electrical configuration */ MV_DDR_OHM_30, /* data_drv_p */ MV_DDR_OHM_30, /* data_drv_n */ MV_DDR_OHM_30, /* ctrl_drv_p */ @@ -67,10 +68,10 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_OHM_120 /* odt_n 2cs */ }, }, - { /* mac electrical configuration */ - MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ + { /* mac electrical configuration */ + MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */ - MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ + MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ }, } }; @@ -95,7 +96,7 @@ static void mpp_config(void) * based on information received from SPD or bootloader * configuration located on non volatile storage */ -void plat_dram_update_topology(void) +void plat_marvell_dram_update_topology(void) { struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); diff --git a/plat/marvell/a8k/a70x0_cust/board/marvell_plat_config.c b/plat/marvell/a8k/a70x0_cust/board/marvell_plat_config.c index 9c7d6c20..ea133b6f 100644 --- a/plat/marvell/a8k/a70x0_cust/board/marvell_plat_config.c +++ b/plat/marvell/a8k/a70x0_cust/board/marvell_plat_config.c @@ -1,15 +1,17 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -#include <plat_config.h> + +#include <armada_common.h> +#include <mvebu_def.h> + /* * If bootrom is currently at BLE there's no need to include the memory * maps structure at this point */ -#include <plat_def.h> #ifndef IMAGE_BLE /***************************************************************************** @@ -20,13 +22,14 @@ struct addr_map_win amb_memory_map[] = { {0xf900, 0x1000000, AMB_DEV_CS0_ID}, /* Device Bus window */ }; -int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_amb_memory_map(struct addr_map_win **win, + uint32_t *size, uintptr_t base) { *win = amb_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(amb_memory_map)/sizeof(amb_memory_map[0]); + *size = ARRAY_SIZE(amb_memory_map); return 0; } @@ -50,13 +53,14 @@ uint32_t marvell_get_io_win_gcr_target(int ap_index) return PIDI_TID; } -int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = io_win_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(io_win_memory_map)/sizeof(io_win_memory_map[0]); + *size = ARRAY_SIZE(io_win_memory_map); return 0; } @@ -75,10 +79,11 @@ struct addr_map_win iob_memory_map[] = { {0x00000000f6000000, 0x1000000, PEX0_TID}, }; -int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { *win = iob_memory_map; - *size = sizeof(iob_memory_map)/sizeof(iob_memory_map[0]); + *size = ARRAY_SIZE(iob_memory_map); return 0; } @@ -101,10 +106,11 @@ uint32_t marvell_get_ccu_gcr_target(int ap) return DRAM_0_TID; } -int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = ccu_memory_map; - *size = sizeof(ccu_memory_map)/sizeof(ccu_memory_map[0]); + *size = ARRAY_SIZE(ccu_memory_map); return 0; } diff --git a/plat/marvell/a8k/a70x0_cust/plat_def.h b/plat/marvell/a8k/a70x0_cust/mvebu_def.h index 419ae84e..026bc61b 100644 --- a/plat/marvell/a8k/a70x0_cust/plat_def.h +++ b/plat/marvell/a8k/a70x0_cust/mvebu_def.h @@ -1,9 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #ifndef __MVEBU_DEF_H__ #define __MVEBU_DEF_H__ diff --git a/plat/marvell/a8k/a70x0_cust/platform.mk b/plat/marvell/a8k/a70x0_cust/platform.mk index 173a44ee..d3a01676 100644 --- a/plat/marvell/a8k/a70x0_cust/platform.mk +++ b/plat/marvell/a8k/a70x0_cust/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (C) 2016 - 2018 Marvell International Ltd. +# Copyright (C) 2018 Marvell International Ltd. # # SPDX-License-Identifier: BSD-3-Clause # https://spdx.org/licenses diff --git a/plat/marvell/a8k/a70x0_pcac/board/dram_port.c b/plat/marvell/a8k/a70x0_pcac/board/dram_port.c index 44488372..fccc532f 100644 --- a/plat/marvell/a8k/a70x0_pcac/board/dram_port.c +++ b/plat/marvell/a8k/a70x0_pcac/board/dram_port.c @@ -1,9 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #include <arch_helpers.h> #include <debug.h> #include <mv_ddr_if.h> @@ -14,9 +15,8 @@ * based on information received from SPD or bootloader * configuration located on non volatile storage */ -void plat_dram_update_topology(void) +void plat_marvell_dram_update_topology(void) { - INFO("Gathering DRAM information\n"); } /* @@ -47,12 +47,12 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ { {0} }, /* raw spd data */ {0}, /* timing parameters */ - { /* electrical configuration */ - { /* memory electrical configuration */ + { /* electrical configuration */ + { /* memory electrical configuration */ MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */ { - MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ - MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ }, { MV_DDR_RTT_WR_DYN_ODT_OFF, /* rtt_wr 1cs */ @@ -60,7 +60,7 @@ static struct mv_ddr_topology_map board_topology_map = { }, MV_DDR_DIC_RZQ_DIV7 /* dic */ }, - { /* phy electrical configuration */ + { /* phy electrical configuration */ MV_DDR_OHM_30, /* data_drv_p */ MV_DDR_OHM_30, /* data_drv_n */ MV_DDR_OHM_30, /* ctrl_drv_p */ @@ -74,7 +74,7 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_OHM_120 /* odt_n 2cs */ }, }, - { /* mac electrical configuration */ + { /* mac electrical configuration */ MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */ MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ diff --git a/plat/marvell/a8k/a70x0_pcac/board/marvell_plat_config.c b/plat/marvell/a8k/a70x0_pcac/board/marvell_plat_config.c index 0b7996a9..aa13c38f 100644 --- a/plat/marvell/a8k/a70x0_pcac/board/marvell_plat_config.c +++ b/plat/marvell/a8k/a70x0_pcac/board/marvell_plat_config.c @@ -1,16 +1,18 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -#include <plat_config.h> +#include <armada_common.h> +#include <mvebu_def.h> +#include <pci_ep.h> + /* * If bootrom is currently at BLE there's no need to include the memory * maps structure at this point */ -#include <plat_def.h> #ifndef IMAGE_BLE /***************************************************************************** @@ -19,7 +21,8 @@ */ struct addr_map_win *amb_memory_map; -int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { *win = amb_memory_map; if (*win == NULL) @@ -49,7 +52,8 @@ uint32_t marvell_get_io_win_gcr_target(int ap_index) return PIDI_TID; } -int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = io_win_memory_map; if (*win == NULL) @@ -74,7 +78,8 @@ struct addr_map_win iob_memory_map[] = { {0x0000008000000000, 0x80000000000, PEX0_TID}, }; -int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { *win = iob_memory_map; *size = sizeof(iob_memory_map)/sizeof(iob_memory_map[0]); @@ -101,7 +106,8 @@ uint32_t marvell_get_ccu_gcr_target(int ap) return DRAM_0_TID; } -int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = ccu_memory_map; *size = sizeof(ccu_memory_map)/sizeof(ccu_memory_map[0]); diff --git a/plat/marvell/a8k/a70x0_pcac/plat_def.h b/plat/marvell/a8k/a70x0_pcac/mvebu_def.h index 5f227133..cd0cdc15 100644 --- a/plat/marvell/a8k/a70x0_pcac/plat_def.h +++ b/plat/marvell/a8k/a70x0_pcac/mvebu_def.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses diff --git a/plat/marvell/a8k/a70x0_pcac/platform.mk b/plat/marvell/a8k/a70x0_pcac/platform.mk index bc8c878f..c7d44f19 100644 --- a/plat/marvell/a8k/a70x0_pcac/platform.mk +++ b/plat/marvell/a8k/a70x0_pcac/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (C) 2016 - 2018 Marvell International Ltd. +# Copyright (C) 2018 Marvell International Ltd. # # SPDX-License-Identifier: BSD-3-Clause # https://spdx.org/licenses diff --git a/plat/marvell/a8k/a80x0/board/dram_port.c b/plat/marvell/a8k/a80x0/board/dram_port.c index a1eff474..54c4883c 100644 --- a/plat/marvell/a8k/a80x0/board/dram_port.c +++ b/plat/marvell/a8k/a80x0/board/dram_port.c @@ -1,15 +1,16 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #include <arch_helpers.h> #include <a8k_i2c.h> #include <debug.h> #include <mmio.h> #include <mv_ddr_if.h> -#include <plat_def.h> +#include <mvebu_def.h> #include <plat_marvell.h> #define MVEBU_AP_MPP_CTRL0_7_REG MVEBU_AP_MPP_REGS(0) @@ -54,12 +55,12 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_CFG_SPD, /* ddr configuration data source */ { {0} }, /* raw spd data */ {0}, /* timing parameters */ - { /* electrical configuration */ - { /* memory electrical configuration */ + { /* electrical configuration */ + { /* memory electrical configuration */ MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */ { - MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ - MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ }, { MV_DDR_RTT_WR_DYN_ODT_OFF, /* rtt_wr 1cs */ @@ -67,7 +68,7 @@ static struct mv_ddr_topology_map board_topology_map = { }, MV_DDR_DIC_RZQ_DIV7 /* dic */ }, - { /* phy electrical configuration */ + { /* phy electrical configuration */ MV_DDR_OHM_30, /* data_drv_p */ MV_DDR_OHM_30, /* data_drv_n */ MV_DDR_OHM_30, /* ctrl_drv_p */ @@ -81,10 +82,10 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_OHM_120 /* odt_n 2cs */ }, }, - { /* mac electrical configuration */ - MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ + { /* mac electrical configuration */ + MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */ - MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ + MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ }, } }; @@ -117,7 +118,7 @@ static void mpp_config(void) * based on information received from SPD or bootloader * configuration located on non volatile storage */ -void plat_dram_update_topology(void) +void plat_marvell_dram_update_topology(void) { struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); diff --git a/plat/marvell/a8k/a80x0/board/marvell_plat_config.c b/plat/marvell/a8k/a80x0/board/marvell_plat_config.c index 65684434..836c9b40 100644 --- a/plat/marvell/a8k/a80x0/board/marvell_plat_config.c +++ b/plat/marvell/a8k/a80x0/board/marvell_plat_config.c @@ -1,16 +1,17 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -#include <plat_config.h> +#include <armada_common.h> + /* * If bootrom is currently at BLE there's no need to include the memory * maps structure at this point */ -#include <plat_def.h> +#include <mvebu_def.h> #ifndef IMAGE_BLE /***************************************************************************** @@ -22,13 +23,14 @@ struct addr_map_win amb_memory_map[] = { {0xf900, 0x1000000, AMB_SPI1_CS0_ID}, }; -int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { *win = amb_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(amb_memory_map)/sizeof(amb_memory_map[0]); + *size = ARRAY_SIZE(amb_memory_map); return 0; } @@ -60,13 +62,14 @@ uint32_t marvell_get_io_win_gcr_target(int ap_index) return PIDI_TID; } -int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = io_win_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(io_win_memory_map)/sizeof(io_win_memory_map[0]); + *size = ARRAY_SIZE(io_win_memory_map); return 0; } @@ -100,16 +103,17 @@ struct addr_map_win iob_memory_map_cp1[] = { {0x00000000fa000000, 0x1000000, PEX0_TID} }; -int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { switch (base) { case MVEBU_CP_REGS_BASE(0): *win = iob_memory_map_cp0; - *size = sizeof(iob_memory_map_cp0)/sizeof(iob_memory_map_cp0[0]); + *size = ARRAY_SIZE(iob_memory_map_cp0); return 0; case MVEBU_CP_REGS_BASE(1): *win = iob_memory_map_cp1; - *size = sizeof(iob_memory_map_cp1)/sizeof(iob_memory_map_cp1[0]); + *size = ARRAY_SIZE(iob_memory_map_cp1); return 0; default: *size = 0; @@ -138,10 +142,11 @@ uint32_t marvell_get_ccu_gcr_target(int ap) return DRAM_0_TID; } -int marvell_get_ccu_memory_map(int ap, struct addr_map_win **win, uint32_t *size) +int marvell_get_ccu_memory_map(int ap, struct addr_map_win **win, + uint32_t *size) { *win = ccu_memory_map; - *size = sizeof(ccu_memory_map)/sizeof(ccu_memory_map[0]); + *size = ARRAY_SIZE(ccu_memory_map); return 0; } @@ -161,7 +166,7 @@ struct power_off_method pm_cfg = { .cfg.gpio.delay_ms = 10, }; -void *plat_get_pm_cfg(void) +void *plat_marvell_get_pm_cfg(void) { /* Return the PM configurations */ return &pm_cfg; @@ -182,7 +187,7 @@ struct skip_image skip_im = { .info.test.cp_index = 0, }; -void *plat_get_skip_image_data(void) +void *plat_marvell_get_skip_image_data(void) { /* Return the skip_image configurations */ return &skip_im; diff --git a/plat/marvell/a8k/a80x0_32bit_ddr/plat_def.h b/plat/marvell/a8k/a80x0/mvebu_def.h index 7686aa20..5bff12ce 100644 --- a/plat/marvell/a8k/a80x0_32bit_ddr/plat_def.h +++ b/plat/marvell/a8k/a80x0/mvebu_def.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses diff --git a/plat/marvell/a8k/a80x0/platform.mk b/plat/marvell/a8k/a80x0/platform.mk index 4b96ae3f..00d24b27 100644 --- a/plat/marvell/a8k/a80x0/platform.mk +++ b/plat/marvell/a8k/a80x0/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (C) 2016 - 2018 Marvell International Ltd. +# Copyright (C) 2018 Marvell International Ltd. # # SPDX-License-Identifier: BSD-3-Clause # https://spdx.org/licenses diff --git a/plat/marvell/a8k/a80x0_32bit_ddr/board/dram_port.c b/plat/marvell/a8k/a80x0_32bit_ddr/board/dram_port.c index 7b9e4ab5..8eb8810e 100644 --- a/plat/marvell/a8k/a80x0_32bit_ddr/board/dram_port.c +++ b/plat/marvell/a8k/a80x0_32bit_ddr/board/dram_port.c @@ -1,15 +1,16 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #include <arch_helpers.h> #include <a8k_i2c.h> #include <debug.h> #include <mmio.h> #include <mv_ddr_if.h> -#include <plat_def.h> +#include <mvebu_def.h> #include <plat_marvell.h> #define MVEBU_AP_MPP_CTRL0_7_REG MVEBU_AP_MPP_REGS(0) @@ -54,12 +55,12 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ { {0} }, /* raw spd data */ {0}, /* timing parameters */ - { /* electrical configuration */ - { /* memory electrical configuration */ + { /* electrical configuration */ + { /* memory electrical configuration */ MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */ { - MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ - MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ }, { MV_DDR_RTT_WR_DYN_ODT_OFF, /* rtt_wr 1cs */ @@ -67,7 +68,7 @@ static struct mv_ddr_topology_map board_topology_map = { }, MV_DDR_DIC_RZQ_DIV7 /* dic */ }, - { /* phy electrical configuration */ + { /* phy electrical configuration */ MV_DDR_OHM_30, /* data_drv_p */ MV_DDR_OHM_30, /* data_drv_n */ MV_DDR_OHM_30, /* ctrl_drv_p */ @@ -81,10 +82,10 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_OHM_120 /* odt_n 2cs */ }, }, - { /* mac electrical configuration */ - MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ + { /* mac electrical configuration */ + MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */ - MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ + MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ }, } }; @@ -117,7 +118,7 @@ static void mpp_config(void) * based on information received from SPD or bootloader * configuration located on non volatile storage */ -void plat_dram_update_topology(void) +void plat_marvell_dram_update_topology(void) { struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); diff --git a/plat/marvell/a8k/a80x0_32bit_ddr/board/marvell_plat_config.c b/plat/marvell/a8k/a80x0_32bit_ddr/board/marvell_plat_config.c index a154fb0f..c0742b0e 100644 --- a/plat/marvell/a8k/a80x0_32bit_ddr/board/marvell_plat_config.c +++ b/plat/marvell/a8k/a80x0_32bit_ddr/board/marvell_plat_config.c @@ -1,16 +1,17 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -#include <plat_config.h> +#include <armada_common.h> +#include <mvebu_def.h> + /* * If bootrom is currently at BLE there's no need to include the memory * maps structure at this point */ -#include <plat_def.h> #ifndef IMAGE_BLE /***************************************************************************** @@ -22,7 +23,8 @@ struct addr_map_win amb_memory_map[] = { {0xf900, 0x1000000, AMB_SPI1_CS0_ID}, }; -int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { *win = amb_memory_map; if (*win == NULL) @@ -60,7 +62,8 @@ uint32_t marvell_get_io_win_gcr_target(int ap_index) return PIDI_TID; } -int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = io_win_memory_map; if (*win == NULL) @@ -98,7 +101,8 @@ struct addr_map_win iob_memory_map_cp1[] = { {0x00000000fa000000, 0x1000000, PEX0_TID} }; -int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { switch (base) { case MVEBU_CP_REGS_BASE(0): @@ -134,7 +138,8 @@ uint32_t marvell_get_ccu_gcr_target(int ap) return DRAM_0_TID; } -int marvell_get_ccu_memory_map(int ap, struct addr_map_win **win, uint32_t *size) +int marvell_get_ccu_memory_map(int ap, struct addr_map_win **win, + uint32_t *size) { *win = ccu_memory_map; *size = ARRAY_SIZE(ccu_memory_map); diff --git a/plat/marvell/a8k/a80x0_mcbin/plat_def.h b/plat/marvell/a8k/a80x0_32bit_ddr/mvebu_def.h index 3fb268cf..5bff12ce 100644 --- a/plat/marvell/a8k/a80x0_mcbin/plat_def.h +++ b/plat/marvell/a8k/a80x0_32bit_ddr/mvebu_def.h @@ -1,9 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #ifndef __MVEBU_DEF_H__ #define __MVEBU_DEF_H__ diff --git a/plat/marvell/a8k/a80x0_32bit_ddr/platform.mk b/plat/marvell/a8k/a80x0_32bit_ddr/platform.mk index 142d987b..34818c13 100644 --- a/plat/marvell/a8k/a80x0_32bit_ddr/platform.mk +++ b/plat/marvell/a8k/a80x0_32bit_ddr/platform.mk @@ -1,9 +1,16 @@ # -# Copyright (C) 2016 - 2018 Marvell International Ltd. +# Copyright (C) 2018 Marvell International Ltd. # # SPDX-License-Identifier: BSD-3-Clause # https://spdx.org/licenses +PCI_EP_SUPPORT := 0 + +DOIMAGE_SEC := tools/doimage/secure/sec_img_8K.cfg + +MARVELL_MOCHI_DRV := drivers/marvell/mochi/apn806_setup.c + + CP_NUM := 2 $(eval $(call add_define,CP_NUM)) diff --git a/plat/marvell/a8k/a80x0_mcbin/board/dram_port.c b/plat/marvell/a8k/a80x0_mcbin/board/dram_port.c index b0150086..4be98f7b 100644 --- a/plat/marvell/a8k/a80x0_mcbin/board/dram_port.c +++ b/plat/marvell/a8k/a80x0_mcbin/board/dram_port.c @@ -1,15 +1,16 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #include <arch_helpers.h> #include <a8k_i2c.h> #include <debug.h> #include <mmio.h> #include <mv_ddr_if.h> -#include <plat_def.h> +#include <mvebu_def.h> #include <plat_marvell.h> #define MVEBU_CP_MPP_CTRL37_OFFS 20 @@ -48,12 +49,12 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_CFG_SPD, /* ddr configuration data source */ { {0} }, /* raw spd data */ {0}, /* timing parameters */ - { /* electrical configuration */ - { /* memory electrical configuration */ + { /* electrical configuration */ + { /* memory electrical configuration */ MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */ { - MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ - MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ }, { MV_DDR_RTT_WR_DYN_ODT_OFF, /* rtt_wr 1cs */ @@ -61,7 +62,7 @@ static struct mv_ddr_topology_map board_topology_map = { }, MV_DDR_DIC_RZQ_DIV7 /* dic */ }, - { /* phy electrical configuration */ + { /* phy electrical configuration */ MV_DDR_OHM_30, /* data_drv_p */ MV_DDR_OHM_30, /* data_drv_n */ MV_DDR_OHM_30, /* ctrl_drv_p */ @@ -75,10 +76,10 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_OHM_120 /* odt_n 2cs */ }, }, - { /* mac electrical configuration */ - MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ + { /* mac electrical configuration */ + MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */ - MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ + MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ }, } }; @@ -108,7 +109,7 @@ static void mpp_config(void) * based on information received from SPD or bootloader * configuration located on non volatile storage */ -void plat_dram_update_topology(void) +void plat_marvell_dram_update_topology(void) { struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); diff --git a/plat/marvell/a8k/a80x0_mcbin/board/marvell_plat_config.c b/plat/marvell/a8k/a80x0_mcbin/board/marvell_plat_config.c index fbe7ce9e..384d0f54 100644 --- a/plat/marvell/a8k/a80x0_mcbin/board/marvell_plat_config.c +++ b/plat/marvell/a8k/a80x0_mcbin/board/marvell_plat_config.c @@ -1,18 +1,19 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ +#include <armada_common.h> #include <delay_timer.h> #include <mmio.h> -#include <plat_config.h> + /* * If bootrom is currently at BLE there's no need to include the memory * maps structure at this point */ -#include <plat_def.h> +#include <mvebu_def.h> #ifndef IMAGE_BLE /***************************************************************************** @@ -55,13 +56,14 @@ struct addr_map_win amb_memory_map[] = { {0xf900, 0x1000000, AMB_SPI1_CS0_ID}, }; -int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { *win = amb_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(amb_memory_map)/sizeof(amb_memory_map[0]); + *size = ARRAY_SIZE(amb_memory_map); return 0; } @@ -93,13 +95,14 @@ uint32_t marvell_get_io_win_gcr_target(int ap_index) return PIDI_TID; } -int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = io_win_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(io_win_memory_map)/sizeof(io_win_memory_map[0]); + *size = ARRAY_SIZE(io_win_memory_map); return 0; } @@ -133,16 +136,17 @@ struct addr_map_win iob_memory_map_cp1[] = { {0x00000000fa000000, 0x1000000, PEX0_TID} }; -int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { switch (base) { case MVEBU_CP_REGS_BASE(0): *win = iob_memory_map_cp0; - *size = sizeof(iob_memory_map_cp0)/sizeof(iob_memory_map_cp0[0]); + *size = ARRAY_SIZE(iob_memory_map_cp0); return 0; case MVEBU_CP_REGS_BASE(1): *win = iob_memory_map_cp1; - *size = sizeof(iob_memory_map_cp1)/sizeof(iob_memory_map_cp1[0]); + *size = ARRAY_SIZE(iob_memory_map_cp1); return 0; default: *size = 0; @@ -171,10 +175,11 @@ uint32_t marvell_get_ccu_gcr_target(int ap) return DRAM_0_TID; } -int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = ccu_memory_map; - *size = sizeof(ccu_memory_map)/sizeof(ccu_memory_map[0]); + *size = ARRAY_SIZE(ccu_memory_map); return 0; } @@ -185,7 +190,7 @@ int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, uint32_t * SKIP IMAGE Configuration ***************************************************************************** */ -void *plat_get_skip_image_data(void) +void *plat_marvell_get_skip_image_data(void) { /* No recovery button on A8k-MCBIN board */ return NULL; diff --git a/plat/marvell/a8k/a80x0/plat_def.h b/plat/marvell/a8k/a80x0_mcbin/mvebu_def.h index 8b98cc70..5bff12ce 100644 --- a/plat/marvell/a8k/a80x0/plat_def.h +++ b/plat/marvell/a8k/a80x0_mcbin/mvebu_def.h @@ -1,10 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ - + #ifndef __MVEBU_DEF_H__ #define __MVEBU_DEF_H__ diff --git a/plat/marvell/a8k/a80x0_mcbin/platform.mk b/plat/marvell/a8k/a80x0_mcbin/platform.mk index 667f1d27..3749c378 100644 --- a/plat/marvell/a8k/a80x0_mcbin/platform.mk +++ b/plat/marvell/a8k/a80x0_mcbin/platform.mk @@ -1,5 +1,5 @@ # -# Copyright (C) 2016 - 2018 Marvell International Ltd. +# Copyright (C) 2018 Marvell International Ltd. # # SPDX-License-Identifier: BSD-3-Clause # https://spdx.org/licenses diff --git a/plat/marvell/a8k/a80x0_ocp/board/dram_port.c b/plat/marvell/a8k/a80x0_ocp/board/dram_port.c index 4c836707..e4acc98c 100644 --- a/plat/marvell/a8k/a80x0_ocp/board/dram_port.c +++ b/plat/marvell/a8k/a80x0_ocp/board/dram_port.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses @@ -7,10 +7,10 @@ #include <arch_helpers.h> #include <a8k_i2c.h> #include <debug.h> +#include <mvebu_def.h> #include <mmio.h> #include <mv_ddr_if.h> #include <plat_marvell.h> -#include <plat_def.h> /* * This struct provides the DRAM training code with @@ -40,12 +40,12 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ { {0} }, /* raw spd data */ {0}, /* timing parameters */ - { /* electrical configuration */ - { /* memory electrical configuration */ + { /* electrical configuration */ + { /* memory electrical configuration */ MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */ { - MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ - MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */ + MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */ }, { MV_DDR_RTT_WR_DYN_ODT_OFF, /* rtt_wr 1cs */ @@ -53,7 +53,7 @@ static struct mv_ddr_topology_map board_topology_map = { }, MV_DDR_DIC_RZQ_DIV7 /* dic */ }, - { /* phy electrical configuration */ + { /* phy electrical configuration */ MV_DDR_OHM_30, /* data_drv_p */ MV_DDR_OHM_30, /* data_drv_n */ MV_DDR_OHM_30, /* ctrl_drv_p */ @@ -67,10 +67,10 @@ static struct mv_ddr_topology_map board_topology_map = { MV_DDR_OHM_120 /* odt_n 2cs */ }, }, - { /* mac electrical configuration */ - MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ + { /* mac electrical configuration */ + MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */ MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */ - MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ + MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */ }, } }; @@ -86,6 +86,6 @@ struct mv_ddr_topology_map *mv_ddr_topology_map_get(void) * based on information received from SPD or bootloader * configuration located on non volatile storage */ -void plat_dram_update_topology(void) +void plat_marvell_dram_update_topology(void) { } diff --git a/plat/marvell/a8k/a80x0_ocp/board/marvell_plat_config.c b/plat/marvell/a8k/a80x0_ocp/board/marvell_plat_config.c index 833ba7c7..2c10ca88 100644 --- a/plat/marvell/a8k/a80x0_ocp/board/marvell_plat_config.c +++ b/plat/marvell/a8k/a80x0_ocp/board/marvell_plat_config.c @@ -1,15 +1,18 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -#include <plat_config.h> + +#include <armada_common.h> +#include <mvebu_def.h> +#include <pci_ep.h> + /* * If bootrom is currently at BLE there's no need to include the memory * maps structure at this point */ -#include <plat_def.h> #ifndef IMAGE_BLE /***************************************************************************** @@ -18,13 +21,14 @@ */ struct addr_map_win *amb_memory_map; -int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_amb_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { *win = amb_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(amb_memory_map)/sizeof(amb_memory_map[0]); + *size = ARRAY_SIZE(amb_memory_map); return 0; } @@ -50,13 +54,14 @@ uint32_t marvell_get_io_win_gcr_target(int ap_index) return PIDI_TID; } -int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = io_win_memory_map; if (*win == NULL) *size = 0; else - *size = sizeof(io_win_memory_map)/sizeof(io_win_memory_map[0]); + *size = ARRAY_SIZE(io_win_memory_map); return 0; } @@ -72,12 +77,13 @@ struct addr_map_win iob_memory_map_cp0[] = { {0x0000008000000000, 0x800000000, PEX0_TID} }; -int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, uintptr_t base) +int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size, + uintptr_t base) { switch (base) { case MVEBU_CP_REGS_BASE(0): *win = iob_memory_map_cp0; - *size = sizeof(iob_memory_map_cp0)/sizeof(iob_memory_map_cp0[0]); + *size = ARRAY_SIZE(iob_memory_map_cp0); return 0; case MVEBU_CP_REGS_BASE(1): *size = 0; @@ -109,10 +115,11 @@ uint32_t marvell_get_ccu_gcr_target(int ap) return DRAM_0_TID; } -int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, uint32_t *size) +int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win, + uint32_t *size) { *win = ccu_memory_map; - *size = sizeof(ccu_memory_map)/sizeof(ccu_memory_map[0]); + *size = ARRAY_SIZE(ccu_memory_map); return 0; } diff --git a/plat/marvell/a8k/a80x0_ocp/plat_def.h b/plat/marvell/a8k/a80x0_ocp/mvebu_def.h index 51b0ee8f..51b0ee8f 100644 --- a/plat/marvell/a8k/a80x0_ocp/plat_def.h +++ b/plat/marvell/a8k/a80x0_ocp/mvebu_def.h diff --git a/plat/marvell/a8k/common/a8k_common.mk b/plat/marvell/a8k/common/a8k_common.mk index 64886ea4..b032b19d 100644 --- a/plat/marvell/a8k/common/a8k_common.mk +++ b/plat/marvell/a8k/common/a8k_common.mk @@ -13,6 +13,8 @@ PLAT_COMMON_BASE := $(PLAT_FAMILY_BASE)/common MARVELL_DRV_BASE := drivers/marvell MARVELL_COMMON_BASE := plat/marvell/common +$(eval $(call add_define,PLAT_FAMILY)) + ERRATA_A72_859971 := 1 # Enable MSS support for a8k family @@ -61,15 +63,15 @@ BLE_PORTING_SOURCES := $(PLAT_FAMILY_BASE)/$(PLAT)/board/dram_port.c \ MARVELL_MOCHI_DRV += $(MARVELL_DRV_BASE)/mochi/cp110_setup.c -BLE_SOURCES := $(PLAT_COMMON_BASE)/plat_ble_setup.c \ - $(MARVELL_MOCHI_DRV) \ - $(MARVELL_DRV_BASE)/i2c/a8k_i2c.c \ - $(PLAT_COMMON_BASE)/plat_pm.c \ - $(MARVELL_DRV_BASE)/aro.c \ - $(MARVELL_DRV_BASE)/thermal.c \ - $(PLAT_COMMON_BASE)/plat_thermal.c \ - $(BLE_PORTING_SOURCES) \ - $(MARVELL_DRV_BASE)/ccu.c \ +BLE_SOURCES := $(PLAT_COMMON_BASE)/plat_ble_setup.c \ + $(MARVELL_MOCHI_DRV) \ + $(MARVELL_DRV_BASE)/i2c/a8k_i2c.c \ + $(PLAT_COMMON_BASE)/plat_pm.c \ + $(MARVELL_DRV_BASE)/aro.c \ + $(MARVELL_DRV_BASE)/thermal.c \ + $(PLAT_COMMON_BASE)/plat_thermal.c \ + $(BLE_PORTING_SOURCES) \ + $(MARVELL_DRV_BASE)/ccu.c \ $(MARVELL_DRV_BASE)/io_win.c ifeq (${PCI_EP_SUPPORT}, 1) diff --git a/plat/marvell/a8k/common/aarch64/a8k_common.c b/plat/marvell/a8k/common/aarch64/a8k_common.c index 86814320..b9e02cb9 100644 --- a/plat/marvell/a8k/common/aarch64/a8k_common.c +++ b/plat/marvell/a8k/common/aarch64/a8k_common.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses diff --git a/plat/marvell/a8k/common/aarch64/plat_arch_config.c b/plat/marvell/a8k/common/aarch64/plat_arch_config.c index 131421be..86673314 100644 --- a/plat/marvell/a8k/common/aarch64/plat_arch_config.c +++ b/plat/marvell/a8k/common/aarch64/plat_arch_config.c @@ -1,10 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ - + #include <platform.h> #include <arch_helpers.h> #include <mmio.h> @@ -16,7 +16,7 @@ #define MVEBU_IO_AFFINITY (0xF00) -void plat_enable_affinity(void) +static void plat_enable_affinity(void) { int cluster_id; int affinity; @@ -27,10 +27,10 @@ void plat_enable_affinity(void) mmio_write_32(CCU_HTC_ASET, affinity); /* set barier */ - __asm__ volatile("isb"); + isb(); } -void psci_arch_init(int die_index) +void marvell_psci_arch_init(int die_index) { #if LLC_ENABLE /* check if LLC is in exclusive mode diff --git a/plat/marvell/a8k/common/aarch64/plat_helpers.S b/plat/marvell/a8k/common/aarch64/plat_helpers.S index e6a8eed8..fadc4c26 100644 --- a/plat/marvell/a8k/common/aarch64/plat_helpers.S +++ b/plat/marvell/a8k/common/aarch64/plat_helpers.S @@ -1,10 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ - + #include <asm_macros.S> #include <platform_def.h> #include <marvell_pm.h> @@ -38,11 +38,12 @@ endfunc plat_secondary_cold_boot_setup * --------------------------------------------------------------------- */ func plat_get_my_entrypoint - mov_imm x0, PLAT_MARVELL_MAILBOX_BASE /* Read first word and compare it with magic num */ + /* Read first word and compare it with magic num */ + mov_imm x0, PLAT_MARVELL_MAILBOX_BASE ldr x1, [x0] mov_imm x2, MVEBU_MAILBOX_MAGIC_NUM cmp x1, x2 - beq warm_boot /* If compare failed, return 0, i.e. cold boot */ + beq warm_boot /* If compare failed, return 0, i.e. cold boot */ mov x0, #0 ret warm_boot: diff --git a/plat/marvell/a8k/common/include/a8k_plat_def.h b/plat/marvell/a8k/common/include/a8k_plat_def.h index 80607d93..95f8c417 100644 --- a/plat/marvell/a8k/common/include/a8k_plat_def.h +++ b/plat/marvell/a8k/common/include/a8k_plat_def.h @@ -1,12 +1,12 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -#ifndef __MVEBU_A8K_DEF_H__ -#define __MVEBU_A8K_DEF_H__ +#ifndef __A8K_PLAT_DEF_H__ +#define __A8K_PLAT_DEF_H__ #include <marvell_def.h> @@ -55,9 +55,11 @@ #define MVEBU_PM_MPP_REGS(cp_index, n) (MVEBU_CP_REGS_BASE(cp_index) + \ 0x440000 + ((n / 8) << 2)) #define MVEBU_CP_GPIO_DATA_OUT(cp_index, n) \ - (MVEBU_CP_REGS_BASE(cp_index) + 0x440100 + ((n > 32) ? 0x40 : 0x00)) + (MVEBU_CP_REGS_BASE(cp_index) + \ + 0x440100 + ((n > 32) ? 0x40 : 0x00)) #define MVEBU_CP_GPIO_DATA_OUT_EN(cp_index, n) \ - (MVEBU_CP_REGS_BASE(cp_index) + 0x440104 + ((n > 32) ? 0x40 : 0x00)) + (MVEBU_CP_REGS_BASE(cp_index) + \ + 0x440104 + ((n > 32) ? 0x40 : 0x00)) #define MVEBU_CP_GPIO_DATA_IN(cp_index, n) (MVEBU_CP_REGS_BASE(cp_index) + \ 0x440110 + ((n > 32) ? 0x40 : 0x00)) #define MVEBU_AP_MPP_REGS(n) (MVEBU_RFU_BASE + 0x4000 + ((n) << 2)) @@ -67,40 +69,47 @@ #define MVEBU_CP0_I2C_BASE (MVEBU_CP_REGS_BASE(0) + 0x701000) #define MVEBU_AP_EXT_TSEN_BASE (MVEBU_RFU_BASE + 0x8084) -#define MVEBU_AP_MC_TRUSTZONE_REG_LOW(ap, win) (MVEBU_REGS_BASE_AP(ap) + 0x20080 + ((win) * 0x8)) -#define MVEBU_AP_MC_TRUSTZONE_REG_HIGH(ap, win) (MVEBU_REGS_BASE_AP(ap) + 0x20084 + ((win) * 0x8)) +#define MVEBU_AP_MC_TRUSTZONE_REG_LOW(ap, win) (MVEBU_REGS_BASE_AP(ap) + \ + 0x20080 + ((win) * 0x8)) +#define MVEBU_AP_MC_TRUSTZONE_REG_HIGH(ap, win) (MVEBU_REGS_BASE_AP(ap) + \ + 0x20084 + ((win) * 0x8)) /* MCI indirect access definitions */ #define MCI_MAX_UNIT_ID 2 /* SoC RFU / IHBx4 Control */ -#define MCIX4_REG_START_ADDRESS_REG(unit_id) (MVEBU_RFU_BASE + 0x4218 + (unit_id * 0x20)) +#define MCIX4_REG_START_ADDRESS_REG(unit_id) (MVEBU_RFU_BASE + \ + 0x4218 + (unit_id * 0x20)) #define MCI_REMAP_OFF_SHIFT 8 -#define MVEBU_MCI_REG_BASE_REMAP(index) (0xFD000000 + ((index) * 0x1000000)) +#define MVEBU_MCI_REG_BASE_REMAP(index) (0xFD000000 + \ + ((index) * 0x1000000)) #define MVEBU_PCIE_X4_MAC_BASE(x) (MVEBU_CP_REGS_BASE(x) + 0x600000) #define MVEBU_COMPHY_BASE(x) (MVEBU_CP_REGS_BASE(x) + 0x441000) #define MVEBU_HPIPE_BASE(x) (MVEBU_CP_REGS_BASE(x) + 0x120000) #define MVEBU_CP_DFX_OFFSET (0x400200) -/******************************************************************************* +/***************************************************************************** * MVEBU memory map related constants - ******************************************************************************/ + ***************************************************************************** + */ /* Aggregate of all devices in the first GB */ #define DEVICE0_BASE MVEBU_REGS_BASE #define DEVICE0_SIZE 0x10000000 /******************************************************************************* * GIC-400 & interrupt handling related constants - ******************************************************************************/ + ***************************************************************************** + */ /* Base MVEBU compatible GIC memory map */ #define MVEBU_GICD_BASE 0x210000 #define MVEBU_GICC_BASE 0x220000 -/******************************************************************************* +/***************************************************************************** * AXI Configuration - ******************************************************************************/ + ***************************************************************************** + */ #define MVEBU_AXI_ATTR_ARCACHE_OFFSET 4 #define MVEBU_AXI_ATTR_ARCACHE_MASK (0xF << \ MVEBU_AXI_ATTR_ARCACHE_OFFSET) @@ -133,9 +142,9 @@ #define DOMAIN_OUTER_SHAREABLE 0x2 #define DOMAIN_SYSTEM_SHAREABLE 0x3 -/************************************************************************* +/************************************************************************ * Required platform porting definitions common to all - * Mangement Compute SubSystems (MSS) + * Management Compute SubSystems (MSS) ************************************************************************ */ /* diff --git a/plat/marvell/a8k/common/include/ddr_info.h b/plat/marvell/a8k/common/include/ddr_info.h index ae90dbd0..e19036a2 100644 --- a/plat/marvell/a8k/common/include/ddr_info.h +++ b/plat/marvell/a8k/common/include/ddr_info.h @@ -1,4 +1,3 @@ - /* * Copyright (C) 2018 Marvell International Ltd. * diff --git a/plat/marvell/a8k/common/include/plat_macros.S b/plat/marvell/a8k/common/include/plat_macros.S index b082208d..2a6ccf27 100644 --- a/plat/marvell/a8k/common/include/plat_macros.S +++ b/plat/marvell/a8k/common/include/plat_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses diff --git a/plat/marvell/a8k/common/include/platform_def.h b/plat/marvell/a8k/common/include/platform_def.h index ac65c662..45650ef6 100644 --- a/plat/marvell/a8k/common/include/platform_def.h +++ b/plat/marvell/a8k/common/include/platform_def.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses @@ -11,7 +11,7 @@ #include <board_marvell_def.h> #include <gic_common.h> #include <interrupt_props.h> -#include <plat_def.h> +#include <mvebu_def.h> #ifndef __ASSEMBLY__ #include <stdio.h> #endif /* __ASSEMBLY__ */ @@ -137,8 +137,8 @@ GIC_INTR_CFG_LEVEL) #define PLAT_MARVELL_G1S_IRQ_PROPS(grp) \ - INTR_PROP_DESC(MARVELL_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, grp, \ - GIC_INTR_CFG_LEVEL), \ + INTR_PROP_DESC(MARVELL_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \ + grp, GIC_INTR_CFG_LEVEL), \ INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \ GIC_INTR_CFG_LEVEL), \ INTR_PROP_DESC(MARVELL_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \ @@ -191,8 +191,11 @@ /* System timer related constants */ #define PLAT_MARVELL_NSTIMER_FRAME_ID 1 -/* Mailbox base address (note the lower memory space are reserved for BLE data) */ -#define PLAT_MARVELL_MAILBOX_BASE (MARVELL_TRUSTED_SRAM_BASE + 0x400) +/* Mailbox base address (note the lower memory space + * is reserved for BLE data) + */ +#define PLAT_MARVELL_MAILBOX_BASE (MARVELL_TRUSTED_SRAM_BASE \ + + 0x400) #define PLAT_MARVELL_MAILBOX_SIZE 0x100 #define PLAT_MARVELL_MAILBOX_MAGIC_NUM 0x6D72766C /* mrvl */ diff --git a/plat/marvell/a8k/common/mss/mss_a8k.mk b/plat/marvell/a8k/common/mss/mss_a8k.mk index 7ca9132f..58f23d8d 100644 --- a/plat/marvell/a8k/common/mss/mss_a8k.mk +++ b/plat/marvell/a8k/common/mss/mss_a8k.mk @@ -1,18 +1,18 @@ # -# Copyright (C) 2016 - 2018 Marvell International Ltd. +# Copyright (C) 2018 Marvell International Ltd. # # SPDX-License-Identifier: BSD-3-Clause # https://spdx.org/licenses # -PLAT_MARVELL := plat/marvell -A8K_MSS_SOURCE := $(PLAT_MARVELL)/a8k/common/mss +PLAT_MARVELL := plat/marvell +A8K_MSS_SOURCE := $(PLAT_MARVELL)/a8k/common/mss BL2_SOURCES += $(A8K_MSS_SOURCE)/mss_bl2_setup.c BL31_SOURCES += $(A8K_MSS_SOURCE)/mss_pm_ipc.c -PLAT_INCLUDES += -I$(A8K_MSS_SOURCE) +PLAT_INCLUDES += -I$(A8K_MSS_SOURCE) ifneq (${SCP_BL2},) # This define is used to inidcate the SCP image is present diff --git a/plat/marvell/a8k/common/mss/mss_bl2_setup.c b/plat/marvell/a8k/common/mss/mss_bl2_setup.c index df73a886..58a9472b 100644 --- a/plat/marvell/a8k/common/mss/mss_bl2_setup.c +++ b/plat/marvell/a8k/common/mss/mss_bl2_setup.c @@ -1,17 +1,18 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + +#include <armada_common.h> #include <bl_common.h> #include <ccu.h> #include <cp110_setup.h> #include <debug.h> +#include <marvell_plat_priv.h> /* timer functionality */ #include <mmio.h> -#include <plat_config.h> #include <platform_def.h> -#include <plat_private.h> /* timer functionality */ #include "mss_scp_bootloader.h" @@ -53,7 +54,7 @@ static int bl2_plat_mmap_init(void) { int cfg_num, win_id, cfg_idx; - cfg_num = sizeof(ccu_mem_map) / sizeof(ccu_mem_map[0]); + cfg_num = ARRAY_SIZE(ccu_mem_map); /* CCU window-0 should not be counted - it's already used */ if (cfg_num > (MVEBU_CCU_MAX_WINS - 1)) { @@ -77,10 +78,11 @@ static int bl2_plat_mmap_init(void) return 0; } -/******************************************************************************* +/***************************************************************************** * Transfer SCP_BL2 from Trusted RAM using the SCP Download protocol. * Return 0 on success, -1 otherwise. - ******************************************************************************/ + ***************************************************************************** + */ int bl2_plat_handle_scp_bl2(image_info_t *scp_bl2_image_info) { int ret; @@ -122,7 +124,8 @@ uint32_t bl2_plat_get_cp_count(int ap_idx) /* A8040: two CPs. * A7040: one CP. */ - if (revision == MVEBU_80X0_DEV_ID || revision == MVEBU_80X0_CP115_DEV_ID) + if (revision == MVEBU_80X0_DEV_ID || + revision == MVEBU_80X0_CP115_DEV_ID) return 2; else return 1; diff --git a/plat/marvell/a8k/common/mss/mss_pm_ipc.c b/plat/marvell/a8k/common/mss/mss_pm_ipc.c index 0088f8c1..6ff4abcc 100644 --- a/plat/marvell/a8k/common/mss/mss_pm_ipc.c +++ b/plat/marvell/a8k/common/mss/mss_pm_ipc.c @@ -1,9 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #include <debug.h> #include <mmio.h> #include <psci.h> @@ -12,14 +13,14 @@ #include <mss_pm_ipc.h> /* -** SISR is 32 bit interrupt register representing 32 interrupts -** -** +======+=============+=============+ -** + Bits + 31 + 30 - 00 + -** +======+=============+=============+ -** + Desc + MSS Msg Int + Reserved + -** +======+=============+=============+ -*/ + * SISR is 32 bit interrupt register representing 32 interrupts + * + * +======+=============+=============+ + * + Bits + 31 + 30 - 00 + + * +======+=============+=============+ + * + Desc + MSS Msg Int + Reserved + + * +======+=============+=============+ + */ #define MSS_SISR (MVEBU_REGS_BASE + 0x5800D0) #define MSS_SISTR (MVEBU_REGS_BASE + 0x5800D8) @@ -27,16 +28,20 @@ #define MSS_TIMER_BASE (MVEBU_REGS_BASE_MASK + 0x580110) #define MSS_TRIGGER_TIMEOUT (1000) -/******************************************************************************* -* mss_pm_ipc_msg_send -* -* DESCRIPTION: create and transmit IPC message -*******************************************************************************/ -int mss_pm_ipc_msg_send(unsigned int channel_id, unsigned int msg_id, const psci_power_state_t *target_state) +/***************************************************************************** + * mss_pm_ipc_msg_send + * + * DESCRIPTION: create and transmit IPC message + ***************************************************************************** + */ +int mss_pm_ipc_msg_send(unsigned int channel_id, unsigned int msg_id, + const psci_power_state_t *target_state) { /* Transmit IPC message */ #ifndef DISABLE_CLUSTER_LEVEL - mv_pm_ipc_msg_tx(channel_id, msg_id, (unsigned int)target_state->pwr_domain_state[MPIDR_AFFLVL1]); + mv_pm_ipc_msg_tx(channel_id, msg_id, + (unsigned int)target_state->pwr_domain_state[ + MPIDR_AFFLVL1]); #else mv_pm_ipc_msg_tx(channel_id, msg_id, 0); #endif @@ -44,11 +49,12 @@ int mss_pm_ipc_msg_send(unsigned int channel_id, unsigned int msg_id, const psci return 0; } -/******************************************************************************* -* mss_pm_ipc_msg_trigger -* -* DESCRIPTION: Trigger IPC message interrupt to MSS -*******************************************************************************/ +/***************************************************************************** + * mss_pm_ipc_msg_trigger + * + * DESCRIPTION: Trigger IPC message interrupt to MSS + ***************************************************************************** + */ int mss_pm_ipc_msg_trigger(void) { unsigned int timeout; @@ -65,7 +71,8 @@ int mss_pm_ipc_msg_trigger(void) /* check timeout */ t_end = mmio_read_32(MSS_TIMER_BASE); - timeout = ((t_start > t_end) ? (t_start - t_end) : (t_end - t_start)); + timeout = ((t_start > t_end) ? + (t_start - t_end) : (t_end - t_start)); if (timeout > MSS_TRIGGER_TIMEOUT) { ERROR("PM MSG Trigger Timeout\n"); break; diff --git a/plat/marvell/a8k/common/mss/mss_pm_ipc.h b/plat/marvell/a8k/common/mss/mss_pm_ipc.h index b1b9cfc6..0f694570 100644 --- a/plat/marvell/a8k/common/mss/mss_pm_ipc.h +++ b/plat/marvell/a8k/common/mss/mss_pm_ipc.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses @@ -15,19 +15,20 @@ /***************************************************************************** -* mss_pm_ipc_msg_send -* -* DESCRIPTION: create and transmit IPC message -****************************************************************************** -*/ -int mss_pm_ipc_msg_send(unsigned int channel_id, unsigned int msg_id, const psci_power_state_t *target_state); + * mss_pm_ipc_msg_send + * + * DESCRIPTION: create and transmit IPC message + ***************************************************************************** + */ +int mss_pm_ipc_msg_send(unsigned int channel_id, unsigned int msg_id, + const psci_power_state_t *target_state); /***************************************************************************** -* mss_pm_ipc_msg_trigger -* -* DESCRIPTION: Trigger IPC message interrupt to MSS -****************************************************************************** -*/ + * mss_pm_ipc_msg_trigger + * + * DESCRIPTION: Trigger IPC message interrupt to MSS + ***************************************************************************** + */ int mss_pm_ipc_msg_trigger(void); diff --git a/plat/marvell/a8k/common/plat_bl1_setup.c b/plat/marvell/a8k/common/plat_bl1_setup.c index ba8a4f78..5d851027 100644 --- a/plat/marvell/a8k/common/plat_bl1_setup.c +++ b/plat/marvell/a8k/common/plat_bl1_setup.c @@ -1,10 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ - + #include <mmio.h> #include <plat_marvell.h> diff --git a/plat/marvell/a8k/common/plat_bl31_setup.c b/plat/marvell/a8k/common/plat_bl31_setup.c index 7d510645..7985e1d9 100644 --- a/plat/marvell/a8k/common/plat_bl31_setup.c +++ b/plat/marvell/a8k/common/plat_bl31_setup.c @@ -1,19 +1,19 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ +#include <armada_common.h> #include <ap_setup.h> #include <cp110_setup.h> #include <debug.h> +#include <marvell_plat_priv.h> #include <marvell_pm.h> #include <mmio.h> #include <mci.h> -#include <plat_config.h> #include <plat_marvell.h> -#include <plat_private.h> #include <mc_trustzone/mc_trustzone.h> #include <mss_ipc_drv.h> @@ -57,7 +57,7 @@ void marvell_bl31_mss_init(void) (struct mss_pm_ctrl_block *)MSS_SRAM_PM_CONTROL_BASE; /* Check that the image was loaded successfully */ - if (mss_pm_crtl->handshake != HOST_ACKNOWLEDGEMENT) { + if (mss_pm_crtl->handshake != HOST_ACKNOWLEDGMENT) { NOTICE("MSS PM is not supported in this build\n"); return; } diff --git a/plat/marvell/a8k/common/plat_ble_setup.c b/plat/marvell/a8k/common/plat_ble_setup.c index 359524e5..29d896a3 100644 --- a/plat/marvell/a8k/common/plat_ble_setup.c +++ b/plat/marvell/a8k/common/plat_ble_setup.c @@ -1,19 +1,19 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ #include <ap_setup.h> +#include <armada_common.h> #include <aro.h> #include <ccu.h> #include <cp110_setup.h> #include <debug.h> #include <io_win.h> #include <mv_ddr_if.h> -#include <plat_config.h> -#include <plat_def.h> +#include <mvebu_def.h> #include <plat_marvell.h> /* Register for skip image use */ @@ -84,18 +84,18 @@ #define AP807_CPU_ARO_SEL_PLL_MASK (0x1 << AP807_CPU_ARO_SEL_PLL_OFFSET) /* - - AVS work points in the LD0 eFuse: - SVC1 work point: LD0[88:81] - SVC2 work point: LD0[96:89] - SVC3 work point: LD0[104:97] - SVC4 work point: LD0[112:105] - - Identification information in the LD-0 eFuse: - DRO: LD0[74:65] - Not used by the SW - Revision: LD0[78:75] - Not used by the SW - Bin: LD0[80:79] - Not used by the SW - SW Revision: LD0[115:113] - Cluster 1 PWR: LD0[193] - if set to 1, power down CPU Cluster-1 - resulting in 2 CPUs active only (7020) + * - AVS work points in the LD0 eFuse: + * SVC1 work point: LD0[88:81] + * SVC2 work point: LD0[96:89] + * SVC3 work point: LD0[104:97] + * SVC4 work point: LD0[112:105] + * - Identification information in the LD-0 eFuse: + * DRO: LD0[74:65] - Not used by the SW + * Revision: LD0[78:75] - Not used by the SW + * Bin: LD0[80:79] - Not used by the SW + * SW Revision: LD0[115:113] + * Cluster 1 PWR: LD0[193] - if set to 1, power down CPU Cluster-1 + * resulting in 2 CPUs active only (7020) */ #define MVEBU_AP_LD_EFUSE_BASE (MVEBU_AP_GEN_MGMT_BASE + 0xF00) /* Bits [94:63] - 32 data bits total */ @@ -128,7 +128,8 @@ static unsigned int ble_get_ap_type(void) unsigned int chip_rev_id; chip_rev_id = mmio_read_32(MVEBU_CSS_GWD_CTRL_IIDR2_REG); - chip_rev_id = ((chip_rev_id & GWD_IIDR2_CHIP_ID_MASK) >> GWD_IIDR2_CHIP_ID_OFFSET); + chip_rev_id = ((chip_rev_id & GWD_IIDR2_CHIP_ID_MASK) >> + GWD_IIDR2_CHIP_ID_OFFSET); return chip_rev_id; } @@ -136,15 +137,15 @@ static unsigned int ble_get_ap_type(void) /****************************************************************************** * The routine allows to save the CCU and IO windows configuration during DRAM * setup and restore them afterwards before exiting the BLE stage. - * Such window configuration is requred since not all default settings coming - * from the HW and the BootROM allow access to periferals connected to + * Such window configuration is required since not all default settings coming + * from the HW and the BootROM allow access to peripherals connected to * all available CPn components. * For instance, when the boot device is located on CP0, the IO window to CP1 * is not opened automatically by the HW and if the DRAM SPD is located on CP1 * i2c channel, it cannot be read at BLE stage. * Therefore the DRAM init procedure have to provide access to all available - * CPn periferals during the BLE stage by setting the CCU IO window to all CPn - * addresses and by enabling the IO windows accordingly. + * CPn peripherals during the BLE stage by setting the CCU IO window to all + * CPnph addresses and by enabling the IO windows accordingly. * Additionally this function configures the CCU GCR to DRAM, which allows * usage or more than 4GB DRAM as it configured by the default CCU DRAM window. * @@ -163,28 +164,30 @@ static void ble_plat_mmap_config(int restore) /* Restore CCU */ iow_restore_win_all(MVEBU_AP0); return; - } else { + } + /* Store original values */ ccu_save_win_all(MVEBU_AP0); /* Save CCU */ iow_save_win_all(MVEBU_AP0); - } init_ccu(MVEBU_AP0); /* The configuration saved, now all the changes can be done */ init_io_win(MVEBU_AP0); } -/****************************************************************************** +/**************************************************************************** * Setup Adaptive Voltage Switching - this is required for some platforms - *****************************************************************************/ + **************************************************************************** + */ static void ble_plat_avs_config(void) { uint32_t reg_val, device_id; /* Due to a bug in A3900 device_id we need a special handling here */ if (ble_get_ap_type() == CHIP_ID_AP807) { - VERBOSE("AVS: Setting AP807 AVS CTRL to 0x%x\n", AVS_A3900_CLK_VALUE); + VERBOSE("AVS: Setting AP807 AVS CTRL to 0x%x\n", + AVS_A3900_CLK_VALUE); mmio_write_32(AVS_EN_CTRL_REG, AVS_A3900_CLK_VALUE); return; } @@ -213,16 +216,18 @@ static void ble_plat_avs_config(void) } } -/****************************************************************************** +/**************************************************************************** * SVC flow - v0.10 - * The feature is inteded to configure AVS value according to eFuse values + * The feature is intended to configure AVS value according to eFuse values * that are burned individually for each SoC during the test process. - * Primary AVS value is stored in HD efuse and processed on power on by the HW engine + * Primary AVS value is stored in HD efuse and processed on power on + * by the HW engine * Secondary AVS value is located in LD efuse and contains 4 work points for * various CPU frequencies. * The Secondary AVS value is only taken into account if the SW Revision stored * in the efuse is greater than 0 and the CPU is running in a certain speed. - *****************************************************************************/ + **************************************************************************** + */ static void ble_plat_svc_config(void) { uint32_t reg_val, avs_workpoint, freq_pidi_mode; @@ -468,7 +473,7 @@ static int ble_skip_current_image(void) struct skip_image *skip_im; /*fetching skip image info*/ - skip_im = (struct skip_image *)plat_get_skip_image_data(); + skip_im = (struct skip_image *)plat_marvell_get_skip_image_data(); if (skip_im == NULL) return 0; @@ -526,7 +531,7 @@ int ble_plat_setup(int *skip) /* * Save the current CCU configuration and make required changes: * - Allow access to DRAM larger than 4GB - * - Open memory access to all CPn periferals + * - Open memory access to all CPn peripherals */ ble_plat_mmap_config(MMAP_SAVE_AND_CONFIG); @@ -557,7 +562,7 @@ int ble_plat_setup(int *skip) ap_ble_init(); /* Update DRAM topology (scan DIMM SPDs) */ - plat_dram_update_topology(); + plat_marvell_dram_update_topology(); /* Kick it in */ ret = dram_init(); diff --git a/plat/marvell/a8k/common/plat_pm.c b/plat/marvell/a8k/common/plat_pm.c index 7fcbfa36..f57d18a6 100644 --- a/plat/marvell/a8k/common/plat_pm.c +++ b/plat/marvell/a8k/common/plat_pm.c @@ -5,6 +5,7 @@ * https://spdx.org/licenses */ +#include <armada_common.h> #include <assert.h> #include <bakery_lock.h> #include <debug.h> @@ -15,7 +16,6 @@ #include <marvell_pm.h> #include <mmio.h> #include <mss_pm_ipc.h> -#include <plat_config.h> #include <plat_marvell.h> #include <platform.h> #include <plat_pm_trace.h> @@ -58,7 +58,7 @@ DEFINE_BAKERY_LOCK(pm_sys_lock); /* Weak definitions may be overridden in specific board */ -#pragma weak plat_get_pm_cfg +#pragma weak plat_marvell_get_pm_cfg /* AP806 CPU power down /power up definitions */ enum CPU_ID { @@ -70,9 +70,11 @@ enum CPU_ID { #define REG_WR_VALIDATE_TIMEOUT (2000) -#define FEATURE_DISABLE_STATUS_REG (MVEBU_REGS_BASE + 0x6F8230) +#define FEATURE_DISABLE_STATUS_REG \ + (MVEBU_REGS_BASE + 0x6F8230) #define FEATURE_DISABLE_STATUS_CPU_CLUSTER_OFFSET 4 -#define FEATURE_DISABLE_STATUS_CPU_CLUSTER_MASK (0x1 << FEATURE_DISABLE_STATUS_CPU_CLUSTER_OFFSET) +#define FEATURE_DISABLE_STATUS_CPU_CLUSTER_MASK \ + (0x1 << FEATURE_DISABLE_STATUS_CPU_CLUSTER_OFFSET) #ifdef MVEBU_SOC_AP807 #define PWRC_CPUN_CR_PWR_DN_RQ_OFFSET 1 @@ -82,21 +84,29 @@ enum CPU_ID { #define PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET 31 #endif -#define PWRC_CPUN_CR_REG(cpu_id) (MVEBU_REGS_BASE + 0x680000 + (cpu_id * 0x10)) -#define PWRC_CPUN_CR_PWR_DN_RQ_MASK (0x1 << PWRC_CPUN_CR_PWR_DN_RQ_OFFSET) +#define PWRC_CPUN_CR_REG(cpu_id) \ + (MVEBU_REGS_BASE + 0x680000 + (cpu_id * 0x10)) +#define PWRC_CPUN_CR_PWR_DN_RQ_MASK \ + (0x1 << PWRC_CPUN_CR_PWR_DN_RQ_OFFSET) #define PWRC_CPUN_CR_ISO_ENABLE_OFFSET 16 -#define PWRC_CPUN_CR_ISO_ENABLE_MASK (0x1 << PWRC_CPUN_CR_ISO_ENABLE_OFFSET) -#define PWRC_CPUN_CR_LDO_BYPASS_RDY_MASK (0x1 << PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET) +#define PWRC_CPUN_CR_ISO_ENABLE_MASK \ + (0x1 << PWRC_CPUN_CR_ISO_ENABLE_OFFSET) +#define PWRC_CPUN_CR_LDO_BYPASS_RDY_MASK \ + (0x1 << PWRC_CPUN_CR_LDO_BYPASS_RDY_OFFSET) -#define CCU_B_PRCRN_REG(cpu_id) (MVEBU_REGS_BASE + 0x1A50 + \ +#define CCU_B_PRCRN_REG(cpu_id) \ + (MVEBU_REGS_BASE + 0x1A50 + \ ((cpu_id / 2) * (0x400)) + ((cpu_id % 2) * 4)) #define CCU_B_PRCRN_CPUPORESET_STATIC_OFFSET 0 -#define CCU_B_PRCRN_CPUPORESET_STATIC_MASK (0x1 << CCU_B_PRCRN_CPUPORESET_STATIC_OFFSET) +#define CCU_B_PRCRN_CPUPORESET_STATIC_MASK \ + (0x1 << CCU_B_PRCRN_CPUPORESET_STATIC_OFFSET) /* power switch fingers */ -#define AP807_PWRC_LDO_CR0_REG (MVEBU_REGS_BASE + 0x680000 + 0x100) +#define AP807_PWRC_LDO_CR0_REG \ + (MVEBU_REGS_BASE + 0x680000 + 0x100) #define AP807_PWRC_LDO_CR0_OFFSET 16 -#define AP807_PWRC_LDO_CR0_MASK (0xff << AP807_PWRC_LDO_CR0_OFFSET) +#define AP807_PWRC_LDO_CR0_MASK \ + (0xff << AP807_PWRC_LDO_CR0_OFFSET) #define AP807_PWRC_LDO_CR0_VAL 0xfd /* @@ -456,7 +466,7 @@ static void a8k_pwr_domain_off(const psci_power_state_t *target_state) } /* Get PM config to power off the SoC */ -void *plat_get_pm_cfg(void) +void *plat_marvell_get_pm_cfg(void) { return NULL; } @@ -468,9 +478,9 @@ void *plat_get_pm_cfg(void) * the system recovery * */ -static void plat_exit_bootrom(void) +static void plat_marvell_exit_bootrom(void) { - exit_bootrom(PLAT_MARVELL_TRUSTED_ROM_BASE); + marvell_exit_bootrom(PLAT_MARVELL_TRUSTED_ROM_BASE); } /* @@ -607,12 +617,13 @@ static void a8k_pwr_domain_suspend(const psci_power_state_t *target_state) gicv2_cpuif_disable(); mailbox[MBOX_IDX_SUSPEND_MAGIC] = MVEBU_MAILBOX_SUSPEND_STATE; - mailbox[MBOX_IDX_ROM_EXIT_ADDR] = (uintptr_t)&plat_exit_bootrom; + mailbox[MBOX_IDX_ROM_EXIT_ADDR] = + (uintptr_t)&plat_marvell_exit_bootrom; #if PLAT_MARVELL_SHARED_RAM_CACHED flush_dcache_range(PLAT_MARVELL_MAILBOX_BASE + - MBOX_IDX_SUSPEND_MAGIC * sizeof(uintptr_t), - 2 * sizeof(uintptr_t)); + MBOX_IDX_SUSPEND_MAGIC * sizeof(uintptr_t), + 2 * sizeof(uintptr_t)); #endif /* Flush and disable LLC before going off-power */ llc_disable(0); @@ -636,7 +647,7 @@ static void a8k_pwr_domain_suspend(const psci_power_state_t *target_state) static void a8k_pwr_domain_on_finish(const psci_power_state_t *target_state) { /* arch specific configuration */ - psci_arch_init(0); + marvell_psci_arch_init(0); /* Interrupt initialization */ gicv2_pcpu_distif_init(); @@ -656,11 +667,12 @@ static void a8k_pwr_domain_on_finish(const psci_power_state_t *target_state) * context. Need to implement a separate suspend finisher. ***************************************************************************** */ -static void a8k_pwr_domain_suspend_finish(const psci_power_state_t *target_state) +static void a8k_pwr_domain_suspend_finish( + const psci_power_state_t *target_state) { if (is_pm_fw_running()) { /* arch specific configuration */ - psci_arch_init(0); + marvell_psci_arch_init(0); /* Interrupt initialization */ gicv2_cpuif_enable(); @@ -714,7 +726,7 @@ static void __dead2 a8k_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state) { const struct power_off_method *pm_cfg = - (const struct power_off_method *)plat_get_pm_cfg(); + (const struct power_off_method *)plat_marvell_get_pm_cfg(); unsigned int srcmd; unsigned int sdram_reg; register_t gpio_data = 0, gpio_addr = 0; @@ -782,9 +794,6 @@ static void __dead2 a8k_system_off(void) { ERROR("%s: needs to be implemented\n", __func__); panic(); - wfi(); - ERROR("%s: operation not handled.\n", __func__); - panic(); } void plat_marvell_system_reset(void) diff --git a/plat/marvell/a8k/common/plat_pm_trace.c b/plat/marvell/a8k/common/plat_pm_trace.c index b797f77e..683e56f6 100644 --- a/plat/marvell/a8k/common/plat_pm_trace.c +++ b/plat/marvell/a8k/common/plat_pm_trace.c @@ -1,9 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #include <mmio.h> #include <mss_mem.h> #include <platform.h> diff --git a/plat/marvell/a8k/common/plat_thermal.c b/plat/marvell/a8k/common/plat_thermal.c index fe6de66b..02fe8209 100644 --- a/plat/marvell/a8k/common/plat_thermal.c +++ b/plat/marvell/a8k/common/plat_thermal.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2017 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses @@ -8,22 +8,27 @@ #include <debug.h> #include <delay_timer.h> #include <mmio.h> -#include <plat_def.h> +#include <mvebu_def.h> #include <thermal.h> #define THERMAL_TIMEOUT 1200 #define THERMAL_SEN_CTRL_LSB_STRT_OFFSET 0 -#define THERMAL_SEN_CTRL_LSB_STRT_MASK (0x1 << THERMAL_SEN_CTRL_LSB_STRT_OFFSET) +#define THERMAL_SEN_CTRL_LSB_STRT_MASK \ + (0x1 << THERMAL_SEN_CTRL_LSB_STRT_OFFSET) #define THERMAL_SEN_CTRL_LSB_RST_OFFSET 1 -#define THERMAL_SEN_CTRL_LSB_RST_MASK (0x1 << THERMAL_SEN_CTRL_LSB_RST_OFFSET) +#define THERMAL_SEN_CTRL_LSB_RST_MASK \ + (0x1 << THERMAL_SEN_CTRL_LSB_RST_OFFSET) #define THERMAL_SEN_CTRL_LSB_EN_OFFSET 2 -#define THERMAL_SEN_CTRL_LSB_EN_MASK (0x1 << THERMAL_SEN_CTRL_LSB_EN_OFFSET) +#define THERMAL_SEN_CTRL_LSB_EN_MASK \ + (0x1 << THERMAL_SEN_CTRL_LSB_EN_OFFSET) #define THERMAL_SEN_CTRL_STATS_VALID_OFFSET 16 -#define THERMAL_SEN_CTRL_STATS_VALID_MASK (0x1 << THERMAL_SEN_CTRL_STATS_VALID_OFFSET) +#define THERMAL_SEN_CTRL_STATS_VALID_MASK \ + (0x1 << THERMAL_SEN_CTRL_STATS_VALID_OFFSET) #define THERMAL_SEN_CTRL_STATS_TEMP_OUT_OFFSET 0 -#define THERMAL_SEN_CTRL_STATS_TEMP_OUT_MASK (0x3FF << THERMAL_SEN_CTRL_STATS_TEMP_OUT_OFFSET) +#define THERMAL_SEN_CTRL_STATS_TEMP_OUT_MASK \ + (0x3FF << THERMAL_SEN_CTRL_STATS_TEMP_OUT_OFFSET) #define THERMAL_SEN_OUTPUT_MSB 512 #define THERMAL_SEN_OUTPUT_COMP 1024 @@ -55,7 +60,8 @@ static int ext_tsen_probe(struct tsen_config *tsen_cfg) mmio_write_32((uintptr_t)&base->ext_tsen_ctrl_lsb, reg); reg = mmio_read_32((uintptr_t)&base->ext_tsen_status); - while ((reg & THERMAL_SEN_CTRL_STATS_VALID_MASK) == 0 && timeout < THERMAL_TIMEOUT) { + while ((reg & THERMAL_SEN_CTRL_STATS_VALID_MASK) == 0 && + timeout < THERMAL_TIMEOUT) { udelay(100); reg = mmio_read_32((uintptr_t)&base->ext_tsen_status); timeout++; @@ -68,7 +74,7 @@ static int ext_tsen_probe(struct tsen_config *tsen_cfg) tsen_cfg->tsen_ready = 1; - INFO("thermal sensor was initialized\n"); + VERBOSE("thermal sensor was initialized\n"); return 0; } @@ -85,7 +91,8 @@ static int ext_tsen_read(struct tsen_config *tsen_cfg, int *temp) base = (struct tsen_regs *)tsen_cfg->regs_base; reg = mmio_read_32((uintptr_t)&base->ext_tsen_status); - reg = ((reg & THERMAL_SEN_CTRL_STATS_TEMP_OUT_MASK) >> THERMAL_SEN_CTRL_STATS_TEMP_OUT_OFFSET); + reg = ((reg & THERMAL_SEN_CTRL_STATS_TEMP_OUT_MASK) >> + THERMAL_SEN_CTRL_STATS_TEMP_OUT_OFFSET); /* * TSEN output format is signed as a 2s complement number diff --git a/plat/marvell/common/aarch64/marvell_common.c b/plat/marvell/common/aarch64/marvell_common.c index fe662c5c..abc501a9 100644 --- a/plat/marvell/common/aarch64/marvell_common.c +++ b/plat/marvell/common/aarch64/marvell_common.c @@ -1,14 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -/* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ + #include <arch.h> #include <arch_helpers.h> #include <assert.h> @@ -90,9 +86,10 @@ unsigned long plat_get_ns_image_entrypoint(void) return PLAT_MARVELL_NS_IMAGE_OFFSET; } -/******************************************************************************* +/***************************************************************************** * Gets SPSR for BL32 entry - ******************************************************************************/ + ***************************************************************************** + */ uint32_t marvell_get_spsr_for_bl32_entry(void) { /* @@ -102,9 +99,10 @@ uint32_t marvell_get_spsr_for_bl32_entry(void) return 0; } -/******************************************************************************* +/***************************************************************************** * Gets SPSR for BL33 entry - ******************************************************************************/ + ***************************************************************************** + */ uint32_t marvell_get_spsr_for_bl33_entry(void) { unsigned long el_status; @@ -126,9 +124,10 @@ uint32_t marvell_get_spsr_for_bl33_entry(void) return spsr; } -/******************************************************************************* +/***************************************************************************** * Returns ARM platform specific memory map regions. - ******************************************************************************/ + ***************************************************************************** + */ const mmap_region_t *plat_marvell_get_mmap(void) { return plat_marvell_mmap; diff --git a/plat/marvell/common/aarch64/marvell_helpers.S b/plat/marvell/common/aarch64/marvell_helpers.S index 45bd2a2c..a3dc917c 100644 --- a/plat/marvell/common/aarch64/marvell_helpers.S +++ b/plat/marvell/common/aarch64/marvell_helpers.S @@ -1,39 +1,12 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -/* - * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of ARM nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - */ + #include <asm_macros.S> +#include <cortex_a72.h> #include <marvell_def.h> #include <platform_def.h> #ifndef PLAT_a3700 @@ -52,7 +25,8 @@ .globl disable_sram .globl disable_icache .globl invalidate_icache_all - .globl exit_bootrom + .globl marvell_exit_bootrom + .globl ca72_l2_enable_unique_clean /* ----------------------------------------------------- * unsigned int plat_my_core_pos(void) @@ -202,7 +176,7 @@ endfunc disable_sram * Disable and invalidate the icache * ----------------------------------------------------- */ -func exit_bootrom +func marvell_exit_bootrom /* Save the system restore address */ mov x28, x0 @@ -234,4 +208,16 @@ func exit_bootrom mov x0, x28 br x0 -endfunc exit_bootrom +endfunc marvell_exit_bootrom + + /* + * Enable L2 UniqueClean evictions with data + */ +func ca72_l2_enable_unique_clean + + mrs x0, CORTEX_A72_L2ACTLR_EL1 + orr x0, x0, #CORTEX_A72_L2ACTLR_ENABLE_UNIQUE_CLEAN + msr CORTEX_A72_L2ACTLR_EL1, x0 + + ret +endfunc ca72_l2_enable_unique_clean diff --git a/plat/marvell/common/marvell_bl1_setup.c b/plat/marvell/common/marvell_bl1_setup.c index 73ebd21c..7b498dd0 100644 --- a/plat/marvell/common/marvell_bl1_setup.c +++ b/plat/marvell/common/marvell_bl1_setup.c @@ -1,9 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ + #include <bl1.h> #include <bl1/bl1_private.h> #include <bl_common.h> diff --git a/plat/marvell/common/marvell_bl2_setup.c b/plat/marvell/common/marvell_bl2_setup.c index 6a91b572..7c87ce33 100644 --- a/plat/marvell/common/marvell_bl2_setup.c +++ b/plat/marvell/common/marvell_bl2_setup.c @@ -1,14 +1,9 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -/* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ #include <arch_helpers.h> #include <bl_common.h> @@ -22,11 +17,12 @@ static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE); -/******************************************************************************* +/***************************************************************************** * This structure represents the superset of information that is passed to * BL31, e.g. while passing control to it from BL2, bl31_params - * and other platform specific params - ******************************************************************************/ + * and other platform specific parameters + ***************************************************************************** + */ typedef struct bl2_to_bl31_params_mem { bl31_params_t bl31_params; image_info_t bl31_image_info; @@ -62,7 +58,7 @@ meminfo_t *bl2_plat_sec_mem_layout(void) return &bl2_tzram_layout; } -/******************************************************************************* +/***************************************************************************** * This function assigns a pointer to the memory that the platform has kept * aside to pass platform specific and trusted firmware related information * to BL31. This memory is allocated by allocating memory to @@ -70,7 +66,8 @@ meminfo_t *bl2_plat_sec_mem_layout(void) * structure whose information is passed to BL31 * NOTE: This function should be called only once and should be done * before generating params to BL31 - ******************************************************************************/ + ***************************************************************************** + */ bl31_params_t *bl2_plat_get_bl31_params(void) { bl31_params_t *bl2_to_bl31_params; @@ -122,10 +119,11 @@ void bl2_plat_flush_bl31_params(void) sizeof(bl2_to_bl31_params_mem_t)); } -/******************************************************************************* +/***************************************************************************** * This function returns a pointer to the shared memory that the platform * has kept to point to entry point information of BL31 to BL2 - ******************************************************************************/ + ***************************************************************************** + */ struct entry_point_info *bl2_plat_get_bl31_ep_info(void) { #if DEBUG @@ -135,11 +133,12 @@ struct entry_point_info *bl2_plat_get_bl31_ep_info(void) return &bl31_params_mem.bl31_ep_info; } -/******************************************************************************* +/***************************************************************************** * BL1 has passed the extents of the trusted SRAM that should be visible to BL2 * in x0. This memory layout is sitting at the base of the free trusted SRAM. * Copy it to a safe location before its reclaimed by later BL2 functionality. - ******************************************************************************/ + ***************************************************************************** + */ void marvell_bl2_early_platform_setup(meminfo_t *mem_layout) { /* Initialize the console to provide early debug support */ @@ -164,10 +163,11 @@ void bl2_platform_setup(void) /* Nothing to do */ } -/******************************************************************************* +/***************************************************************************** * Perform the very early platform specific architectural setup here. At the * moment this is only initializes the mmu in a quick and dirty way. - ******************************************************************************/ + ***************************************************************************** + */ void marvell_bl2_plat_arch_setup(void) { marvell_setup_page_tables(bl2_tzram_layout.total_base, @@ -189,32 +189,35 @@ void bl2_plat_arch_setup(void) marvell_bl2_plat_arch_setup(); } -/******************************************************************************* +/***************************************************************************** * Populate the extents of memory available for loading SCP_BL2 (if used), * i.e. anywhere in trusted RAM as long as it doesn't overwrite BL2. - ******************************************************************************/ + ***************************************************************************** + */ void bl2_plat_get_scp_bl2_meminfo(meminfo_t *scp_bl2_meminfo) { *scp_bl2_meminfo = bl2_tzram_layout; } -/******************************************************************************* +/***************************************************************************** * Before calling this function BL31 is loaded in memory and its entrypoint * is set by load_image. This is a placeholder for the platform to change * the entrypoint of BL31 and set SPSR and security state. * On MARVELL std. platforms we only set the security state of the entrypoint - ******************************************************************************/ + ***************************************************************************** + */ void bl2_plat_set_bl31_ep_info(image_info_t *bl31_image_info, - entry_point_info_t *bl31_ep_info) + entry_point_info_t *bl31_ep_info) { SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE); bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS); } -/******************************************************************************* +/***************************************************************************** * Populate the extents of memory available for loading BL32 - ******************************************************************************/ + ***************************************************************************** + */ #ifdef BL32_BASE void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo) { @@ -230,36 +233,39 @@ void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo) } #endif -/******************************************************************************* +/***************************************************************************** * Before calling this function BL32 is loaded in memory and its entrypoint * is set by load_image. This is a placeholder for the platform to change * the entrypoint of BL32 and set SPSR and security state. * On MARVELL std. platforms we only set the security state of the entrypoint - ******************************************************************************/ + ***************************************************************************** + */ void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info, - entry_point_info_t *bl32_ep_info) + entry_point_info_t *bl32_ep_info) { SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE); bl32_ep_info->spsr = marvell_get_spsr_for_bl32_entry(); } -/******************************************************************************* +/***************************************************************************** * Before calling this function BL33 is loaded in memory and its entrypoint * is set by load_image. This is a placeholder for the platform to change * the entrypoint of BL33 and set SPSR and security state. * On MARVELL std. platforms we only set the security state of the entrypoint - ******************************************************************************/ + ***************************************************************************** + */ void bl2_plat_set_bl33_ep_info(image_info_t *image, - entry_point_info_t *bl33_ep_info) + entry_point_info_t *bl33_ep_info) { SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE); bl33_ep_info->spsr = marvell_get_spsr_for_bl33_entry(); } -/******************************************************************************* +/***************************************************************************** * Populate the extents of memory available for loading BL33 - ******************************************************************************/ + ***************************************************************************** + */ void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo) { bl33_meminfo->total_base = MARVELL_DRAM_BASE; diff --git a/plat/marvell/common/marvell_bl31_setup.c b/plat/marvell/common/marvell_bl31_setup.c index d281356a..a74816b7 100644 --- a/plat/marvell/common/marvell_bl31_setup.c +++ b/plat/marvell/common/marvell_bl31_setup.c @@ -1,21 +1,17 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -/* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ + #include <arch.h> #include <assert.h> #include <console.h> #include <debug.h> #include <marvell_def.h> +#include <marvell_plat_priv.h> #include <plat_marvell.h> -#include <plat_private.h> #include <platform.h> #ifdef USE_CCI @@ -45,12 +41,13 @@ static entry_point_info_t bl33_image_ep_info; #pragma weak bl31_plat_get_next_image_ep_info #pragma weak plat_get_syscnt_freq2 -/******************************************************************************* +/***************************************************************************** * Return a pointer to the 'entry_point_info' structure of the next image for * the security state specified. BL33 corresponds to the non-secure image type * while BL32 corresponds to the secure image type. A NULL pointer is returned * if the image does not exist. - ******************************************************************************/ + ***************************************************************************** + */ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) { entry_point_info_t *next_image_info; @@ -62,14 +59,15 @@ entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type) return next_image_info; } -/******************************************************************************* +/***************************************************************************** * Perform any BL31 early platform setup common to ARM standard platforms. * Here is an opportunity to copy parameters passed by the calling EL (S-EL1 * in BL2 & S-EL3 in BL1) before they are lost (potentially). This needs to be * done before the MMU is initialized so that the memory layout can be used * while creating page tables. BL2 has flushed this information to memory, so * we are guaranteed to pick up good data. - ******************************************************************************/ + ***************************************************************************** + */ void marvell_bl31_early_platform_setup(bl31_params_t *from_bl2, void *plat_params_from_bl2) { @@ -153,9 +151,10 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2, #endif } -/******************************************************************************* +/***************************************************************************** * Perform any BL31 platform setup common to ARM standard platforms - ******************************************************************************/ + ***************************************************************************** + */ void marvell_bl31_platform_setup(void) { /* Initialize the GIC driver, cpu and distributor interfaces */ @@ -163,17 +162,18 @@ void marvell_bl31_platform_setup(void) plat_marvell_gic_init(); /* For Armada-8k-plus family, the SoC includes more than - ** a single AP die, but the default die that boots is AP #0. - ** For other families there is only one die (#0). - ** Initialize psci arch from die 0 - ** */ - psci_arch_init(0); + * a single AP die, but the default die that boots is AP #0. + * For other families there is only one die (#0). + * Initialize psci arch from die 0 + */ + marvell_psci_arch_init(0); } -/******************************************************************************* +/***************************************************************************** * Perform any BL31 platform runtime setup prior to BL31 exit common to ARM * standard platforms - ******************************************************************************/ + ***************************************************************************** + */ void marvell_bl31_plat_runtime_setup(void) { /* Initialize the runtime console */ @@ -192,12 +192,13 @@ void bl31_plat_runtime_setup(void) marvell_bl31_plat_runtime_setup(); } -/******************************************************************************* +/***************************************************************************** * Perform the very early platform specific architectural setup shared between * ARM standard platforms. This only does basic initialization. Later * architectural setup (bl31_arch_setup()) does not do anything platform * specific. - ******************************************************************************/ + ***************************************************************************** + */ void marvell_bl31_plat_arch_setup(void) { marvell_setup_page_tables(BL31_BASE, @@ -210,7 +211,7 @@ void marvell_bl31_plat_arch_setup(void) , BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END #endif - ); + ); #if BL31_CACHE_DISABLE enable_mmu_el3(DISABLE_DCACHE); diff --git a/plat/marvell/common/marvell_cci.c b/plat/marvell/common/marvell_cci.c index 95c6f265..2df48024 100755 --- a/plat/marvell/common/marvell_cci.c +++ b/plat/marvell/common/marvell_cci.c @@ -1,10 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ - + #include <cci.h> #include <plat_marvell.h> @@ -13,34 +13,38 @@ static const int cci_map[] = { PLAT_MARVELL_CCI_CLUSTER1_SL_IFACE_IX }; -/****************************************************************************** +/**************************************************************************** * The following functions are defined as weak to allow a platform to override * the way ARM CCI driver is initialised and used. - *****************************************************************************/ + **************************************************************************** + */ #pragma weak plat_marvell_interconnect_init #pragma weak plat_marvell_interconnect_enter_coherency #pragma weak plat_marvell_interconnect_exit_coherency -/****************************************************************************** +/**************************************************************************** * Helper function to initialize ARM CCI driver. - *****************************************************************************/ + **************************************************************************** + */ void plat_marvell_interconnect_init(void) { cci_init(PLAT_MARVELL_CCI_BASE, cci_map, ARRAY_SIZE(cci_map)); } -/****************************************************************************** +/**************************************************************************** * Helper function to place current master into coherency - *****************************************************************************/ + **************************************************************************** + */ void plat_marvell_interconnect_enter_coherency(void) { cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); } -/****************************************************************************** +/**************************************************************************** * Helper function to remove current master from coherency - *****************************************************************************/ + **************************************************************************** + */ void plat_marvell_interconnect_exit_coherency(void) { cci_disable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1())); diff --git a/plat/marvell/common/marvell_common.mk b/plat/marvell/common/marvell_common.mk index 2e03302e..3ee2f3db 100644 --- a/plat/marvell/common/marvell_common.mk +++ b/plat/marvell/common/marvell_common.mk @@ -1,4 +1,4 @@ -# Copyright (C) 2016 - 2018 Marvell International Ltd. +# Copyright (C) 2018 Marvell International Ltd. # # SPDX-License-Identifier: BSD-3-Clause # https://spdx.org/licenses @@ -20,8 +20,8 @@ $(eval $(call add_define,ARO_ENABLE)) LLC_ENABLE := 1 $(eval $(call add_define,LLC_ENABLE)) -PLAT_INCLUDES += -I. -Iinclude/common/tbbr \ - -I$(MARVELL_PLAT_INCLUDE_BASE)/common \ +PLAT_INCLUDES += -I. -Iinclude/common/tbbr \ + -I$(MARVELL_PLAT_INCLUDE_BASE)/common \ -I$(MARVELL_PLAT_INCLUDE_BASE)/common/aarch64 diff --git a/plat/marvell/common/marvell_ddr_info.c b/plat/marvell/common/marvell_ddr_info.c index ecbee3fb..68bff998 100644 --- a/plat/marvell/common/marvell_ddr_info.c +++ b/plat/marvell/common/marvell_ddr_info.c @@ -18,7 +18,8 @@ #define DRAM_AREA_LENGTH_OFFS 16 #define DRAM_AREA_LENGTH_MASK (0x1f << DRAM_AREA_LENGTH_OFFS) #define DRAM_START_ADDRESS_L_OFFS 23 -#define DRAM_START_ADDRESS_L_MASK (0x1ff << DRAM_START_ADDRESS_L_OFFS) +#define DRAM_START_ADDRESS_L_MASK \ + (0x1ff << DRAM_START_ADDRESS_L_OFFS) #define DRAM_START_ADDR_HTOL_OFFS 32 #define DRAM_MAX_CS_NUM 2 @@ -84,15 +85,21 @@ uint64_t mvebu_get_dram_size(uint64_t ap_base_addr) if (!DRAM_CS_ENABLED(iface, cs, ap_base_addr)) break; - /* Decode area length for current CS from register value */ - region_code = GET_DRAM_REGION_SIZE_CODE(iface, cs, ap_base_addr); + /* Decode area length for current CS + * from register value + */ + region_code = + GET_DRAM_REGION_SIZE_CODE(iface, cs, + ap_base_addr); if (DRAM_REGION_SIZE_EVEN(region_code)) { - mem_size += GET_DRAM_REGION_SIZE_EVEN(region_code); + mem_size += + GET_DRAM_REGION_SIZE_EVEN(region_code); } else if (DRAM_REGION_SIZE_ODD(region_code)) { - mem_size += GET_DRAM_REGION_SIZE_ODD(region_code); + mem_size += + GET_DRAM_REGION_SIZE_ODD(region_code); } else { - WARN("%s: Invalid memory region code (0x%x) for CS#%d\n", + WARN("%s: Invalid mem region (0x%x) CS#%d\n", __func__, region_code, cs); return 0; } diff --git a/plat/marvell/common/marvell_gicv2.c b/plat/marvell/common/marvell_gicv2.c index 3a667785..ba8e4096 100644 --- a/plat/marvell/common/marvell_gicv2.c +++ b/plat/marvell/common/marvell_gicv2.c @@ -1,14 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -/* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ + #include <gicv2.h> #include <plat_marvell.h> #include <platform.h> @@ -46,7 +42,7 @@ static gicv2_driver_data_t marvell_gic_data = { .target_masks_num = ARRAY_SIZE(target_mask_array), }; -/*/ +/* * ARM common helper to initialize the GICv2 only driver. */ void plat_marvell_gic_driver_init(void) diff --git a/plat/marvell/common/marvell_gicv3.c b/plat/marvell/common/marvell_gicv3.c index c4d2b3de..c15d115c 100644 --- a/plat/marvell/common/marvell_gicv3.c +++ b/plat/marvell/common/marvell_gicv3.c @@ -1,14 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -/* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ + #include <debug.h> #include <gicv3.h> #include <interrupt_props.h> @@ -121,7 +117,7 @@ void plat_marvell_gic_cpuif_disable(void) } /****************************************************************************** - * Marvell common helper to initialize the per-cpu redistributor interface in GICv3 + * Marvell common helper to init. the per-cpu redistributor interface in GICv3 *****************************************************************************/ void plat_marvell_gic_pcpu_init(void) { @@ -138,7 +134,7 @@ void plat_marvell_gic_irq_save(void) * If an ITS is available, save its context before * the Redistributor using: * gicv3_its_save_disable(gits_base, &its_ctx[i]) - * Additionnaly, an implementation-defined sequence may + * Additionally, an implementation-defined sequence may * be required to save the whole ITS state. */ diff --git a/plat/marvell/common/marvell_io_storage.c b/plat/marvell/common/marvell_io_storage.c index ca1d7675..cb9ece24 100644 --- a/plat/marvell/common/marvell_io_storage.c +++ b/plat/marvell/common/marvell_io_storage.c @@ -1,14 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -/* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ + #include <assert.h> #include <bl_common.h> /* For ARRAY_SIZE */ #include <debug.h> diff --git a/plat/marvell/common/marvell_pm.c b/plat/marvell/common/marvell_pm.c index 822d2bc6..2a757900 100644 --- a/plat/marvell/common/marvell_pm.c +++ b/plat/marvell/common/marvell_pm.c @@ -1,14 +1,10 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -/* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ + #include <arch_helpers.h> #include <assert.h> #include <psci.h> @@ -17,11 +13,12 @@ /* Standard ARM platforms are expected to export plat_arm_psci_pm_ops */ extern const plat_psci_ops_t plat_arm_psci_pm_ops; -/******************************************************************************* +/***************************************************************************** * Private function to program the mailbox for a cpu before it is released * from reset. This function assumes that the mail box base is within * the MARVELL_SHARED_RAM region - ******************************************************************************/ + ***************************************************************************** + */ void marvell_program_mailbox(uintptr_t address) { uintptr_t *mailbox = (void *)PLAT_MARVELL_MAILBOX_BASE; @@ -45,10 +42,11 @@ void marvell_program_mailbox(uintptr_t address) #endif } -/******************************************************************************* +/***************************************************************************** * The ARM Standard platform definition of platform porting API * `plat_setup_psci_ops`. - ******************************************************************************/ + ***************************************************************************** + */ int plat_setup_psci_ops(uintptr_t sec_entrypoint, const plat_psci_ops_t **psci_ops) { diff --git a/plat/marvell/common/marvell_topology.c b/plat/marvell/common/marvell_topology.c index 9418307a..a40ff6f5 100644 --- a/plat/marvell/common/marvell_topology.c +++ b/plat/marvell/common/marvell_topology.c @@ -1,23 +1,20 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -/* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ + #include <plat_marvell.h> /* The power domain tree descriptor */ unsigned char marvell_power_domain_tree_desc[PLAT_MARVELL_CLUSTER_COUNT + 1]; -/******************************************************************************* +/***************************************************************************** * This function dynamically constructs the topology according to * PLAT_MARVELL_CLUSTER_COUNT and returns it. - ******************************************************************************/ + ***************************************************************************** + */ const unsigned char *plat_get_power_domain_tree_desc(void) { int i; @@ -38,18 +35,20 @@ const unsigned char *plat_get_power_domain_tree_desc(void) return marvell_power_domain_tree_desc; } -/******************************************************************************* +/***************************************************************************** * This function validates an MPIDR by checking whether it falls within the * acceptable bounds. An error code (-1) is returned if an incorrect mpidr * is passed. - ******************************************************************************/ + ***************************************************************************** + */ int marvell_check_mpidr(u_register_t mpidr) { unsigned int nb_id, cluster_id, cpu_id; mpidr &= MPIDR_AFFINITY_MASK; - if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK | MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT)) + if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK | + MPIDR_AFFLVL_MASK << MPIDR_AFF2_SHIFT)) return -1; /* Get north bridge ID */ @@ -69,12 +68,13 @@ int marvell_check_mpidr(u_register_t mpidr) return 0; } -/******************************************************************************* - * This function implements a part of the critical interface between the psci +/***************************************************************************** + * This function implements a part of the critical interface between the PSCI * generic layer and the platform that allows the former to query the platform * to convert an MPIDR to a unique linear index. An error code (-1) is returned * in case the MPIDR is invalid. - ******************************************************************************/ + ***************************************************************************** + */ int plat_core_pos_by_mpidr(u_register_t mpidr) { if (marvell_check_mpidr(mpidr) == -1) diff --git a/plat/marvell/common/mrvl_sip_svc.c b/plat/marvell/common/mrvl_sip_svc.c index 4d79cd0d..ec293afa 100644 --- a/plat/marvell/common/mrvl_sip_svc.c +++ b/plat/marvell/common/mrvl_sip_svc.c @@ -8,10 +8,10 @@ #include <ap_setup.h> #include <cache_llc.h> #include <debug.h> +#include <marvell_plat_priv.h> #include <runtime_svc.h> #include <smcc.h> #include "comphy/phy-comphy-cp110.h" -#include <plat_private.h> /* #define DEBUG_COMPHY */ #ifdef DEBUG_COMPHY @@ -45,8 +45,8 @@ uintptr_t mrvl_sip_smc_handler(uint32_t smc_fid, u_register_t x2, u_register_t x3, u_register_t x4, - void *cookie, - void *handle, + void *cookie, + void *handle, u_register_t flags) { u_register_t ret; @@ -63,12 +63,14 @@ uintptr_t mrvl_sip_smc_handler(uint32_t smc_fid, x1 = (x1 & ~0xffffff) + MVEBU_COMPHY_OFFSET; if ((x1 & 0xffffff) != MVEBU_COMPHY_OFFSET) { - ERROR("%s: Wrong smc (0x%x) address: %lx\n", __func__, smc_fid, x1); + ERROR("%s: Wrong smc (0x%x) address: %lx\n", + __func__, smc_fid, x1); SMC_RET1(handle, SMC_UNK); } if (x2 >= MAX_LANE_NR) { - ERROR("%s: Wrong smc (0x%x) lane nr: %lx\n", __func__, smc_fid, x2); + ERROR("%s: Wrong smc (0x%x) lane nr: %lx\n", + __func__, smc_fid, x2); SMC_RET1(handle, SMC_UNK); } } diff --git a/plat/marvell/common/mss/mss_common.mk b/plat/marvell/common/mss/mss_common.mk index 83fe32c0..898b6dcc 100644 --- a/plat/marvell/common/mss/mss_common.mk +++ b/plat/marvell/common/mss/mss_common.mk @@ -1,35 +1,11 @@ # -# *************************************************************************** -# Copyright (C) 2016 Marvell International Ltd. -# *************************************************************************** +# Copyright (C) 2018 Marvell International Ltd. # -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions are met: -# -# Redistributions of source code must retain the above copyright notice, this -# list of conditions and the following disclaimer. -# -# Redistributions in binary form must reproduce the above copyright notice, -# this list of conditions and the following disclaimer in the documentation -# and/or other materials provided with the distribution. -# -# Neither the name of Marvell nor the names of its contributors may be used -# to endorse or promote products derived from this software without specific -# prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, -# OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -# POSSIBILITY OF SUCH DAMAGE. +# SPDX-License-Identifier: BSD-3-Clause +# https://spdx.org/licenses # + PLAT_MARVELL := plat/marvell MSS_SOURCE := $(PLAT_MARVELL)/common/mss diff --git a/plat/marvell/common/mss/mss_ipc_drv.c b/plat/marvell/common/mss/mss_ipc_drv.c index 5fde9243..731c315b 100644 --- a/plat/marvell/common/mss/mss_ipc_drv.c +++ b/plat/marvell/common/mss/mss_ipc_drv.c @@ -1,35 +1,8 @@ /* - * *************************************************************************** - * Copyright (C) 2016 Marvell International Ltd. - * *************************************************************************** + * Copyright (C) 2018 Marvell International Ltd. * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of Marvell nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, - * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *************************************************************************** + * SPDX-License-Identifier: BSD-3-Clause + * https://spdx.org/licenses */ #include <plat_marvell.h> @@ -46,10 +19,10 @@ unsigned long mv_pm_ipc_msg_base; unsigned int mv_pm_ipc_queue_size; -unsigned int msg_sync = 0; +unsigned int msg_sync; int msg_index = IPC_CH_MSG_IDX; -/******************************************************************************* +/****************************************************************************** * mss_pm_ipc_init * * DESCRIPTION: Initialize PM IPC infrastructure @@ -61,17 +34,19 @@ int mv_pm_ipc_init(unsigned long ipc_control_addr) (struct mss_pm_ipc_ctrl *)ipc_control_addr; /* Initialize PM IPC control block */ - mv_pm_ipc_msg_base = ipc_control->msg_base_address | IPC_MSG_BASE_MASK; + mv_pm_ipc_msg_base = ipc_control->msg_base_address | + IPC_MSG_BASE_MASK; mv_pm_ipc_queue_size = ipc_control->queue_size; return 0; } -/******************************************************************************* -* mv_pm_ipc_queue_addr_get -* -* DESCRIPTION: Returns the IPC queue address -*******************************************************************************/ +/****************************************************************************** + * mv_pm_ipc_queue_addr_get + * + * DESCRIPTION: Returns the IPC queue address + ****************************************************************************** + */ unsigned int mv_pm_ipc_queue_addr_get(void) { unsigned int addr; @@ -81,31 +56,35 @@ unsigned int mv_pm_ipc_queue_addr_get(void) if (msg_index >= IPC_CH_NUM_OF_MSG) msg_index = 0; - addr = (unsigned int)(mv_pm_ipc_msg_base + (msg_index * mv_pm_ipc_queue_size)); + addr = (unsigned int)(mv_pm_ipc_msg_base + + (msg_index * mv_pm_ipc_queue_size)); flush_dcache_range((uint64_t)&msg_index, sizeof(msg_index)); return addr; } -/******************************************************************************* -* mv_pm_ipc_msg_rx -* -* DESCRIPTION: Retrieve message from IPC channel -*******************************************************************************/ +/****************************************************************************** + * mv_pm_ipc_msg_rx + * + * DESCRIPTION: Retrieve message from IPC channel + ****************************************************************************** + */ int mv_pm_ipc_msg_rx(unsigned int channel_id, struct mss_pm_ipc_msg *msg) { unsigned int addr = mv_pm_ipc_queue_addr_get(); + msg->msg_reply = mmio_read_32(addr + IPC_MSG_REPLY_LOC); return 0; } -/******************************************************************************* -* mv_pm_ipc_msg_tx -* -* DESCRIPTION: Send message via IPC channel -*******************************************************************************/ +/****************************************************************************** + * mv_pm_ipc_msg_tx + * + * DESCRIPTION: Send message via IPC channel + ****************************************************************************** + */ int mv_pm_ipc_msg_tx(unsigned int channel_id, unsigned int msg_id, unsigned int cluster_power_state) { @@ -120,11 +99,12 @@ int mv_pm_ipc_msg_tx(unsigned int channel_id, unsigned int msg_id, mmio_write_32(addr + IPC_MSG_SYNC_ID_LOC, msg_sync); mmio_write_32(addr + IPC_MSG_ID_LOC, msg_id); mmio_write_32(addr + IPC_MSG_CPU_ID_LOC, channel_id); - mmio_write_32(addr + IPC_MSG_POWER_STATE_LOC, cluster_power_state); + mmio_write_32(addr + IPC_MSG_POWER_STATE_LOC, + cluster_power_state); mmio_write_32(addr + IPC_MSG_STATE_LOC, IPC_MSG_OCCUPY); } else { - printf("mv_pm_ipc_msg_tx failed!!!\n"); + ERROR("%s: FAILED\n", __func__); } return 0; diff --git a/plat/marvell/common/mss/mss_ipc_drv.h b/plat/marvell/common/mss/mss_ipc_drv.h index ff8508ac..28eb907e 100644 --- a/plat/marvell/common/mss/mss_ipc_drv.h +++ b/plat/marvell/common/mss/mss_ipc_drv.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses @@ -101,19 +101,19 @@ struct mss_pm_ipc_ch { int mv_pm_ipc_init(unsigned long ipc_control_addr); /***************************************************************************** -* mv_pm_ipc_msg_rx -* -* DESCRIPTION: Retrieve message from IPC channel -****************************************************************************** -*/ + * mv_pm_ipc_msg_rx + * + * DESCRIPTION: Retrieve message from IPC channel + ***************************************************************************** + */ int mv_pm_ipc_msg_rx(unsigned int channel_id, struct mss_pm_ipc_msg *msg); /***************************************************************************** -* mv_pm_ipc_msg_tx -* -* DESCRIPTION: Send message via IPC channel -****************************************************************************** -*/ + * mv_pm_ipc_msg_tx + * + * DESCRIPTION: Send message via IPC channel + ***************************************************************************** + */ int mv_pm_ipc_msg_tx(unsigned int channel_id, unsigned int msg_id, unsigned int cluster_power_state); diff --git a/plat/marvell/common/mss/mss_mem.h b/plat/marvell/common/mss/mss_mem.h index bed5584c..efff59e6 100644 --- a/plat/marvell/common/mss/mss_mem.h +++ b/plat/marvell/common/mss/mss_mem.h @@ -1,35 +1,8 @@ /* - * *************************************************************************** - * Copyright (C) 2016 Marvell International Ltd. - * *************************************************************************** + * Copyright (C) 2018 Marvell International Ltd. * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of Marvell nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, - * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *************************************************************************** + * SPDX-License-Identifier: BSD-3-Clause + * https://spdx.org/licenses */ #ifndef __MSS_PM_MEM_H @@ -41,8 +14,8 @@ enum mss_pm_ctrl_handshake { MSS_UN_INITIALIZED = 0, MSS_COMPATIBILITY_ERROR = 1, - MSS_ACKNOWLEDGEMENT = 2, - HOST_ACKNOWLEDGEMENT = 3 + MSS_ACKNOWLEDGMENT = 2, + HOST_ACKNOWLEDGMENT = 3 }; enum mss_pm_ctrl_rtos_env { diff --git a/plat/marvell/common/mss/mss_scp_bl2_format.h b/plat/marvell/common/mss/mss_scp_bl2_format.h index 4db3a336..c04df727 100644 --- a/plat/marvell/common/mss/mss_scp_bl2_format.h +++ b/plat/marvell/common/mss/mss_scp_bl2_format.h @@ -1,35 +1,8 @@ /* - * *************************************************************************** - * Copyright (C) 2017 Marvell International Ltd. - * *************************************************************************** + * Copyright (C) 2018 Marvell International Ltd. * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of Marvell nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, - * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *************************************************************************** + * SPDX-License-Identifier: BSD-3-Clause + * https://spdx.org/licenses */ #ifndef __MSS_SCP_BL2_FORMAT_H @@ -44,7 +17,8 @@ /* Types definitions */ typedef struct file_header { - uint32_t magic; /* Magic specific for concatenated file (used for validation) */ + /* Magic specific for concatenated file (used for validation) */ + uint32_t magic; uint32_t nr_of_imgs; /* Number of images concatenated */ } file_header_t; @@ -62,7 +36,9 @@ enum cm3_t { typedef struct img_header { uint32_t type; /* CM3 type, can be one of cm3_t */ uint32_t length; /* Image length */ - uint32_t version; /* For sanity checks and future extended functionality */ + uint32_t version; /* For sanity checks and future + * extended functionality + */ } img_header_t; #endif /* __MSS_SCP_BL2_FORMAT_H */ diff --git a/plat/marvell/common/mss/mss_scp_bootloader.c b/plat/marvell/common/mss/mss_scp_bootloader.c index b395a393..ff8f26c8 100644 --- a/plat/marvell/common/mss/mss_scp_bootloader.c +++ b/plat/marvell/common/mss/mss_scp_bootloader.c @@ -1,35 +1,8 @@ /* - * *************************************************************************** - * Copyright (C) 2016 Marvell International Ltd. - * *************************************************************************** + * Copyright (C) 2018 Marvell International Ltd. * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of Marvell nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, - * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *************************************************************************** + * SPDX-License-Identifier: BSD-3-Clause + * https://spdx.org/licenses */ #include <assert.h> @@ -76,14 +49,14 @@ static int mss_check_image_ready(volatile struct mss_pm_ctrl_block *mss_pm_crtl) int timeout = MSS_HANDSHAKE_TIMEOUT; /* Wait for SCP to signal it's ready */ - while ((mss_pm_crtl->handshake != MSS_ACKNOWLEDGEMENT) && + while ((mss_pm_crtl->handshake != MSS_ACKNOWLEDGMENT) && (timeout-- > 0)) mdelay(1); - if (mss_pm_crtl->handshake != MSS_ACKNOWLEDGEMENT) + if (mss_pm_crtl->handshake != MSS_ACKNOWLEDGMENT) return -1; - mss_pm_crtl->handshake = HOST_ACKNOWLEDGEMENT; + mss_pm_crtl->handshake = HOST_ACKNOWLEDGMENT; return 0; } @@ -98,7 +71,7 @@ static int mss_image_load(uint32_t src_addr, uint32_t size, uintptr_t mss_regs) return 1; } - NOTICE("Loading MSS image from address 0x%x Size 0x%x to MSS at 0x%lx\n", + NOTICE("Loading MSS image from addr. 0x%x Size 0x%x to MSS at 0x%lx\n", src_addr, size, mss_regs); /* load image to MSS RAM using DMA */ loop_num = (size / DMA_SIZE) + (((size & (DMA_SIZE - 1)) == 0) ? 0 : 1); @@ -153,7 +126,8 @@ static int mss_image_load(uint32_t src_addr, uint32_t size, uintptr_t mss_regs) * firmware for AP is dedicated for PM and therefore some additional PM * initialization is required */ -static int mss_ap_load_image(uintptr_t single_img, uint32_t image_size, uint32_t ap_idx) +static int mss_ap_load_image(uintptr_t single_img, + uint32_t image_size, uint32_t ap_idx) { volatile struct mss_pm_ctrl_block *mss_pm_crtl; int ret; @@ -188,7 +162,8 @@ static int mss_ap_load_image(uintptr_t single_img, uint32_t image_size, uint32_t /* TODO: add checksum to image */ VERBOSE("Send info about the SCP_BL2 image to be transferred to SCP\n"); - ret = mss_image_load(single_img, image_size, bl2_plat_get_ap_mss_regs(ap_idx)); + ret = mss_image_load(single_img, image_size, + bl2_plat_get_ap_mss_regs(ap_idx)); if (ret != 0) { ERROR("SCP Image load failed\n"); return -1; @@ -203,7 +178,8 @@ static int mss_ap_load_image(uintptr_t single_img, uint32_t image_size, uint32_t } /* Load CM3 image (single_img) to CM3 pointed by cm3_type */ -static int load_img_to_cm3(enum cm3_t cm3_type, uintptr_t single_img, uint32_t image_size) +static int load_img_to_cm3(enum cm3_t cm3_type, + uintptr_t single_img, uint32_t image_size) { int ret, ap_idx, cp_index; uint32_t ap_count = bl2_plat_get_ap_count(); @@ -230,14 +206,20 @@ static int load_img_to_cm3(enum cm3_t cm3_type, uintptr_t single_img, uint32_t i */ cp_index = cm3_type - 1; for (ap_idx = 0; ap_idx < ap_count; ap_idx++) { - /* Check if we should load this image according to number of CPs */ + /* Check if we should load this image + * according to number of CPs + */ if (bl2_plat_get_cp_count(ap_idx) <= cp_index) { - NOTICE("Skipping MSS CP%d related image\n", cp_index); + NOTICE("Skipping MSS CP%d related image\n", + cp_index); break; } - NOTICE("Load image to CP%d MSS AP%d\n", cp_index, ap_idx); - ret = mss_image_load(single_img, image_size, bl2_plat_get_cp_mss_regs(ap_idx, cp_index)); + NOTICE("Load image to CP%d MSS AP%d\n", + cp_index, ap_idx); + ret = mss_image_load(single_img, image_size, + bl2_plat_get_cp_mss_regs( + ap_idx, cp_index)); if (ret != 0) { ERROR("SCP Image load failed\n"); return -1; diff --git a/plat/marvell/common/mss/mss_scp_bootloader.h b/plat/marvell/common/mss/mss_scp_bootloader.h index 762bb020..67c387a0 100644 --- a/plat/marvell/common/mss/mss_scp_bootloader.h +++ b/plat/marvell/common/mss/mss_scp_bootloader.h @@ -1,35 +1,8 @@ /* - * *************************************************************************** - * Copyright (C) 2016 Marvell International Ltd. - * *************************************************************************** + * Copyright (C) 2018 Marvell International Ltd. * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * Neither the name of Marvell nor the names of its contributors may be used - * to endorse or promote products derived from this software without specific - * prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE - * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, - * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - * POSSIBILITY OF SUCH DAMAGE. - * - *************************************************************************** + * SPDX-License-Identifier: BSD-3-Clause + * https://spdx.org/licenses */ #ifndef __MSS_SCP_BOOTLOADER_H__ diff --git a/plat/marvell/common/plat_delay_timer.c b/plat/marvell/common/plat_delay_timer.c index eab68ca1..dfc77c7f 100644 --- a/plat/marvell/common/plat_delay_timer.c +++ b/plat/marvell/common/plat_delay_timer.c @@ -1,17 +1,13 @@ /* - * Copyright (C) 2016 - 2018 Marvell International Ltd. + * Copyright (C) 2018 Marvell International Ltd. * * SPDX-License-Identifier: BSD-3-Clause * https://spdx.org/licenses */ -/* - * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ + #include <arch_helpers.h> #include <delay_timer.h> -#include <plat_def.h> +#include <mvebu_def.h> #define SYS_COUNTER_FREQ_IN_MHZ (COUNTER_FREQUENCY/1000000) diff --git a/plat/marvell/marvell.mk b/plat/marvell/marvell.mk index 8a1d9fcb..217ad46f 100644 --- a/plat/marvell/marvell.mk +++ b/plat/marvell/marvell.mk @@ -1,4 +1,4 @@ -# Copyright (C) 2016 - 2018 Marvell International Ltd. +# Copyright (C) 2018 Marvell International Ltd. # # SPDX-License-Identifier: BSD-3-Clause # https://spdx.org/licenses |