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2017-05-29Bump atf-v1.3 to release armada-17.06.2atf-v1.3-armada-17.06Konstantin Porotchkin
Change-Id: Ib6e10f237906baf35657a1b1699036611d4fc4e0 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/40025 Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2017-05-28ble: set binary extension size to max per specVictor Axelrod
This patch sets the binary extension size close to its maximum as defined by the specification. The upper limit may be set to 0xffe7c000 (0xffe1c000 + 384KB), but actually set to 0xffe7800 to provide 16KB for the secure extension of 9,956 bytes size. Change-Id: Id6e78eba95ab9d0e5241c7b70d750cb5b39230b1 Signed-off-by: Victor Axelrod <victora@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/37789 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/40002
2017-05-21Bump atf-v1.3 to release armada-17.06.1Konstantin Porotchkin
Change-Id: I50303cf6870de1d9480ed66a8916ec93cf36db91 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39704 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com>
2017-05-21fix: mci: remove redundant enablement of register-mode accessOmri Itach
according to design guidelines, enablement of register-mode access (mci_enable_phy_regs_access) is redundant and should not performed as a part of MCI initialization for A80x0-A1. Change-Id: I7b8fb70a4d6fa518ee56c64556305210a183f7a6 Signed-off-by: Omri Itach <omrii@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39746 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2017-05-21fix: mci: Fine tune of MCI parametersOmri Itach
At AP and CP //reg[15:8] – RX NQ threshold reduced to 0x7 //reg[23:16] – RX PQ threshold reduced to 0x7 //reg[31:24] – RX RQ threshold reduced to 0x7 //reg[7:4] – RX delta threshold reduced to 0x2 At AP: //reg[4:0] – WR outstanding reduced to 0x6 (0x5 written to reg) //reg[10:6] – RD outstanding reduced to 0x6 (0x5 written to reg) At CP: //reg[10:6] – RD outstanding reduced to d’14 (d’13 written to reg) Change-Id: I00d1f22501d22171015873a1b12224e0c0443fbe Signed-off-by: Omri Itach <omrii@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39526 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-05-21fix: pcie: temporarily disable pcie clock fixIgal Liberman
After commit "f82b49e fix: pcie: cp110: fix pcie clock selection" we encountered some instabilities in PCIe. This patch disables the PCIe clock fix temporarily, until we figure out the root cause for this this issue. Change-Id: I521e4495118fab2bcbe1e99e6080d1cbb2b08f39 Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39663 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-05-18fix: mci: ap806: skip setting MCI ID assignment when booting from MCIOmri Itach
When boot source is from MCI, bootROM is already enabling MCI simultaneous transactions (ID assignment), so in that case we must avoid enabling it for the 2nd time (according to design guidelines). Change-Id: I3967fc3526e27356f9e8ebf184b52cc21003e3c1 Signed-off-by: Omri Itach <omrii@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39557 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-05-16fix: pcie: fix pcie clock selection for A2 revisionIgal Liberman
This patch fixes incorrect handling of pcie clock: If pcie_clk is set to input (by the Sample-at-Reset), PCIE refclk buffer 0/1 source field in PCIe_Reference_Clock_Buffer_Control register should be set to 1 and not 0 as it done now. Change-Id: I14fedce9d3299b5b85eb742048f03b17f1f9ab14 Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39456 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-05-15fix: mvebu: pcie: set correct preset4 valueIgal Liberman
Currently, incorrect preset4 value is used. This patch fixes the preset4 according to HW measurments. Change-Id: I839a6c843e912182bb0c71e3ab836dac27ce8a97 Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39421 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2017-05-15fix: pcie: cp110: update analog parameters according to latest ETPIgal Liberman
Add PCIE analog parameters initialization values according to latest ETP. Change-Id: I3f5892702610e46ebaba7485e3cef5817f1518b5 Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/36995 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39411
2017-05-12Bump atf-v1.3 to release devel-17.06.0Konstantin Porotchkin
Change-Id: I11ee81c5741cbe5b7d1f07f57aed095a3f31c182 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39323 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Wilson Ding <dingwei@marvell.com>
2017-05-12makefile: a3700: move opthash.txt file to build folder for trusted buildTerry Zhou
The 'opthash.txt' contains the KAK key digest, which is used by the customer to program the fuse for the trusted boot. Change-Id: I5d7e095a6b48a0c5cb8587c2a8e0063e7988ab7e Signed-off-by: zachary <zhangzg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39356 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Wilson Ding <dingwei@marvell.com>
2017-05-12fix: makefile: a3700: correct DOIMAGEPATH assignmentzachary
DOIMAGEPATH used to get its path by 'dir' command when Makefile assigns the WTP path to it. The 'dir' command returns the left string from the last "/" of the file or directory path. Therefore, the actual DOIMAGEPATH is missing one level directory without one extra "/" in WTP export env. This patch fixed this issue by assign the WTP path to DOIMAGEPATH directly. Change-Id: I2b18b13f2d3283e714ec6bfa47db6d477295f9c1 Signed-off-by: zachary <zhangzg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39355 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Wilson Ding <dingwei@marvell.com>
2017-05-12a3700: add unnecessary files to gitignore listzachary
Added the intermediate files "CSK*-KeyHash.txt" and "TIMHash.txt" and "Tim_msg.txt" files to gitignore list, which are generated by boot image generated tool Change-Id: I3c880f898d4c46a20e85ee3202677a9f682615dc Signed-off-by: zachary <zhangzg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39286 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Wilson Ding <dingwei@marvell.com>
2017-05-12makefile: a3700: remove unnecessary files after buildzachary
Remove "CSKN-KeyHash.txt" and Hash.txt after building trusted image Remove "TIMHash.txt" and "Tim_msg.txt" after building untrusted image Change-Id: I6ce675f39d49c3cd6538205acefd5e64685d6fbf Signed-off-by: zachary <zhangzg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39358 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Terry Zhou <bjzhou@marvell.com> Reviewed-by: Wilson Ding <dingwei@marvell.com>
2017-05-12fix: a3700: Fix the issue of make distcleanTerry Zhou
Armada37x0's ATF compilation includes native ATF code and external WTP component. Thus, WTP component should also be cleaned up along with ATF. However, WTP path is now tied to DOIMAGEPATH, which is different from the default for other Marvell SoCs. Thus, PLAT option is required in order to clean up the WTP component: make PLAT=a3700 WTP=<path/to/wtp> distclean/clean ATF always invokes make clean for "CRTTOOLPATH". When specifying PLAT option in "make clean" command, it will validate the "include" folder under "PLAT_DIR", which expects "include" folder located in the same directory of "platform.mk". Since the existing Armada37x0's PLAT directory doesn't compiles with ATF convention, it caused the error in "make clean". The temporary solution is to add a symbolic link named as 'include' under "PLAT_DIR", which points to itself. This WA will be removed after 'plat/marvell/a3700' folder is reorganized. Change-Id: I95bea27f3999b6490103aec56197eecee2cdd8b6 Signed-off-by: Terry Zhou <bjzhou@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39357 Reviewed-by: Wilson Ding <dingwei@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2017-05-11fix: ap806: enable 48-bit virtual addressMarcin Wojtas
Issue found when enable 48-bit Virtual Address in kernel In ARMv8 the CPU can work with 48-bit virtual address, at this case for propagating TLB maintenance 44-bit of Physical address are needed. Marvell interconnect is configured to be 40-bit address by default, therefore AxAddr[43:40] are not propagated so the DVM is not working. Change-Id: I7b8a3ec7960697814079f2c932fd06962bfa4c75 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39185 Reviewed-by: Igal Liberman <igall@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Hanna Hawa <hannah@marvell.com>
2017-05-11script: a3700: add static startup scripts for XDBKen Ma
This patch adds static startup XDB scripts for Armada37x0: - The DDR will be initialized, but only the first 512MB, which is good enough for board recovery - The first dram cpu decoder window size will be set; - BL1 and FIP will be loaded and executed by default. Change-Id: I4ec4cdb7dcded4d9757fa647d00c977ab4de3b63 Signed-off-by: Ken Ma <make@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39249 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-by: Wilson Ding <dingwei@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2017-05-11fix: pcie: move pcie initialization to cp110_ble_initIgal Liberman
In addition, add a call to cp110_pcie_clk_cfg(). This function is responsible for configuring PCIe ref clock and must me called before configuring PCIe interface. Change-Id: I807a4466d9c4459f9403b2542d771c961f07a46e Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39257 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-05-11fix: mvebu: pcie: improve PCIE mac configurationIgal Liberman
This patch does the following: - Disable auto flush If auto flash is enabled, we can't enable/disable the link and perform "hot reset" - Set link equalization training to preset4 According to ETP, this is the best preset that our receiver can handle. - Remove VPD capability from the capability list It's not supported - Remove SRIOV capability from the capability list It's not supported - In end point mode: unmask the reset request: The hot reset and link disable/enable must penetrate and reset the MAC configurations. Change-Id: Ia189aaef29b175eb351ee9a861ae3883b3677fa9 Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39226 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-05-11fix: pcie: cp110: fix pcie clock selectionIgal Liberman
There's a difference between PCIe clock configuration. in CP110 revision A1 and CP110 revision A2 CP110 revision A1: The SatR that decides if the PCIE uses internal refclock or external refclock does not work properly. When the clock is set to input we need to do extra configuration in order to make the input clock functional. (Iboth PCIe clocks must be aligned, so if one set to input, we must Performe the configuration). CP110 revision A2: PCIe Reference Clock Buffer Control register must be set according to the clock direction (input/output), there's a field for each refclock (pcie0 and pcie1) which are set accordingly to the clock configuration. Change-Id: I6b0150293bfd2d7595d19016c1fd82c4d4ed326a Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39297 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-05-11cp110: add function to read cp110 revisionIgal Liberman
Change-Id: I8288e56954c3d31af5ffe7184c5b3a10ae491dee Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39296 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-05-10makefile: a3700: update TBB binary file nameEvan Wang
The patch updated the TBB binary file name from tbb_linux.exe and ntbb_linux.exe to TBB_linux. The new bianry file of TBB_linux supports both security boot and nonsecurity. The new binary is generated by the latest TBB source code. Change-Id: Ifb251a10062dbcdff09aca5b7f92a1ea08f0e262 Signed-off-by: Evan Wang <xswang@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39050 Reviewed-by: Wilson Ding <dingwei@marvell.com> Tested-by: Wilson Ding <dingwei@marvell.com>
2017-05-10fix: doc: mvebu: correct DDR topology option number for DDR4 2CSzachary
- There was a wrong DDR Topology option number description issue for DDR4 2CS. - The patch changes its option number from 4 to 3 for DDR4 2CS. Change-Id: If37b885b231f57215ea1b5bc51faa5b0e3d234eb Signed-off-by: zachary <zhangzg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39136 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Wilson Ding <dingwei@marvell.com> Reviewed-by: Gina Tadmore <gina@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com>
2017-05-09fix: io-dec: a3700: disable io-decode windows to rWTMjinghua
- By default, several IOs have decode window to rWTM: - SATA: window 2, from 0x1fff0000 to 0x2000ffff. - SDIO/eMMC: window 2, from 0x1fff0000 to 0x2000ffff. - USB32: window 2, from 0xC0000000 to 0xC000ffff. - These windows should be disabled in non-DAS mode, since: - These IOs should not access rWTM. - These decode windows overlap with DRAM decode window. For example, in 512MB DRAM case, SATA and SDIO/eMMC rWTM window overlap with DRAM decode window in the last 64KB DRAM address. - This patch sets these decode window to be used for DRAM, so software would disable them by default, and configure them to be DRAM decode window if needed. - JIRA: A3700-1163 Change-Id: I6d35a98b14f3ddc575930f83ea5e700995a29519 Signed-off-by: jinghua <jinghua@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39247 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Wilson Ding <dingwei@marvell.com>
2017-05-08fix: pm: a3700: reinit CPU decode window in resume sequenceEvan Wang
In order to support 4GB DRAM the CPU decode window changed from default configuration, and the PCIe decode window is also changed with less than 2GB DRAM to align with 4GB DRAM. So PCIe will not work well with default CPU decode window configuration and it needs init again in callback of pwr_domain_suspend_finish(). JIRA number: A3700-1157 Change-Id: I938070589890215b8d8aaffed4f23ba592184c3e Signed-off-by: Evan Wang <xswang@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39167 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-by: Wilson Ding <dingwei@marvell.com> Reviewed-by: Ken Ma <make@marvell.com>
2017-05-07fix: io-decode: a3700: add eip97 window attributesIgal Liberman
EIP97 (crypto hardware) DMA address decoder register is not configured. This patch configures the register and fixes the EIP97 driver operation in the Kernel. Change-Id: I5a3d1acfce0b08956534cfbde6cae3d208ecf2b4 Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39184 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2017-05-03plat: marvell: a8k: Rename A80x0 customer to McbinKonstantin Porotchkin
Rename Macciatobin platform from a80x0_cust to a80x0_mcbin Change-Id: I715be80891f7c2d5d68a84f22a0568eb94b26c18 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38411 Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2017-05-03doc: a3700: update build file for adding ddr4 2cs 4GB supportzachary
- This patch adds build option DDR_TOPOLOGY number to support DDR4 2cs 4GB build. - Example: make DEBUG=1 USE_COHERENT_MEM=0 DDR_TOPOLOGY=3 PLAT=a3700 all fip Change-Id: I966dc6630fda5ebab906ba669ef93f4614bd2a36 Signed-off-by: zachary <zhangzg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38864 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Gina Tadmore <gina@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-05-03doc: a3700: update build.txt for new clock preset 1200/750Ken Ma
Change-Id: I0143ffbeae1d48e2700b35107588b4d6de893485 Signed-off-by: Ken Ma <make@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39046 Reviewed-by: Hua Jing <jinghua@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-05-03doc: a3700: add build option of wtmi imageKen Ma
- Update build.txt for the build option - WTMI_IMG. WTMI_IMG can point to a image which does nothing, a image which supports EFUSE or a customized CM3 firmware image. Change-Id: I63304fe39c823d67db39c7ee111972fef063cecd Signed-off-by: Ken Ma <make@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39047 Reviewed-by: Hua Jing <jinghua@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-04-3070x0: pcac: rename a7040_pcac to a70x0_pcacIgal Liberman
In addition, this patch fixes DRAM initialization issue introduced in: "6942e0c fix: a8k: Fix the platform dependency issue" The root cause of the DRAM failure is the pcac naming. All other A7040 devices names A70x0_XX but pcac was named A7040_pcac. Change-Id: Ic204a3d5272a3563a15f955bb8ce70e2e7390ba1 Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39021 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-04-30fix: pcac: a70x0: fix linkage issue in plat_get_pcie_hw_dataIgal Liberman
plat_get_pcie_hw_data() has weak implementation in pci_ep_setup.c and another implementation for A70x0 PCAC in marvell_plat_config.c. Currently, there's an issue with A70x0 PCAC linkage and the weak implementation is chosen. The issue is caused by the fact that the A70x0 PCAC implementation is located under #ifndef BLE but the PCIe code is located in the BLE. This patch fixes the linkage issue (by moving the plat_get_pcie_hw_data() code out if the #ifndef). Change-Id: I53cd32af6f858b0bfd63a0fffd562c34e17eb2e3 Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39020 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-04-28io-decode: a3700: update the max dram decode windows numberKen Ma
- Not all configurable decode windows could be used for dram, some units have to reserve one decode window for other unit they have to communicate with; for example, DMA engineer has 3 configurable windows, but only two could be for dram while the last one has to be for pcie, so for DMA, its max dram decode windows number is 2; - Only io dram decode windows needs to be reconfigured for different dram size boards(512MB, 2GB and 4GB), this patch renames the field member max_win to max_dram_win and updates the old io max decode windows number to max dram decode windows number. Change-Id: I61ed0c936baa5b2f73c5e7d0c41dfc81c7033b90 Signed-off-by: Ken Ma <make@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38956 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Hua Jing <jinghua@marvell.com>
2017-04-28fix: cpu-win: a3700: remove remap function for cpu dram windows of 4GBKen Ma
- When dram size is 4GB, there are 4 cpu dram windows, the number 4 exceeds the limit of io decode windows number, so in this case, only one io decode window whose size is 4GB is used for dram; - In order to have the same view on dram for cpu and ios, cpu dram window must not use remap function, this patch removes remap function for cpu dram windows. Change-Id: I328b7338ee464935917c80857be208c40369d4ba Signed-off-by: Ken Ma <make@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38925 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Hua Jing <jinghua@marvell.com>
2017-04-26fix: a3700: restore timn image in uart trusted buildTerry Zhou
- The TIMN image is missing in Armada3700 build folder, which is one of the image components needed by the recovery procedure. Makefile is supposed to get the image filename from atf_timN.txt and it defines a variable to parse the filename in the atf_timN.txt. But the atf_timN.txt is dynamically generated. It doesn't exist when this variable is initialized (if ATF performs a clean build). - This patch is to change this global variable as the second-expansion of shell command in Makefile. So that the shell will execute the enclosed command only when the Makefile is referring this variable Change-Id: Iba39377cc2752c42bcb0ecbd854f8a9e57e1353d Signed-off-by: Terry Zhou <bjzhou@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38699 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Hua Jing <jinghua@marvell.com>
2017-04-26makefile: a3700: add image encryption support for trusted bootTerry Zhou
only support AES_CBC_256 algorithm build uart image without encryption Change-Id: I66caf134b6e159433561e34c0f775d6e177dde31 Signed-off-by: Terry Zhou <bjzhou@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38698 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Hua Jing <jinghua@marvell.com>
2017-04-26io-decode: a3700: update IO decode window configuration in ATFKen Ma
- Now in ATF IO decode windows are configured according to CPU DRAM decode window; For 4GB dram board, there are 4 CPU DRAM decode windows, the IO decode window number is smaller than 4(some IO has 2 decode windows while other IOs has 3 decode windows), then 4 CPU DRAM windows can not be configured for IO all; - This patch only fill the first IO decode window with base(0) and size (4GB) when CPU DRAM windows number exceeds the IO decode windows max number. Change-Id: Ic386c85fae11c3d6381c738e37ade261382cfce0 Signed-off-by: Ken Ma <make@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38868 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Hua Jing <jinghua@marvell.com>
2017-04-25dram: a3700: writing dram cpu decode windows information by sysinfozachary
- In order to support 2 chips dram 4Gb, a3700 needs to use more than 1 dram cpu decode window configuration. - A3700 uboot used to read the first dram cpu decode window and size, it is not enough for more than 2 cpu decode window. - This patch writes dram cpu decode windows information to DDR for passing these information to uboot for using. Change-Id: I721cf0ca0eeb634c7e860dd4a6e15a56c2ed1605 Signed-off-by: zachary <zhangzg@marvell.com> Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: zachary <zhangzg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38695 Reviewed-by: Hua Jing <jinghua@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2017-04-25mvebu: add more system info types for passing atf information to ubootzachary
- In order to pass cpu decode window information from atf to uboot, add more system information types for it. Change-Id: I83032a9ab26c7438e542e1c9a04ecbeaebcc3bc1 Signed-off-by: zachary <zhangzg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38833 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-by: Hua Jing <jinghua@marvell.com>
2017-04-25cpu-win: a3700: support 4GB DRAM CPU decode window configurationKen Ma
- To support 4GB DRAM, CPU decode window needs to be updated: there are at most 5 configurable cpu decode windows and each window could only supports the size with 2 powers of N; since the address range is 4GB and Internal Regs, CCI-400 and Boot Rom windows hold fixed ranges, so it means that the configurable window size could be 2GB, 1GB, 512MB, 256MB...; and cpu dram windows number must increase to utilize memory as much as possible, they will take place of some unused cpu io windows; - If total dram size is more than 2GB, now there is only one case - 4GB dram, the cpu windows configuration is as below: - Internal Regs, CCI-400 and Boot Rom windows are kept as default; - Use 4 CPU decode windows for DRAM, which cover 3.75GB DRAM; since DDR window 0 is configured in tim header with 2GB size, this patch only configures cpu dram windows 1/2/3 with sizes of 1GB/256MB/512MB; - The only one CPU decode window left is for PCIe, which has 64MB address; - If total dram size is no more than 2GB, then pcie cpu window is modified to be aligned with 4GB dram's configuration, other cpu windows are kept as default. Change-Id: I178df27fd5a38d18472f35e7ba89227ef269572a Signed-off-by: Ken Ma <make@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38762 Reviewed-by: Hua Jing <jinghua@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2017-04-24doc: Update Marvell porting documentationallen yan
- Update Marvell platform porting documents. Change-Id: I6a8d3a0d527dcce342f358e8f0d49ea2598306ac Signed-off-by: allen yan <yanwei@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38689 Reviewed-by: Victor Gu <xigu@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-by: Hua Jing <jinghua@marvell.com>
2017-04-24atf: a3700: add crash report print for relevant regszachary
- The patch adds macro prints for relevant GIC and CCI registers registers whenever an unhandled exception is taken in BL31. Change-Id: Ic9519fba41d45e6e47a615aea242d1b240aa3ce6 Signed-off-by: zachary <zhangzg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38637 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Hua Jing <jinghua@marvell.com>
2017-04-24atf: a3700: rename plat interconnect reg macro definationzachary
- Use plat cci reg print to repalce plat interconnect reg print to align mainline code. Change-Id: If0df0049f8efb3ac1cf54117b431ae11b2827b85 Signed-off-by: zachary <zhangzg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38666 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-04-21pm: a3700: support uart port as wake up sourcewei yan
- For uart1, the first step is setting uart tx and rx pin as gpio mode, and then set gpio 18/19 as wake up source. - For uart0, the first step is setting uart tx and rx pin as gpio mode, and then set gpio 25/26 as wake up source. - Default config uart1 as wake up source. Change-Id: I8deb16266300af5b1d72d7a13ebd7a2e5cecc451 Signed-off-by: wei yan <yanwei@marvell.com> Signed-off-by: allen yan <yanwei@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38685 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Hua Jing <jinghua@marvell.com>
2017-04-21fix: pm: a3700: skip setting gpio wake up bit for PPD and stepdown modeVictor Gu
The GPIO wake up enable registers(0xD0013C18 and 0xD0013C1C) are used to enable the GPIO pin to wake up the CPU from partial powerdown and step down mode. According to the suspend to RAM testing, the GPIO wake up do not need to set it, and there is crash if some of its bits are set. This patch removes the setting for GPIO wake up bits. Change-Id: Iae5ab2aac1fe5b8a4023158d4a4fe763c2723f4c Signed-off-by: Victor Gu <xigu@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38683 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Hua Jing <jinghua@marvell.com>
2017-04-21fix: pm: a3700: set wake up option and source prior to ack the irqVictor Gu
It is possible to trigger extra interrupts during setting the wake up option and sources, which affects the suspend operation. Thus the wake up option and source setting should be done prior to ack the irq. Change-Id: I83f79193b935e98a29443c1efaaec7075b8eb01f Signed-off-by: Victor Gu <xigu@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38644 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Hua Jing <jinghua@marvell.com>
2017-04-21fix: mpp: a3700: switch all SPI pins back from uart download featurejinghua
- In UART boot mode initialization, SPI CS and CLK pins are used as downloading image purpose; But after downloading, these bits should be switch back to SPI mode. Otherwise SPI functionality is broken. - This patch sets bit 28 of north_bridge_pin_out_en_high register 13804, to switch SPI CS and CLK pins back from UART download feature. Change-Id: I30e2c0202da7f7b0fba3916af121da9017e1cce4 Signed-off-by: jinghua <jinghua@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38690 Tested-by: iSoC Platform CI <ykjenk@marvell.com> (cherry picked from commit eaa8a65da8af00d3443068418955f9396becd00f) Reviewed-on: http://vgitil04.il.marvell.com:8080/38691
2017-04-21gicv3: a3700: save and restore SPI and PPI state during low power modezachary
The SPI and PPI irq states are saved during core power off or suspend, and resumed during core up or resume. Change-Id: Ib41a28b453d07cc718c61ab2246dfa382c2d87bf Signed-off-by: Victor Gu <xigu@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/37432 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Hua Jing <jinghua@marvell.com> Signed-off-by: zachary <zhangzg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38078 Tested-by: Hua Jing <jinghua@marvell.com> Signed-off-by: zachary <zhangzg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38610
2017-04-21gicv3: marvell: add IRQ state PM supportVictor Gu
This patch wrap the ARM GICv3 SPI and PPI irq state PM APIs for Marvell platform, which are used in suspend and resume process. Marvell plat_marvell_gic_irq_save/restore APIs are used to save and restore SPI irq states. Marvell plat_marvell_gic_irq_pcpu_save/restore APIs are used to save and restore per-cpu irq states. Change-Id: I7a466fef369241b3ce7f727c0c7179ec7023a09e Signed-off-by: Victor Gu <xigu@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/37431 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Hua Jing <jinghua@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38077 Tested-by: Hua Jing <jinghua@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38609
generated by cgit (git 2.34.1) at 2024-05-07 01:10:42 +0000