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2017-04-02platform: Add marvell platforms common componentsKonstantin Porotchkin
Add common platform components to be used by all supported Marvell platforms. Change-Id: Ie5f70fc7ff668c8f8073d6dd936458f35890ebcf Signed-off-by: Haim Boot <hayim@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38133
2017-04-02tools: Add marvell doimage build toolKonstantin Porotchkin
Add Marvell flash image builder "doimage" The "doimage" tool is used for building a boot image with all headers and extensions acceptable by the SoC BootROM. It also is able to sign and encrypt the image for trusted boot mode as far as verify and print the image content information. This "doimage" release supports Marvell A7K/A8K SoCs. Change-Id: I5ad7377abdcbccb77cb4d71e5e4e4cd4358303e7 Signed-off-by: Haim Boot <hayim@marvell.com> Signed-off-by: Yehuda Yitschak <yehuday@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/37917
2017-04-02drivers: Add drivers for Marvell A7K and A8K platformsKonstantin Porotchkin
Add Marvell drivers for A7K and A8K SoC families Change-Id: I7fb530e543e4f64782f41f8a058b6aabd82af9e8 Signed-off-by: Haim Boot <hayim@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/37916
2017-04-02ble: Add BLE stage used by Marvell platforms for DDR initKonstantin Porotchkin
Add BLE stage that runs in BootROM context and used by Marvell platforms for DRAM initialization and training. Change-Id: I989b7298c47446824b25c4b68d27bd2379462035 Signed-off-by: Haim Boot <hayim@marvell.com> Signed-off-by: Yehuda Yitschak <yehuday@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/37915
2017-04-02io: Allow image load to address zeroKonstantin Porotchkin
Allow zero-address assertion bypass if requested by platform compilation flag PLAT_ALLOW_ZERO_ADDR_COPY. This patch allows loading BL33 (u-boot) to address 0x0 Change-Id: I10518db13466017110358437790ce5212d52d9e6 Signed-off-by: Haim Boot <hayim@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/37914
2017-04-02delay_timer: Add timer value get functionsKonstantin Porotchkin
Add ability to get timer value in micro- and milliseconds. Change-Id: I864619c23fe8a2a01cef86795e39d1b0bfd2e3d3 Signed-off-by: Victor Axelrod <victora@marvell.com> Signed-off-by: Ofir Fedida <ofedida@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/37913 Reviewed-by: Haim Boot <hayim@marvell.com>
2017-03-23scripts: Add checkpatch script and change check defaultsKonstantin Porotchkin
Please do not push this patch to the mainline, it is intended to be used with Marvell CI only. Add checkpatch.pl script to the source tree and modify the checkpatch settings provided by the mainline (checkpatch.conf) The mainline configuration is created for unmodified checkpatch from latest kernel sources. It includes option --showfile which is not supported by the regular u-boot/ATF checkpatch script. Change-Id: Id36a49b7844e08751214b55db602b31621ef0b3c Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/37920 Reviewed-by: Haim Boot <hayim@marvell.com>
2017-03-15Revert "Fill exception vectors with zero bytes"Haim Boot
This reverts commit 79627dc37259781e578c47e1e63856dd0424b2a2. It is required to allow build of ATF with MGCC and Yocto toolchain. Change-Id: I7bfcf46e977c05cc988d93a2d1a22a9d0cc512d3 Reviewed-on: http://vgitil04.il.marvell.com:8080/37435 Reviewed-by: Hua Jing <jinghua@marvell.com> Reviewed-by: Haim Boot <hayim@marvell.com> Tested-by: Haim Boot <hayim@marvell.com>
2016-10-13Merge pull request #733 from danh-arm/dh/v1.3-finaldavidcunado-arm
Final updates for v1.3 release
2016-10-13Merge pull request #736 from davidcunado-arm/dc/v1.3_updatedavidcunado-arm
Release v1.3: Minor updates to user guide
2016-10-13Release v1.3: Minor updates to user guideDavid Cunado
Updated the user guide to clarify building FIP for AArch32. The instructions were previously specific to building a FIP for AArch64. Change-Id: I7bd1a6b8e810cfda411f707e04f479006817858e Signed-off-by: David Cunado <david.cunado@arm.com>
2016-10-13Update readme.md for v1.3Dan Handley
Update the release notes (readme.md) for the ARM Trusted Firmware v1.3 release. Change-Id: Ia1f4eb1897e63eeab7d69a593ba0ad91d50043f5 Signed-off-by: Dan Handley <dan.handley@arm.com>
2016-10-13Release v1.3: Update minor version number to 3David Cunado
Change-Id: I05991543d28e70b67be600b714990af6a8d7ba29
2016-10-13Release v1.3: update change-log.mdDavid Cunado
Updated change-log.md with summary of changes since release v1.2. Change-Id: Ia1e18ff4b0da567cf12dfcb53e6317e995100bdf
2016-10-12Merge pull request #732 from dp-arm/dp/pmf-docdanh-arm
PMF: Add documentation
2016-10-12PMF: Add documentationdp-arm
Add a Performance Measurement Framework (PMF) section to the firmware design document. Change-Id: I5953bd3b1067501f190164c8827d2b0d8022fc0b Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2016-10-12Merge pull request #731 from danh-arm/an/fix-juno-docdanh-arm
Fix documentation of bootwrapper boot on juno
2016-10-12Fix documentation of bootwrapper boot on junoAntonio Nino Diaz
The user guide incorrectly claimed that it is possible to load a bootwrapped kernel over JTAG on Juno in the same manner as an EL3 payload. In the EL3 payload boot flow, some of the platform initialisations in BL2 are modified. In particular, the TZC settings are modified to allow unrestricted access to DRAM. This in turn allows the debugger to access the DRAM and therefore to load the image there. In the BL33-preloaded boot flow though, BL2 uses the default TZC programming, which prevent access to most of the DRAM from secure state. When execution reaches the SPIN_ON_BL1_EXIT loop, the MMU is disabled and thus DS-5 presumably issues secure access transactions while trying to load the image, which fails. One way around it is to stop execution at the end of BL2 instead. At this point, the MMU is still enabled and the DRAM is mapped as non-secure memory. Therefore, the debugger is allowed to access this memory in this context and to sucessfully load the bootwrapped kernel in DRAM. The user guide is updated to suggest this alternative method. Co-Authored-By: Sandrine Bailleux <sandrine.bailleux@arm.com> Signed-off-by: Dan Handley <dan.handley@arm.com> Change-Id: I537ea1c6d2f96edc06bc3f512e770c748bcabe94
2016-10-12Merge pull request #728 from yatharth-arm/yk/AArch32_porting_docdanh-arm
AArch32: Update firmware-design.md
2016-10-12Merge pull request #727 from soby-mathew/sm/PSCI_lib_docdanh-arm
AArch32: Update user-guide and add DTBs
2016-10-12Merge pull request #726 from soby-mathew/sm/fix_dtdanh-arm
Fix GICv3 DT to include psci system off/reset
2016-10-12Merge pull request #725 from jeenu-arm/fix-duplicate-titledanh-arm
Docs: Rename duplicate title in porting guide
2016-10-11AArch32: Update user-guide and add DTBsSoby Mathew
This patch adds necessary updates for building and running Trusted Firmware for AArch32 to user-guide.md. The instructions for running on both `FVP_Base_AEMv8A-AEMv8A` in AArch32 mode and `FVP_Base_Cortex-A32x4` models are added. The device tree files for AArch32 Linux kernel are also added in the `fdts` folder. Change-Id: I0023b6b03e05f32637cb5765fdeda8c8df2d0d3e
2016-10-11AArch32: Update firmware-design.mdYatharth Kochar
This patch updates the firmware-design.md for AArch32 related changes. Change-Id: Idf392a44861ab9c1f59f3de4f3435f508b17c678
2016-10-11Docs: Rename duplicate title in porting guideJeenu Viswambharan
Fix one of the two titles that ended up being the same, although both describe different things. Change-Id: I66ecf369643709898ee4c014659d8f85c0480643
2016-10-11Fix GICv3 DT to include psci system off/resetSoby Mathew
The `fvp-base-gicv3-psci` and `fvp-foundation-gicv3-psci` device tree source files did not have psci node entries for `system off` and `system reset`. Also the DTS files included `rtsm_ve-motherboard-no_psci.dtsi` instead of `rtsm_ve-motherboard.dtsi`. As a result, the Linux kernel failed to invoke the PSCI_SYSTEM_OFF/RESET API when being shutdown/reset. This patch corrects this problem and also updates the corresponding DTB files. This patch also removes `rtsm_ve-motherboard-no_psci.dtsi` and `fvp-foundation-motherboard-no_psci.dtsi` files as they are no longer used. Change-Id: I8ba61a1323035f7508cae663bb490ac0e8a64618
2016-09-29Merge pull request #719 from yatharth-arm/yk/AArch32_porting_memcpydavidcunado-arm
AArch32: Add `memcpy4` function in assembly
2016-09-29Merge pull request #720 from soby-mathew/sm/PSCI_lib_docsdavidcunado-arm
Docs: Add the PSCI library integration guide
2016-09-28Merge pull request #722 from danh-arm/dh/drop-cladanh-arm
Drop requirement for CLA in contribution.md
2016-09-28Docs: Add the PSCI library integration guideSoby Mathew
This patch adds the PSCI library integration guide for AArch32 ARMv8-A systems `psci-lib-integration-guide.md` to the documentation. The patch also adds appropriate reference to the new document in the `firmware-design.md` document. Change-Id: I2d5b5c6b612452371713399702e318e3c73a8ee0
2016-09-28AArch32: Add `memcpy4` function in assemblyYatharth Kochar
At present the `el3_entrypoint_common` macro uses `memcpy` function defined in lib/stdlib/mem.c file, to copy data from ROM to RAM for BL1. Depending on the compiler being used the stack could potentially be used, in `memcpy`, for storing the local variables. Since the stack is initialized much later in `el3_entrypoint_common` it may result in unknown behaviour. This patch adds `memcpy4` function definition in assembly so that it can be used before the stack is initialized and it also replaces `memcpy` by `memcpy4` in `el3_entrypoint_common` macro, to copy data from ROM to RAM for BL1. Change-Id: I3357a0e8095f05f71bbbf0b185585d9499bfd5e0
2016-09-27Drop requirement for CLA in contribution.mdDan Handley
It is no longer necessary for contributors to send a CLA to ARM before making contributions. Contributors must instead add a "Signed-off-by:" line to each commit, which certifies that the contribution is made under the Developer Certificate of Origin (DCO). Update contributing.md to reflect this new policy and add a copy of the DCO to the repository. Change-Id: I7ca98bffc3bf57e8bdd51d763c24f13e415a328b Signed-off-by: Dan Handley <dan.handley@arm.com>
2016-09-27Merge pull request #718 from sandrine-bailleux-arm/sb/update-deps-v1.3davidcunado-arm
Upgrade Linaro release, FVPs and mbed TLS versions
2016-09-27Upgrade Linaro release, FVPs and mbed TLS versionsSandrine Bailleux
This patch updates the User Guide to recommend the latest version of some of the software dependencies of ARM Trusted Firmware. - Upgrade Linaro release: 16.02 -> 16.06 - Upgrade FVPs - Foundation v8 FVP: 9.5 -> 10.1 - Base FVPs: 7.6 -> 7.7 - Upgrade mbed TLS library: 2.2.0 -> 2.2.1 Note that the latest release of mbed TLS as of today is 2.3.0 but it has compilations issues with the set of library configuration options that Trusted Firmware uses. 2.2.1 is the next most recent release known to build with TF. This patch also fixes the markdown formatting of a link in the User Guide. Change-Id: Ieb7dd336f4d3110fba060afec4ad580ae707a8f1
2016-09-26Merge pull request #717 from sandrine-bailleux-arm/sb/foundation-fvp-v10davidcunado-arm
Whitelist version 9.6 of Foundation FVP
2016-09-23Merge pull request #716 from yatharth-arm/yk/AArch32_portingdavidcunado-arm
AArch32: Fix detection of virtualization support
2016-09-23AArch32: Fix detection of virtualization supportYatharth Kochar
The Virtualization field in the ID_PFR1 register has only 2 valid values (0 or 1) but it was incorrectly checked against unrelated value tied to the SPSR register instead. This patch fixes the detection of virtualization support by using the valid values in BL1 context management code. Change-Id: If12592e343770e1da90f0f5fecf0a3376047ac29
2016-09-23Whitelist version 9.6 of Foundation FVPSandrine Bailleux
This prevents a warning being emitted in the console during FVP configuration setup when using the Foundation FVP 9.6 onwards. Change-Id: I685b8bd0dbd0119af4b0cb3f7d708fcc08e99561
2016-09-22Merge pull request #714 from soby-mathew/sm/psci_lib_argsdanh-arm
Introduce PSCI Library argument structure
2016-09-22PSCI: Do psci_setup() as part of std_svc_setup()Soby Mathew
This patch moves the invocation of `psci_setup()` from BL31 and SP_MIN into `std_svc_setup()` as part of ARM Standard Service initialization. This allows us to consolidate ARM Standard Service initializations which will be added to in the future. A new function `get_arm_std_svc_args()` is introduced to get arguments corresponding to each standard service. This function must be implemented by the EL3 Runtime Firmware and both SP_MIN and BL31 implement it. Change-Id: I38e1b644f797fa4089b20574bd4a10f0419de184
2016-09-22PSCI: Introduce PSCI Library argument structureSoby Mathew
This patch introduces a `psci_lib_args_t` structure which must be passed into `psci_setup()` which is then used to initialize the PSCI library. The `psci_lib_args_t` is a versioned structure so as to enable compatibility checks during library initialization. Both BL31 and SP_MIN are modified to use the new structure. SP_MIN is also modified to add version string and build message as part of its cold boot log just like the other BLs in Trusted Firmware. NOTE: Please be aware that this patch modifies the prototype of `psci_setup()`, which breaks compatibility with EL3 Runtime Firmware (excluding BL31 and SP_MIN) integrated with the PSCI Library. Change-Id: Ic3761db0b790760a7ad664d8a437c72ea5edbcd6
2016-09-22Merge pull request #713 from yatharth-arm/yk/AArch32_portingdanh-arm
Add basic AArch32 support for BL1 & BL2
2016-09-21AArch32: Add support for ARM Cortex-A32 MPCore ProcessorYatharth Kochar
This patch adds ARM Cortex-A32 MPCore Processor support in the CPU specific operations framework. It also includes this support for the Base FVP port. Change-Id: If3697b88678df737c29f79cf3fa1ea2cb6fa565d
2016-09-21AArch32: Support in SP_MIN to receive arguments from BL2Yatharth Kochar
This patch adds support in SP_MIN to receive generic and platform specific arguments from BL2. The new signature is as following: void sp_min_early_platform_setup(void *from_bl2, void *plat_params_from_bl2); ARM platforms have been modified to use this support. Note: Platforms may break if using old signature. Default value for RESET_TO_SP_MIN is changed to 0. Change-Id: I008d4b09fd3803c7b6231587ebf02a047bdba8d0
2016-09-21AArch32: Refactor SP_MIN to support RESET_TO_SP_MINYatharth Kochar
This patch uses the `el3_entrypoint_common` macro to initialize CPU registers, in SP_MIN entrypoint.s file, in both cold and warm boot path. It also adds conditional compilation, in cold and warm boot entry path, based on RESET_TO_SP_MIN. Change-Id: Id493ca840dc7b9e26948dc78ee928e9fdb76b9e4
2016-09-21AArch32: Add ARM platform changes in BL2Yatharth Kochar
This patch adds ARM platform changes in BL2 for AArch32 state. It instantiates a descriptor array for ARM platforms describing image and entrypoint information for `SCP_BL2`, `BL32` and `BL33`. It also enables building of BL2 for ARCH=aarch32. Change-Id: I60dc7a284311eceba401fc789311c50ac746c51e
2016-09-21AArch32: Add generic changes in BL2Yatharth Kochar
This patch adds generic changes in BL2 to support AArch32 state. New AArch32 specific assembly/C files are introduced and some files are moved to AArch32/64 specific folders. BL2 for AArch64 is refactored but functionally identical. BL2 executes in Secure SVC mode in AArch32 state. Change-Id: Ifaacbc2a91f8640876385b953adb24744d9dbde3
2016-09-21AArch32: Add ARM platform changes in BL1Yatharth Kochar
This patch adds ARM platform changes in BL1 for AArch32 state. It also enables building of BL1 for ARCH=aarch32. Change-Id: I079be81a93d027f37b0f7d8bb474b1252bb4cf48
2016-09-21AArch32: Add generic changes in BL1Yatharth Kochar
This patch adds generic changes in BL1 to support AArch32 state. New AArch32 specific assembly/C files are introduced and some files are moved to AArch32/64 specific folders. BL1 for AArch64 is refactored but functionally identical. BL1 executes in Secure Monitor mode in AArch32 state. NOTE: BL1 in AArch32 state ONLY handles BL1_RUN_IMAGE SMC. Change-Id: I6e2296374c7efbf3cf2aa1a0ce8de0732d8c98a5
2016-09-21AArch32: Common changes needed for BL1/BL2Yatharth Kochar
This patch adds common changes to support AArch32 state in BL1 and BL2. Following are the changes: * Added functions for disabling MMU from Secure state. * Added AArch32 specific SMC function. * Added semihosting support. * Added reporting of unhandled exceptions. * Added uniprocessor stack support. * Added `el3_entrypoint_common` macro that can be shared by BL1 and BL32 (SP_MIN) BL stages. The `el3_entrypoint_common` is similar to the AArch64 counterpart with the main difference in the assembly instructions and the registers that are relevant to AArch32 execution state. * Enabled `LOAD_IMAGE_V2` flag in Makefile for `ARCH=aarch32` and added check to make sure that platform has not overridden to disable it. Change-Id: I33c6d8dfefb2e5d142fdfd06a0f4a7332962e1a3
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