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2017-07-30Bump atf-v1.3 to release devel-17.08.1atf-v1.3-armada-17.08Konstantin Porotchkin
Change-Id: I5530e2bd9dc3012847efaca1afc90ef5f6b5d992 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/42335 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com>
2017-07-27fix: dec-win: a3700: roll back PCI decode window to SOC defaultKen Ma
Since Armada3700 17.06 BSP release, PCI decode window has been changed as below in order to support as large memory as possible for 4GB DRAM application. < 17.06 17.06 base 0xE800_0000 0xD8200_00000 size 128MB 64MB The PCI decode window shift caused the backward compability issue to the previous BSP release early than 17.06. This patch rolls back the change to PCI decode window but keeps the other changes in CPU address map for 4GB DRAM application. Please revert the relevant patches in othe BSP components (U-boot & Linux) as well. At a cost, the total available memory for 4GB DRAM application is reduced by 384MB. Please refer to the release notes for the larger memory support. Change-Id: I8aad2426e069d3f89ef53f9b38fed038e3494ffb Signed-off-by: Ken Ma <make@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/42175 Reviewed-by: Wilson Ding <dingwei@marvell.com> Tested-by: Wilson Ding <dingwei@marvell.com>
2017-07-24fix: aro: Missing break command in switch caseChristine Gharzuzi
in case the chosen frequency is 1000/800 the frequency is configured as 2000 Mhz due to missing break command in the case for 1000/800 so it is configured to the default frequency Change-Id: I86555f386d0661328e164f47c6681b9e809e96b2 Signed-off-by: Christine Gharzuzi <chrisg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/42047 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-07-23Bump atf-v1.3 To release devel-17.08.0Konstantin Porotchkin
Change-Id: I3132e4bc34e31641249e2937c36cfe6b60f05924 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/41945 Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2017-07-23fix: svc: Correct the PIDI slow bit positionKonstantin Porotchkin
Correct the shift of PIDI slow bit in the frequency mode and PIDI status. The frequency mode is located in bits[4:0], so the PIDI slow bit[20] should be shifted back by 15 in order to be located in bit[5] of the frequncy mode and not override the bit[4] Change-Id: Ic6ec031ccb4cf7083d5459a14c0485c3e5fd8019 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/42001 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Omri Itach <omrii@marvell.com>
2017-07-20a80x0: add support for Armada 8k OCP boardOfir Fedida
this patch introduces support for new Armada 8k OCP board. - added new platform a80x0_ocp - enabled PCIe EP driver with delay_cfg=1 to allow later EP driver in Linux. - ddr configuration: 1CS 8Gb x5 Samsung devices K4A8G165WB BCRC speed bin 2400S device width x16 verified interfaces: 2 * 10G ethernet ports SPI MMC UART Change-Id: Id723b4a7b4b2f9c590a56417b9ceebe22d5727db Signed-off-by: Ofir Fedida <ofedida@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/41853 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-07-19plat: marvell: increase the secure SRAM size and space for BL31 sizeGrzegorz Jaszczyk
Since the scp_bl2 image is going to be bigger, we need to increase the size of memory required for it. It is not intuitive but BL31_SIZE is used for defining SCP_BL2 size. This can be done since the secure SRAM size is 1MB wide. Change-Id: Ida4a04d69d03376e8bbba713586b85fc66c848f6 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/41640 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Omri Itach <omrii@marvell.com>
2017-07-19fix: mvebu: pcie_dw: set preset request vector to preset4Igal Liberman
This preset is used during the initial part of the equalization master phase. According to hardware measurements, our PCIe hardware can use preset4 or preset6. However, when we try both preset4 and preset6, we might get timeouts, which may cause failure for PCIe endpoint operation. This patch updates the MAC and the PHY to use only preset4. This solves an issue, observed when A7040 PCAC opernates as NIC in a PC (inmod of SNIC module fails). Change-Id: I056cc2ddf93eed937539d3417611f1b16a6aea38 Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/41771 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/41814
2017-07-19fix: mvebu: pcie_dw: set correct hints to lane equalization registerIgal Liberman
Currently, we don't modify the default preset values in lane equalization register which may cause issues with some PCIe GEN3 devices which fail to link up. According to hardware measurements, we must modify the preset values to improve PCIe GEN3 link establishment. Change-Id: Ib93656ee75e6125c0a270550d1fb384111f406f6 Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/41770 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/41813
2017-07-18fix: aro: Fix equation for cpu frequency calculationChristine Gharzuzi
wrong parentheses in the equations for calculating the clusters' frequency which caused booting to freeze when 2000 MHz frequency is chosen Change-Id: I47cd7b7368e4f07ff9e5d7ea55d845613e495558 Signed-off-by: Christine Gharzuzi <chrisg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/41780 Verified-Armada8K: Igal Liberman <igall@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2017-07-17plat/marvell: a80x0_mcbin: add pcie reset release through GPIOIgal Liberman
A8040 MACCHIATObin releases the reset of the PCIe via GPIO (number 52). Currently we perform the reset in u-boot which might be too late for some PCIe endpoints. This patch adds the required code to get the PCIe card out of reset and adds a weak stub for other platforms which do not require this. Change-Id: I43a2e20d091985cf858165d36dc7a8911d0457e0 Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/41656 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2017-07-16atf: ARO: Introduce Adaptive Ring OscillatorChristine Gharzuzi
is a clock generator, which is used in AP806 as a source clock for the CPU clusters. In AP806 the ARO is not the major clock, and this document discuss the way to switch from PLL mode (which is the default mode) to ARO mode. The motivation for ARO usage is improving the Yield of the device at 2Ghz and improving the power consumption at that work point. In general – ARO allow lower Vmin for running in this premium work point which serves both cause (yield and power). Change-Id: I76a391a29cd98abedcd003f52d37a60459ee8b80 Signed-off-by: Christine Gharzuzi <chrisg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/40640 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Hanna Hawa <hannah@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-07-13pm: a8k: add initial support for suspend to RAMKonstantin Porotchkin
Add initial support for suspend to RAM feature. The warm boot mode (recovery) is detected at BLE stage and the control leaves the BootROM for eliminating boot device image copy and verification. Then booting CPU jumps to ATF and continues system restore bypassing further BootROM stages, and finnaly jumps back to Linux bypassing the u-boot. Change-Id: Ifbafd783d5b554bfe50de6c4829e93e40cd28631 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Victor Gu <xigu@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/40478 Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2017-07-13ble: a8k: svc: Add initial SVC supportKonstantin Porotchkin
Add support for SVC functionality according to specification version 0.4 The "Rev0" and "Premium" efuse values are voluntary assigned since are still missing in the feature definition documents. The feature is inteded to configure AVS value according to eFuse values that are burned individually for each SoC during the test process. Primary AVS value is stored in HD efuse and processed on power on by the HW engine. Secondary AVS value is located in LD efuse and contains 3 work points for various CPU frequencies. The Secondary AVS value is only taken into account if the Revision ID stored in the efuse matches the expected value, the CPU is running in a certain speed and the SoC Bin matches the value selected for the AVS update. Change-Id: I42e6e6958988becbb07779ed02ef0f4d6edee2ea Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/40604 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Omri Itach <omrii@marvell.com>
2017-07-12ble: prepare DRAM for running in warm boot modeKonstantin Porotchkin
The DRAM is marked as non-executable memory segment in BootROM. In the Warm Boot mode the control should be passed from BLE to the ATF that already exists in the DRAM. This is needed for eliminating the unnecessary boot image reload from the boot device. This patch marks the DRAM as an executable memory. Change-Id: I29a9d4e6a47cd664ce7040c270537690f1f1254e Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/40474 Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2017-07-12pm: add plat PM definitions and make mailbox code genericKonstantin Porotchkin
Add new common platform header file for Marvell PM usage. Remove A37xx-specific code from the common PM sources. Change-Id: I8cb55c9e66ce503bbe3f359e7c1b04eaca1a4f9d Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Victor Gu <xigu@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/40476 Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2017-07-11platform: Add support for Armada 3900 familyKevin Shi
Add platform support files for Marvell Armada 3900 SoC family. A3900 is repackaged from armada-7040. AP - APN806 *1 CP - CPN-110 *1 RFU: - map 0xf900_0000 to mochi endpoint. IOB: - remove PCI-1 0xf700_0000 mapping and reserve it for PCI0/PCI2 io space mapping Add fetures: - Add mochi support Change-Id: I9f636d2d8fa7354eb62327550d5b9006a43a50dc Signed-off-by: Kevin Shi <kshi@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/41455 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-07-11pm: a8k: Add get_sys_suspend_power_state handlerKonstantin Porotchkin
Implement the missing get_sys_suspend_power_state handler in patform PM module for enabling "suspend to RAM" support in Linux kernel Change-Id: Ia6a4efc417ca5fc90f274a151b0bff93b679f9c1 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/40477 Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2017-07-11ble: reduce the DRAM init mesasge log levelKonstantin Porotchkin
Change the notification about DRAM init from NOTICE to INFO level. This output is not really required in a normal boot mode an will slow down recovery in warm boot. Change-Id: Id7036650cb192da1d2dd30bfc94534846c010196 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Victor Gu <xigu@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/40475 Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2017-07-11Bump atf-v1.3 To release devel-17.06.1 for Armada7020 AMCVictor Gu
Change-Id: I2eab9f3082a257bf161301b260ad304e1cd360fd Signed-off-by: Victor Gu <xigu@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/40695 Reviewed-by: Hanna Hawa <hannah@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-07-10ap806: pm: poweroff unused CPUs at early boot stageOmri Itach
The entire boot flow is performed via CPU0, while CPUs1-3 remain unused untill Linux is booted. During this stage, CPU1-3 are kept in reset (not powered off), hence still consuming current and leading to increased SoC temperatures. To avoid unnecessary current consumption, and mainly to reduce SoC temperatures, unused CPUs are powered off (CPU1 in dual-core system, and CPU1-3 in quad-core systems), at early BLE stage, prior to DDR initialization, and powered back on during Linux PSCI calls to a8k_pwr_domain_on, before getting these CPUs out of reset. This patch was tested on Armada 8040 MACCHIATObin, and it leads to ~10-15% reduction of current consumption and SoC temperature in U-Boot. Change-Id: Ic1baeaa89f2806125d8347badcf5b30c13583162 Signed-off-by: Omri Itach <omrii@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/40869 Reviewed-by: Hanna Hawa <hannah@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-07-09fix: ddr: select spd mem page 0 to get dram configVictor Axelrod
This patch replaces the i2c read to write operation to 0x36 device to select SPD memory page 0 in order to access DRAM configuration data. The read operation returns Ack when the current page is 0 or NoAck when the current page is 1, while the write operation actually sets the current page to 0. Change-Id: Iab2b78d005b5967c75d0544f6f7770631165db7e Signed-off-by: Victor Axelrod <victora@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/41184 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-07-06doc: a3700: update build file to add ddr3 1cs 1GB supportzachary
This patch adds build option DDR_TOPOLOGY number to support DDR3 1cs 1GB build. Example: make DEBUG=1 USE_COHERENT_MEM=0 DDR_TOPOLOGY=4 PLAT=a3700 all fip Change-Id: If19dd6636847fba4c03172c1315aab0a646f9d26 Signed-off-by: zachary <zhangzg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/40547 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Hua Jing <jinghua@marvell.com> Reviewed-by: Wilson Ding <dingwei@marvell.com> Reviewed-by: Gina Tadmore <gina@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com>
2017-06-29fix: doc: porting: Fix wrong file name of the address mapKonstantin Porotchkin
Fix wrong reference to the file name containing the SoC memory map. Change-Id: Ia95b2eff64d96b8517714bb2674b65756fd8d0eb Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/40605 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Neta Zur Hershkovits <neta@marvell.com>
2017-06-29plat/marvell/a80x0_cust: reconfigure CP0 PCIx4 windowsArd Biesheuvel
In order to allow the use of PCIe cards such as graphics cards, whose demands for BAR space are typically much higher than those of network or SATA/USB cards, reconfigure the I/O windows so we can declare two MMIO PCI regions: a 512 MB MMIO32 one at 0xc000_0000 and a 4 GB MMIO64 one at 0x8_0000_0000. In addition, this will leave ample room for an ECAM config space at 0xe000_0000 (up to the ECAM maximum of 256 MB) For compatibility with older kernels or firmware, leave the original 16 MB window in place as well. Change-Id: I78daec1650ebc28d11e565ec1eceecffdb45c545 Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Reviewed-on: http://vgitil04.il.marvell.com:8080/40788 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com>
2017-06-27Revert "fix: pcie: temporarily disable pcie clock fix"Igal Liberman
This reverts commit 3cf300e7695e6883787ce01d5c4b97ced96bb8c1. Following u-boot 2017 fix, we can use the correct setting for PCIe clock direction. Change-Id: If65ffad0bb507392d7815d00ef6dff62d5ccb9dc Reviewed-on: http://vgitil04.il.marvell.com:8080/40780 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-06-26fix: makefile: a3700: pad boot-image.bin for 4-bytes alignmentallen yan
- In eMMC download mode, the ROM checks if the size and address are aligned to 4 byte. If not aligned, it will report SDMMC_ADDR_MISALIGN_ERROR. - This patch align the boot-image.bin size to 4 bytes. Change-Id: I97f390c78797ca403f0353bdd9c99625ab412eb3 Signed-off-by: allen yan <yanwei@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/40661 Reviewed-by: Wilson Ding <dingwei@marvell.com> Tested-by: Wilson Ding <dingwei@marvell.com>
2017-06-25tools: doimage: Remove support for the REG headerKonstantin Porotchkin
Remove support for the register type header from doimage tool. This header type is a legacy one and not used in modern SoCs. Change-Id: I2a1fe4380115c20fcf0296d0c0f63d4be8d69594 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/40628 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Hanna Hawa <hannah@marvell.com>
2017-06-22a7k: add AMC board supportVictor Gu
This patch adds support for ARMADA-7020 AMC board, including DRAM topology and board relevant addressing mapping settings. Change-Id: Icee0c73eddc26e337d676be66cc10a95e3e7cca1 Signed-off-by: Victor Gu <xigu@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/40200 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Hanna Hawa <hannah@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-06-21ble: makefile: force mv_ddr dir visit and allow parallel buildVictor Axelrod
This patch forces to visit mv_ddr directory making mv_ddr changes to be visible to the build system, and allows to build mv_ddr in parallel. Change-Id: I2a198b0ce577bcc425b74beef143cf81a66367fe Signed-off-by: Victor Axelrod <victora@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/40638 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-06-19fix: xdb: a80x0: a70x0: update xdb recovery scriptDavid Sniatkiwicz
update xdb recovery script for a80x0 and a70x0 bootloader recovery. Remove Armada-80x0-RZ support from XDB scripts Remove BLx & U-Boot debug option, the XDB scripts will be used for recovery only. Change-Id: Icb176691f05855440411ddcf908ea63c5bc4c33f Signed-off-by: David Sniatkiwicz <davidsn@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/40363 Reviewed-by: Hanna Hawa <hannah@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/40590
2017-06-18i2c: a8k: unstuck when start clear bit timeoutsAnton
When performing back-to-back resets (~1s apart) SPD I2C fails as the bus gets stuck: ERROR: Start clear bit timeout Release the bus using the "unstuck" register. This requires to soft-reset to complete successfully (otherwise I2C drives to finish the requested start/stop and interferes with unstuck FSM). On successful completion of unstuck process reset i2c again. The solution assumes failure occurs on the first access, therefore -EAGAIN returned triggers a re-try and SPD access is completed successfully: NOTICE: Gathering DRAM information ERROR: Start clear bit timeout Trying to "unstuck i2c"... ok mv_ddr: version 16.12.1 mv_ddr: scrubbing memory... Change-Id: I6a3a5ccb45edd0472de770ba55b747e6b6d357ff Signed-off-by: Anton <antone@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/40573 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-06-18i2c: a8k: add comment which describes baudrate settingsNeta Zur
Change-Id: I6b62e8ff3089542bd9d1c49ff7f85eab98533deb Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Neta Zur <neta@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/40574 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-06-04doc: a3700: update build.txt for wtptp tool updatejinghua
This patch udpates the build doc for A3700: - Adds build option WTP, which points to wtp tool source code tree directory. - Removes tbb tools installation part, since it is not needed anymore. Change-Id: I6fcdf67435aae0b86e9682d8a05d00fcf719737e Signed-off-by: jinghua <jinghua@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/40080 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/40118 Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2017-05-29ble: set binary extension size to max per specVictor Axelrod
This patch sets the binary extension size close to its maximum as defined by the specification. The upper limit may be set to 0xffe7c000 (0xffe1c000 + 384KB), but actually set to 0xffe7800 to provide 16KB for the secure extension of 9,956 bytes size. Change-Id: Id6e78eba95ab9d0e5241c7b70d750cb5b39230b1 Signed-off-by: Victor Axelrod <victora@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/37789 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/40002 Reviewed-on: http://vgitil04.il.marvell.com:8080/40014
2017-05-22fix: mci: remove redundant enablement of register-mode accessOmri Itach
according to design guidelines, enablement of register-mode access (mci_enable_phy_regs_access) is redundant and should not performed as a part of MCI initialization for A80x0-A1. Change-Id: I7b8fb70a4d6fa518ee56c64556305210a183f7a6 Signed-off-by: Omri Itach <omrii@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39746 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39761
2017-05-22fix: mci: Fine tune of MCI parametersOmri Itach
At AP and CP //reg[15:8] – RX NQ threshold reduced to 0x7 //reg[23:16] – RX PQ threshold reduced to 0x7 //reg[31:24] – RX RQ threshold reduced to 0x7 //reg[7:4] – RX delta threshold reduced to 0x2 At AP: //reg[4:0] – WR outstanding reduced to 0x6 (0x5 written to reg) //reg[10:6] – RD outstanding reduced to 0x6 (0x5 written to reg) At CP: //reg[10:6] – RD outstanding reduced to d’14 (d’13 written to reg) Change-Id: I00d1f22501d22171015873a1b12224e0c0443fbe Signed-off-by: Omri Itach <omrii@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39526 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> (cherry picked from commit cbcf48899360940826678e370d5c247bb782938d) Reviewed-on: http://vgitil04.il.marvell.com:8080/39797
2017-05-22fix: mci: ap806: skip setting MCI ID assignment when booting from MCIOmri Itach
When boot source is from MCI, bootROM is already enabling MCI simultaneous transactions (ID assignment), so in that case we must avoid enabling it for the 2nd time (according to design guidelines). Change-Id: I3967fc3526e27356f9e8ebf184b52cc21003e3c1 Signed-off-by: Omri Itach <omrii@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39557 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> (cherry picked from commit c721c97f7ea0724d3eaed92168897db4fc1b9b03) Reviewed-on: http://vgitil04.il.marvell.com:8080/39795
2017-05-22fix: pcie: temporarily disable pcie clock fixIgal Liberman
After commit "f82b49e fix: pcie: cp110: fix pcie clock selection" we encountered some instabilities in PCIe. This patch disables the PCIe clock fix temporarily, until we figure out the root cause for this this issue. Change-Id: I521e4495118fab2bcbe1e99e6080d1cbb2b08f39 Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39663 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39759
2017-05-17fix: pcie: fix pcie clock selection for A2 revisionIgal Liberman
This patch fixes incorrect handling of pcie clock: If pcie_clk is set to input (by the Sample-at-Reset), PCIE refclk buffer 0/1 source field in PCIe_Reference_Clock_Buffer_Control register should be set to 1 and not 0 as it done now. Change-Id: I14fedce9d3299b5b85eb742048f03b17f1f9ab14 Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39456 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39544
2017-05-16fix: mvebu: pcie: set correct preset4 valueIgal Liberman
Currently, incorrect preset4 value is used. This patch fixes the preset4 according to HW measurments. Change-Id: I839a6c843e912182bb0c71e3ab836dac27ce8a97 Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39421 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39491
2017-05-16fix: pcie: cp110: update analog parameters according to latest ETPIgal Liberman
Add PCIE analog parameters initialization values according to latest ETP. Change-Id: I3f5892702610e46ebaba7485e3cef5817f1518b5 Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/36995 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39411 Reviewed-on: http://vgitil04.il.marvell.com:8080/39490
2017-05-12Bump atf-v1.3 to release devel-17.06.0Konstantin Porotchkin
Change-Id: I11ee81c5741cbe5b7d1f07f57aed095a3f31c182 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39323 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Wilson Ding <dingwei@marvell.com>
2017-05-12makefile: a3700: move opthash.txt file to build folder for trusted buildTerry Zhou
The 'opthash.txt' contains the KAK key digest, which is used by the customer to program the fuse for the trusted boot. Change-Id: I5d7e095a6b48a0c5cb8587c2a8e0063e7988ab7e Signed-off-by: zachary <zhangzg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39356 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Wilson Ding <dingwei@marvell.com>
2017-05-12fix: makefile: a3700: correct DOIMAGEPATH assignmentzachary
DOIMAGEPATH used to get its path by 'dir' command when Makefile assigns the WTP path to it. The 'dir' command returns the left string from the last "/" of the file or directory path. Therefore, the actual DOIMAGEPATH is missing one level directory without one extra "/" in WTP export env. This patch fixed this issue by assign the WTP path to DOIMAGEPATH directly. Change-Id: I2b18b13f2d3283e714ec6bfa47db6d477295f9c1 Signed-off-by: zachary <zhangzg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39355 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Wilson Ding <dingwei@marvell.com>
2017-05-12a3700: add unnecessary files to gitignore listzachary
Added the intermediate files "CSK*-KeyHash.txt" and "TIMHash.txt" and "Tim_msg.txt" files to gitignore list, which are generated by boot image generated tool Change-Id: I3c880f898d4c46a20e85ee3202677a9f682615dc Signed-off-by: zachary <zhangzg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39286 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Wilson Ding <dingwei@marvell.com>
2017-05-12makefile: a3700: remove unnecessary files after buildzachary
Remove "CSKN-KeyHash.txt" and Hash.txt after building trusted image Remove "TIMHash.txt" and "Tim_msg.txt" after building untrusted image Change-Id: I6ce675f39d49c3cd6538205acefd5e64685d6fbf Signed-off-by: zachary <zhangzg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39358 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Terry Zhou <bjzhou@marvell.com> Reviewed-by: Wilson Ding <dingwei@marvell.com>
2017-05-12fix: a3700: Fix the issue of make distcleanTerry Zhou
Armada37x0's ATF compilation includes native ATF code and external WTP component. Thus, WTP component should also be cleaned up along with ATF. However, WTP path is now tied to DOIMAGEPATH, which is different from the default for other Marvell SoCs. Thus, PLAT option is required in order to clean up the WTP component: make PLAT=a3700 WTP=<path/to/wtp> distclean/clean ATF always invokes make clean for "CRTTOOLPATH". When specifying PLAT option in "make clean" command, it will validate the "include" folder under "PLAT_DIR", which expects "include" folder located in the same directory of "platform.mk". Since the existing Armada37x0's PLAT directory doesn't compiles with ATF convention, it caused the error in "make clean". The temporary solution is to add a symbolic link named as 'include' under "PLAT_DIR", which points to itself. This WA will be removed after 'plat/marvell/a3700' folder is reorganized. Change-Id: I95bea27f3999b6490103aec56197eecee2cdd8b6 Signed-off-by: Terry Zhou <bjzhou@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39357 Reviewed-by: Wilson Ding <dingwei@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2017-05-11fix: ap806: enable 48-bit virtual addressMarcin Wojtas
Issue found when enable 48-bit Virtual Address in kernel In ARMv8 the CPU can work with 48-bit virtual address, at this case for propagating TLB maintenance 44-bit of Physical address are needed. Marvell interconnect is configured to be 40-bit address by default, therefore AxAddr[43:40] are not propagated so the DVM is not working. Change-Id: I7b8a3ec7960697814079f2c932fd06962bfa4c75 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39185 Reviewed-by: Igal Liberman <igall@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Hanna Hawa <hannah@marvell.com>
2017-05-11script: a3700: add static startup scripts for XDBKen Ma
This patch adds static startup XDB scripts for Armada37x0: - The DDR will be initialized, but only the first 512MB, which is good enough for board recovery - The first dram cpu decoder window size will be set; - BL1 and FIP will be loaded and executed by default. Change-Id: I4ec4cdb7dcded4d9757fa647d00c977ab4de3b63 Signed-off-by: Ken Ma <make@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39249 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-by: Wilson Ding <dingwei@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
generated by cgit (git 2.34.1) at 2024-04-28 18:36:45 +0000