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2018-04-23Bump atf-v1.3 to release armada-17.10.8atf-v1.3-armada-17.10Konstantin Porotchkin
Change-Id: I22853188c8097d7d17a51f7516257a2a127f4f89 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/53513 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com>
2018-04-15plat: marvell: Enable CA72 Errata 859971 handlingKonstantin Porotchkin
Enable handling of CA72 Errata 859971 on A8K platform. Change-Id: I7fade6519c630c2f3840ac7c3f1fc5b7416eba05 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/52579 Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2018-04-15Add support for SMCCC_VERSION in PSCI featuresDimitris Papastamos
On some platforms it may be necessary to discover the SMCCC version via a PSCI features call. Change-Id: I95281ac2263ca9aefda1809eb03464fbdb8ac24d Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/52578 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-04-15runtime_exceptions: Save x4-x29 unconditionallyDimitris Papastamos
In preparation for SMCCC v1.1 support, save x4 to x29 unconditionally. Previously we expected callers coming from AArch64 mode to preserve x8-x17. This is no longer the case with SMCCC v1.1 as AArch64 callers only need to save x0-x3. Change-Id: Ie62d620776533969ff4a02c635422f1b9208be9c Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/52577 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-04-15Optimize SMCCC_ARCH_WORKAROUND_1 on Cortex A57/A72/A73 and A75Dimitris Papastamos
This patch implements a fast path for this SMC call on affected PEs by detecting and returning immediately after executing the workaround. NOTE: The MMU disable/enable workaround now assumes that the MMU was enabled on entry to EL3. This is a valid assumption as the code turns on the MMU after reset and leaves it on until the core powers off. Change-Id: I13c336d06a52297620a9760fb2461b4d606a30b3 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/52575 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-04-15Implement support for SMCCC v1.1Dimitris Papastamos
SMCCC v1.1 comes with a relaxed calling convention for AArch64 callers. The caller only needs to save x0-x3 before doing an SMC call. This patch adds support for SMCCC_VERSION and SMCCC_ARCH_FEATURES. Refer to "Firmware Interfaces for mitigating CVE_2017_5715 System Software on Arm Systems"[0] for more information. [0] https://developer.arm.com/-/media/developer/pdf/ARM%20DEN%200070A%20Firmware%20interfaces%20for%20mitigating%20CVE-2017-5715_V1.0.pdf Change-Id: If5b1c55c17d6c5c7cb9c2c3ed355d3a91cdad0a9 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/52576 Tested-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-04-15Optimize/cleanup BPIALL workaroundDimitris Papastamos
In the initial implementation of this workaround we used a dedicated workaround context to save/restore state. This patch reduces the footprint as no additional context is needed. Additionally, this patch reduces the memory loads and stores by 20%, reduces the instruction count and exploits static branch prediction to optimize the SMC path. Change-Id: Ia9f6bf06fbf8a9037cfe7f1f1fb32e8aec38ec7d Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/52574 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-04-15Workaround for CVE-2017-5715 on Cortex A73 and A75Dimitris Papastamos
Invalidate the Branch Target Buffer (BTB) on entry to EL3 by temporarily dropping into AArch32 Secure-EL1 and executing the `BPIALL` instruction. This is achieved by using 3 vector tables. There is the runtime vector table which is used to handle exceptions and 2 additional tables which are required to implement this workaround. The additional tables are `vbar0` and `vbar1`. The sequence of events for handling a single exception is as follows: 1) Install vector table `vbar0` which saves the CPU context on entry to EL3 and sets up the Secure-EL1 context to execute in AArch32 mode with the MMU disabled and I$ enabled. This is the default vector table. 2) Before doing an ERET into Secure-EL1, switch vbar to point to another vector table `vbar1`. This is required to restore EL3 state when returning from the workaround, before proceeding with normal EL3 exception handling. 3) While in Secure-EL1, the `BPIALL` instruction is executed and an SMC call back to EL3 is performed. 4) On entry to EL3 from Secure-EL1, the saved context from step 1) is restored. The vbar is switched to point to `vbar0` in preparation to handle further exceptions. Finally a branch to the runtime vector table entry is taken to complete the handling of the original exception. This workaround is enabled by default on the affected CPUs. NOTE ==== There are 4 different stubs in Secure-EL1. Each stub corresponds to an exception type such as Sync/IRQ/FIQ/SError. Each stub will move a different value in `R0` before doing an SMC call back into EL3. Without this piece of information it would not be possible to know what the original exception type was as we cannot use `ESR_EL3` to distinguish between IRQs and FIQs. Change-Id: I90b32d14a3735290b48685d43c70c99daaa4b434 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/52573 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-04-15Disable workaround for CVE-2017-5715 on unaffected platformsDimitris Papastamos
Change-Id: Ib67b841ab621ca1ace3280e44cf3e1d83052cb73 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/52572 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-04-15Print erratum application report for CVE-2017-5715Dimitris Papastamos
Even though the workaround for CVE-2017-5715 is not a CPU erratum, the code is piggybacking on the errata framework to print whether the workaround was applied, missing or not needed. Change-Id: I821197a4b8560c73fd894cd7cd9ecf9503c72fa3 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/52571 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-04-15Change the default errata format stringDimitris Papastamos
As we are using the errata framework to handle workarounds in a more general sense, change the default string to reflect that. Change-Id: I2e266af2392c9d95e18fe4e965f9a1d46fd0e95e Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/52570 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-04-15Cortex-A72: Implement workaround for erratum 859971Eleanor Bonnici
Erratum 855971 applies to revision r0p3 or earlier Cortex-A72 CPUs. The recommended workaround is to disable instruction prefetch. Change-Id: I7fde74ee2a8a23b2a8a1891b260f0eb909fad4bf Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com> Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/52568 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-04-15Report errata workaround status to consoleJeenu Viswambharan
The errata reporting policy is as follows: - If an errata workaround is enabled - If it applies (i.e. the CPU is affected by the errata), an INFO message is printed, confirming that the errata workaround has been applied. - If it does not apply, a VERBOSE message is printed, confirming that the errata workaround has been skipped. - If an errata workaround is not enabled, but would have applied had it been, a WARN message is printed, alerting that errata workaround is missing. The CPU errata messages are printed by both BL1 (primary CPU only) and runtime firmware on debug builds, once for each CPU/errata combination. Relevant output from Juno r1 console when ARM Trusted Firmware is built with PLAT=juno LOG_LEVEL=50 DEBUG=1: VERBOSE: BL1: cortex_a57: errata workaround for 806969 was not applied VERBOSE: BL1: cortex_a57: errata workaround for 813420 was not applied INFO: BL1: cortex_a57: errata workaround for disable_ldnp_overread was applied WARNING: BL1: cortex_a57: errata workaround for 826974 was missing! WARNING: BL1: cortex_a57: errata workaround for 826977 was missing! WARNING: BL1: cortex_a57: errata workaround for 828024 was missing! WARNING: BL1: cortex_a57: errata workaround for 829520 was missing! WARNING: BL1: cortex_a57: errata workaround for 833471 was missing! ... VERBOSE: BL31: cortex_a57: errata workaround for 806969 was not applied VERBOSE: BL31: cortex_a57: errata workaround for 813420 was not applied INFO: BL31: cortex_a57: errata workaround for disable_ldnp_overread was applied WARNING: BL31: cortex_a57: errata workaround for 826974 was missing! WARNING: BL31: cortex_a57: errata workaround for 826977 was missing! WARNING: BL31: cortex_a57: errata workaround for 828024 was missing! WARNING: BL31: cortex_a57: errata workaround for 829520 was missing! WARNING: BL31: cortex_a57: errata workaround for 833471 was missing! ... VERBOSE: BL31: cortex_a53: errata workaround for 826319 was not applied INFO: BL31: cortex_a53: errata workaround for disable_non_temporal_hint was applied Also update documentation. Change-Id: Iccf059d3348adb876ca121cdf5207bdbbacf2aba Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/52569 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-04-15tspd:FWU:Fix usage of SMC_RET0Antonio Nino Diaz
SMC_RET0 should only be used when the SMC code works as a function that returns void. If the code of the SMC uses SMC_RET1 to return a value to signify success and doesn't return anything in case of an error (or the other way around) SMC_RET1 should always be used to return clearly identifiable values. This patch fixes two cases in which the code used SMC_RET0 instead of SMC_RET1. It also introduces the define SMC_OK to use when an SMC must return a value to tell that it succeeded, the same way as SMC_UNK is used in case of failure. Change-Id: Ie4278b51559e4262aced13bbde4e844023270582 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/52567 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-04-15Allow spin locks to be defined from assemblyJeenu Viswambharan
At present, spin locks can only defined from C files. Add some macros such that they can be defined from assembly files too. Change-Id: I64f0c214062f5c15b3c8b412c7f25c908e87d970 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/52566 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-03-22fix: Makefile: a3700: align wtmi image with 4 bytesjinghua
To boot from eMMC, there is a limitation that each firmware component size has to be aligned with 4 bytes. Since u-boot image has already been aligned, this patch does it for WTMI image. Change-Id: Ie8f4517d5f04baedc7bca2bd230c5ce2f73b3e3a Signed-off-by: jinghua <jinghua@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/52417 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2018-02-05Bump atf-v1.3 to release armada-17.10.7Konstantin Porotchkin
Change-Id: I0de5108b1e4c71ccbb937637f6970950742cc05e Reviewed-on: http://vgitil04.il.marvell.com:8080/49998 Reviewed-by: Neta Zur Hershkovits <neta@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2018-02-04Fix dimensions of psci_req_local_pwr_statesBernhard Rosenkränzer
Wrong array size cause compilation error when using GCC 7.2: lib/psci/psci_common.c: In function ‘psci_do_state_coordination’: lib/psci/psci_common.c:220:27: error: array subscript is above array bounds [-Werror=array-bounds] psci_req_local_pwr_states[pwrlvl - 1][cpu_idx] = req_pwr_state; Change-Id: I5dc189e9624a3773e6f10d56d949d66c18c98206 Signed-off-by: Bernhard Rosenkränzer <bero@lindev.ch> Reviewed-on: http://vgitil04.il.marvell.com:8080/49631 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Nadav Haklai <nadavh@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-01-28fix: a8k: svc: Fix the voltage settings for a7040 @ 1600MHzKonstantin Porotchkin
For A7040 running at 1600MHz the SVC workpoint should not be changed. Change-Id: Ied44e34ffd71989b5a309f07ae29ba5a52d497ff Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/49627 Reviewed-by: Ilan Dahan <iland@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Igor Shapiro <ishapiro@marvell.com>
2018-01-22Bump atf-v1.3 to release armada-17.10.6Igal Liberman
Change-Id: I522e9d9768278f07f03767d8c34f42c968ffc827 Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/49331 Reviewed-by: Nadav Haklai <nadavh@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2018-01-22Workaround for CVE-2017-5715 on Cortex A57 and A72Dimitris Papastamos
Invalidate the Branch Target Buffer (BTB) on entry to EL3 by disabling and enabling the MMU. To achieve this without performing any branch instruction, a per-cpu vbar is installed which executes the workaround and then branches off to the corresponding vector entry in the main vector table. A side effect of this change is that the main vbar is configured before any reset handling. This is to allow the per-cpu reset function to override the vbar setting. This workaround is enabled by default on the affected CPUs. Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com> Change-Id: I135c4173b4f5a16186c8b2e85dc5adb21e041b0b [Resolve conflicts] Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/48855 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com>
2017-12-18Bump atf-v1.3 to release armada-17.10.5Konstantin Porotchkin
Change-Id: Iea0de5f079c1f8e487822f2d94c46e9787eb31c3 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/47753 Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2017-12-18marvell: svc: Update the SVC algorithm to v0.10Konstantin Porotchkin
Update SVC flow according to definitions v0.10 Change-Id: I36934e915554401a203f6617bf25da1e0419909f Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/47625 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com>
2017-11-28Bump atf-v1.3 to release armada-17.10.4Konstantin Porotchkin
Change-Id: Ia007e2b61b78ad83eec6401cba0ee41280dfd2a6 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/46982 Reviewed-by: Igal Liberman <igall@marvell.com>
2017-11-27marvell: svc: Update the SVC algorithm to v0.8Konstantin Porotchkin
Add parity check for WP efuse values according to SVC definition version 0.8 Change-Id: I5221975bbc2ec02cf07b2ca68b5a4f36aa6087a9 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/46753 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Ilan Dahan <iland@marvell.com> Reviewed-by: Neta Zur Hershkovits <neta@marvell.com>
2017-11-23plat/marvell: a70x0: configure Direct Mode window for SPI flashMarcin Wojtas
In order to be able to support UEFI variables, direct mode access to the SPI flash is required. The variables will be placed at 4MB - 256KB offset. For this purpose at offset 0xf9000000 configure new window pointing to the CP0 SPI1 CS0 device. Change-Id: I61402b8741a07cf12e35050de48bbf39baeb4cbb Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/46713 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-11-23plat/marvell: a80x0: configure Direct Mode window for SPI flashMarcin Wojtas
In order to be able to support UEFI variables, direct mode access to the SPI flash is required. The variables will be placed at 4MB - 256KB offset. For this purpose at offset 0xf9000000 configure new window pointing to the CP1 SPI1 CS0 device. Because the platform supports maximum amount of 6 IO windows, existing window for CP1 PCIE0 was extended to cover the SPI area as well. Change-Id: I5ef5eb4ac95f86d78a4af7f474127a04dd083254 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/46712 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-11-23plat/marvell: a80x0_mcbin: configure Direct Mode window for SPI flashMarcin Wojtas
In order to be able to support UEFI variables, direct mode access to the SPI flash is required. The variables will be placed at 4MB - 256KB offset. For this purpose at offset 0xf9000000 configure new window pointing to the CP1 SPI1 CS0 device. Because the platform supports maximum amount of 6 IO windows, CP1 PCIE0 window had to be be extended to cover the SPI area as well. Change-Id: I125ebfb5259549e2ea0d0d2c76296e4167c6ca45 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/46711 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-11-22pm: mvebu: remove operation before jumping back to ATFVictor Gu
Before jumping back DDR to execute ATF during system resume, need to run cache maintenance operations. This patch removes current code, another patch will re-write the code to be more generic. Change-Id: I6059525abfe04c1a6c80486a3483b8c671f48270 Signed-off-by: Victor Gu <xigu@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/46246 Reviewed-by: Neta Zur Hershkovits <neta@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/46631
2017-11-21plat: marvell: a8k: make SCP_BL2 image mandatory for a8k familyGrzegorz Jaszczyk
Force build with SCP_BL2 on a80x0 boards. This enforcement ensures that the required service CPU executable is always incluided in the final system flash image. Change-Id: I6efe32ec20ab5e193e56273b016a76f646d2c4ee Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/46209 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Yoav Gvili <ygvili@marvell.com>
2017-10-03Bump atf-v1.3 to release armada-17.10.3Konstantin Porotchkin
Change-Id: Ifa961b6dc4f4484cfe687e891ab9ca577f77ab2f Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/44998 Reviewed-by: Neta Zur Hershkovits <neta@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2017-10-03a8k: svc: Update the SVC flow to version 0.6Konstantin Porotchkin
Update the SVC flow according to the version 0.6 specification. Change-Id: I2af1e14a407a01badb965b2394986d86370f4499 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/44997 Reviewed-by: Neta Zur Hershkovits <neta@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2017-09-24Bump atf-v1.3 to release armada-17.10.2Konstantin Porotchkin
Change-Id: Ifb062c279a05ea746e9a1345b5a4e6aafd982c59 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/44592 Reviewed-by: Igal Liberman <igall@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2017-09-24fix: mci: fix uart recovery by correctly determining when to skip mci confGrzegorz Jaszczyk
The process of enabling MCI simultaneous transactions is performed in bootrom when the source id is SAR_MCIX4. Because according to design guidelines the MCI simultaneous transaction shouldn't be enabled more then once, atf code verified if this configuration was performed by bootrom, by determining boot source. Hitherto verification wasn't sufficient in case of uart recovery(boot from uart) since the bootrom flow is different and mentioned initialization is skipped even if boot source is SAR_MCIX4. The new verification base on appropriate mci's register content: if the appropriate reg contains 0x0 it means that the bootrom didn't perform required mci configuration. Before this patch after uart recovery the CPU hang was observed, since MCI wasn't configured to allow simultaneous read/write transaction (e.g. doing AP to CP1 access over MCI and vice-versa triggered the issue). Change-Id: I9514bbd7ecac4282206be54a98b278cdf2ddd4e8 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/44567 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-09-19Bump atf-v1.3 to release armada-17.10.1Konstantin Porotchkin
Change-Id: I3547c2a12ed73270bcdaeb15862d1ec45e192346 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/44474 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Neta Zur Hershkovits <neta@marvell.com>
2017-09-07plat: marvell: a8k: add missing check for scp bl2 addrNeta Zur
Commit "plat: marvell: a8k: allow to load scp_bl2 firmware that doesn't contain PM FW" add scp_bl2 related checks done at runtime. Nevertheless it occurred that during build with debugs enabled and SCP_BL2 undefined, the build error was triggered. Adding preprocessor checks for SCP_BL2_BASE fixes that issue. Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Change-Id: I8aa127ef389c7549035b43cb63e67d83edb831c1 Signed-off-by: Neta Zur <neta@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43973 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Omri Itach <omrii@marvell.com>
2017-09-03Bump atf-v1.3 to release armada-17.10.0Konstantin Porotchkin
Change-Id: I59a7c1c88fd2efc51a8717624b78e1540fc2d290 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43655 Reviewed-by: Igal Liberman <igall@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2017-09-03fix: tee: Update TEE dispatcher patchKonstantin Porotchkin
- Fix the Marvell TEE dispatcher patch failed to apply after moving to the new documentation format. Change-Id: I7b86544b205d481ea88d3f6e7eb1c53b1f982f8b Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43652 Reviewed-by: Nadav Haklai <nadavh@marvell.com>
2017-08-31pcie: a8040_ocp: pcie stabilization configurationsIgal Liberman
This patch optimizes the pcie comphy receiver and transmitter configuration. It includes the following optimizations: RX - Force FFE constant values instead of trained values TX - Increase the full swing value and update all presets (p0 - p10) accordingly Change-Id: I6e48d543eb343b453ed804d9b48bcfec86c30225 Signed-off-by: Ofir Fedida <ofedida@marvell.com> Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43426 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-08-31fix: mci: adjust backoff thresholds and the outstanding transactions limitsOmri Itach
update parameters for various backoff thresholds and the limits of the outstanding transactions. This is to prevent backoff at all the queues, except for the PQ of AP (writes from CP to AP), which cannot be prevented. Changes list: 1) Global RX backoff threshold changed from 0xB to 0x3f (bits 22:16 of register 25 of IHB on both ends) 2) PQ backoff threshold at AP side changed from 0x7 to 0x6 (IHB register 0 of AP, bits 22:16) 3) RX Delta changed from 0x2 to 0xf (IHB register 0 on both sides, bits 7:4) 4) set AP read & write oustanding limits to 4. 5) set CP write oustanding limit to 18, and CP read oustanding to 12. Change-Id: I31869f134a368f681ac769caae880d2e45e37c21 Signed-off-by: Omri Itach <omrii@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/40930 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-08-31plat: marvell: a8k: allow to load scp_bl2 firmware that doesn't contain PM FWGrzegorz Jaszczyk
Hitherto if the SCP_BL2 path was defined, Marvell platform code (plat/marvell/a8k/common/a8k_common.mk via plat/marvell/a8k/common/mss/mss_common.mk) was defining SCP_IMAGE, which was used in power management related code(mainly in plat_pm.c) for choosing proper PM related code. Therefore there were two different situation: 1) The SCP_BL2 was not defined, then the ATF used its own PM related code 2) The SCP_BL2 was defined and ATF assumed that during SCP_BL2 stage the firmware with PM support was loaded into MSS AP CM3 and PM was managed mainly via IPC messages between ATF and MSS AP CM3 firmware. Now in some cases the firmware for MSS AP CM3 does not support PM therefore it causes some issue: during Linux boot only one CPU was brought out from reset and all secondary CPUs remained down. After this change the Marvell platform code can verify if the firmware loaded to MSS AP CM3 has PM support at runtime and does not make assumption basing on SCP_BL2 definition anymore. In other words all preprocessor condition of SCP_IMAGE was replaced by runtime condition that allows to really distinguish between situation where we are running PM firmware or not, so three different scenario are possible and handled correctly now: 1) The SCP_BL2 is not used at all then the ATF uses its own PM related code. 2) The SCP_BL2 contains firmware for MSS AP CM3 and it supports PM, then ATF manage PM mainly via IPC messages between ATF and MSS AP CM3 firmware. 3) The SCP_BL2 does not contain firmware for MSS AP CM3 or it contain firmware that does not support PM, then ATF uses its own PM related code. Change-Id: I26da4db968966cb5e61714ff192fb645a3a57875 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43573 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-by: Omri Itach <omrii@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com>
2017-08-30fix: llc: ocp, pcac: temporarily force disable of LLCOmri Itach
Force disable of LLC for A8k-OCP and A7k-PCAC boards, regardless of LLC_DISABLE compilation flag. This is due to an issue observed while running iperf with smartNIC End Poind driver/application, while LLC is enabled. As a temporary workaround, until issue is solved, we disable LLC. Change-Id: Ie8362dafcf227112a8c48e865f74bfe69c8598d5 Signed-off-by: Omri Itach <omrii@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/42127 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-08-29plat: a70x0_amc: Increase the PCIe address rangeKonstantin Porotchkin
Increase the PCIe address range for A7K AMC board to 96MB as required by CPSS Linux drivers. Change-Id: I78a762eb91a7454c9c86f1ded513b95582583768 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43448 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Hanna Hawa <hannah@marvell.com> Reviewed-by: Victor Gu <xigu@marvell.com>
2017-08-29mvebu: io_win: move GCR offset to be defined in platformHanna Hawa
As part of AP810 preparation and driver changes, move GCR offset to be defined in platform file and not in IO_WIN driver as AP810 & AP806 have different GCR offset. No functional changes introduced by this patch. Change-Id: Iadb4d7294909fa764bf26aa6b7442bb8a33a9c53 Signed-off-by: Hanna Hawa <hannah@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43469 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com>
2017-08-29fix: mvebu: ccu: remove skip window functionHanna Hawa
Skip window function as we don't use it any more, this function was added to skip the SRAM window in old u-boot revision, since we move all the window configuration to ATF, no need for it. Skip window #1, because it configured by default to internal registers. Change-Id: I9ad3fedfb3ac770652430db3c8679ebefda4fae2 Signed-off-by: Hanna Hawa <hannah@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43465 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com>
2017-08-28fix: a8k: Correct bad IRQ mapping macrosKonstantin Porotchkin
Corect wrongly defined PLAT_MARVELL_G0_IRQS and PLAT_MARVELL_G1S_IRQS macros in A8K platform common files Change-Id: Ic538f448188cbfb86703074658e7b9b0b6b7debf Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43453 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Hanna Hawa <hannah@marvell.com>
2017-08-28pm: a8k: change the GPIO toggling sequenceVictor Gu
In order to support multiple times of power off the system by PMIC, the GPIO toggling sequence for Armada80x0 board should be "1-0-1-0-1-0-1" instead of "1-0-1-0-1". Change-Id: Ia03330e7ff8e115ea7b841a8a10f7641f4cc7b65 Signed-off-by: Victor Gu <xigu@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43437 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-08-28plat: mvebu: add check of north bridge number to marvell_check_mpidr functionHanna Hawa
Part of AP810 preparation and driver changes, add check of north bridge number to marvell_check_mpidr function. For Armada-8k family and Armada-37xx family, no functional change, they have single north bridge die. Armada-8k-plus family can contain 4 north bridge dies, so need to check the value of the die number. Change-Id: I1f3b9fa46e6b099f83024e411828f586bb8927c2 Signed-off-by: Hanna Hawa <hannah@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43400 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Hua Jing <jinghua@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-08-28plat: mvebu: add die parameter for psci_arch_init functionHanna Hawa
As part of AP810 preparation and driver changes, add die parameter for psci_arch_init function. For Armada-8k family and Armada-37xx family, no functional change, they have single north bridge die (die #0), add die 0 for all psci_arch_init functions. Armada-8k-plus family can contain 4 north bridge die, so need to call psci_arch_init with different die number. No functional changes introduced by this patch. Change-Id: I5e334ce5bb75103236c322b389a0bc5e216fbe2a Signed-off-by: Hanna Hawa <hannah@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43399 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Hua Jing <jinghua@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-08-27mvebu: pm: a8k: move armada-8k functions to be staticHanna Hawa
Change-Id: Ib5a70cf178f055a1ba506ba77592d452e9730321 Signed-off-by: Hanna Hawa <hannah@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43394 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
generated by cgit (git 2.34.1) at 2024-05-02 14:46:46 +0000