summaryrefslogtreecommitdiff
AgeCommit message (Collapse)Author
2018-09-03Bump atf-v1.5 to release armada-18.09.4atf-v1.5-armada-18.09Igal Liberman
Change-Id: I4a3abeec05830da6cc34858729deb32b540eb716 Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/59575 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-09-03mvebu: cp110: fix GEN3 SATA linkIgal Liberman
Currently when we connect SATA GEN3 disk, GEN2 link is established. This patch updates 2 comphy parameters, g3_emph and allign_90, fixing this issue. Change-Id: I4e39d180cb8b401490643ddab0fc5d6442c1c220 Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/59563 Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-09-03Bump atf-v1.5 to release armada-18.09.3Igal Liberman
Change-Id: I9e483df9c7d6c0c0d0d8281ed678e7ee71000efa Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/59403 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2018-09-03doc: marvell: Add a notice about CVE-2018-3639 WA enablementKonstantin Porotchkin
Starting Marvell TF-A release 18.09 the CVE-2018-3639 workaround is disabled by default. This patch adds documentation notice about way to enables this WA. Change-Id: I4f8c7c203dd5c0d16f609bab97cc8dc70866ae22 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/59281 Reviewed-by: Nadav Haklai <nadavh@marvell.com> Tested-by: Nadav Haklai <nadavh@marvell.com>
2018-09-03Bump atf-v1.5 to release armada-18.09.2Nadav Haklai
Change-Id: I87cdc96d21211387366e8bdc5040a75734bded09 Signed-off-by: Nadav Haklai <nadavh@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/59184
2018-09-03fix: tools: Fix doimage syntax breaking secure mode buildKonstantin Porotchkin
Missing ")" in fprintf causing build break in secure boot mode. Change-Id: Ice555571683b68bb0d81479e9fc8abc4296809ac Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/59143 Reviewed-by: Nadav Haklai <nadavh@marvell.com>
2018-09-03fix: marvell: Check the required libraries before building doimageKonstantin Porotchkin
Some customers are missing host libraries required for doimage builds. This patch requests for the library installation check for every doimage build and suggest the required installation steps in case of missing headers. Change-Id: Icde18c3d4d6045f65e50d2dc9e6514971f40033e Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/59049 Reviewed-by: Igal Liberman <igall@marvell.com> (cherry picked from commit 0909d554b3d914f918e5c0ead9750e6e0767ab6e) Reviewed-on: http://vgitil04.il.marvell.com:8080/59135 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Nadav Haklai <nadavh@marvell.com>
2018-09-03Bump atf-v1.5 to release armada-18.09.1Nadav Haklai
Change-Id: I70bb4c81c6d3128f8a5087ab210e8e211d2c9556 Signed-off-by: Nadav Haklai <nadavh@marvell.com>
2018-09-03mvebu: cp110: fix XFI link down problemIgal Liberman
This patch fixes an issue on Armada7040/8040-DB, when a XFI port is enabled, the link is not established. This is caused due to changes in commit: c14a9cf9535f ('commit mvebu: cp110: introduce porting layer for sfi'). This patch has the following updates: - Fix incorrect static values in SFI configuration: g1_rx_selmuff, g1_rx_selmufi, g1_rx_selmupf, g1_rx_selmupi - Update HPIPE_G1_SETTINGS_3_REG configuration. - Remove the following settings: HPIPE_RX_CLK_ALIGN90_AND_TX_IDLE_CALIB_CTRL_REG HPIPE_DFE_REG0 HPIPE_G1_SETTINGS_4_REG In addition, cosmetic change in xfi_static_values_tab struct - add 0x prefix for the values, to avoid inconsistency. Change-Id: I97cb5f63504b6d16ccbc0b73c5ea037a83e8ba49 Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/58930 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2018-09-03xdb: script: update 8k XDB scriptChristine Gharzuzi
- This patch updates the RET address of ble_main function - This is a fixed value, since no code is added to the ble_main function anymore (instead ble_main calls for another function that can edited.) Change-Id: I97ed8562dd9d33e5067c22a47cc98b475d3c61d6 Signed-off-by: Christine Gharzuzi <chrisg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/58770 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-09-03plat: svc: ap807: add SVC configuration for AP807Christine Gharzuzi
- add svc configuration according to values burnt to the chip efuse Change-Id: Icf5d7cc41bc09ac2244d0a126106e681afebb064 Signed-off-by: Christine Gharzuzi <chrisg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/58673 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-09-03Bump atf-v1.5 to release devel-18.09.0Konstantin Porotchkin
Change-Id: I4c729b71e845a4392bbbf8df6c24bf1dfd603107 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/58576 Reviewed-by: Igal Liberman <igall@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2018-09-03docs: marvell: update the porting guide about comphy porting layerGrzegorz Jaszczyk
Change-Id: I41862b1176c27ab815863bc1c3393d29d2f11b7f Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/58400 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-09-03plat: a8k: enable PMU overflow interrupt handlerMarcin Wojtas
This patch enables handling PMU overflow IRQ by GIC SPI's directly in EL3. Also implement additional SMC routine, which can disable the solution on demand in runtime. Change-Id: Ie76aa62ccc4fd7cabfec9e3d5ed9970ada1c1b2a Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/58304 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: Kostya Porotchkin <kostap@marvell.com>
2018-09-03marvell: drivers: correct RTC init sequenceMarcin Wojtas
It turned out that resetting the RTC time register is not necessary during initial configuration. Safely remove it from the sequence. Change-Id: Id2b9c7db44a8c8dbe88a7f8a21695b72a7fd78ee Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/58534 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Nadav Haklai <nadavh@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-09-03gicv2: enable configuring IRQ trigger typeMarcin Wojtas
This patch introduces new helper routines that allow configuring the individual IRQs to be edge-triggered via GICD_ICFGR registers. This is helpful to modify the default configuration of the GIC SPI's, which are all set during initialization to be level-sensitive. Change-Id: I23deb4a0381691a686a3cda52405aa1dfd5e56f2 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/58303 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-09-03fix: a3900: pm: fix number of CPU power switches.Christine Gharzuzi
- Number of open power switches for CPUs should be three and now two. - This patch updates the value of open power switches from 0xfd (two power-switches) to 0xfc (three power-switches). Change-Id: I2783ab7f04bbbb6da78eeedcabe4636f9a774512 Signed-off-by: Christine Gharzuzi <chrisg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/58399 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-09-03marvell: pm: do not panic by default in cpu_standbyMarcin Wojtas
Current default behavior of cpu_standby callback is problematic during the SBSA test, which is unable to run due to EL3 panic. Make it dependent on the PM firmware running. Change-Id: I7a53de8c880bd23b157dd65ce14bb48b5a5c76c8 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/58302 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-09-03fix: a8k-p: Change the way Makefile tests for PALLADIUM valueKonstantin Porotchkin
Change the A8K+ common makefile in the way that PALLADIUM variable is always checked for value 1 and not 0, since PALLADIUM=0 is usually not explicitly set in the compilation string. Instead, the default value of 0 is assigned to PALLADIUM variable by lately included make files in order to handle the preprocessor directives in source files. Change-Id: I9793e5808c56960a17cab0bab6ac4204fd3cbc27 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/58446 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com>
2018-09-03fix: comphy: Exclude COMPHY support in PD buildsKonstantin Porotchkin
Remove COMPHY support from PD builds on A8K+ platforms Change-Id: I27d4561b602ac4746330ea95d7f88dfeb04b2ae1 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/58378 Reviewed-by: Igal Liberman <igall@marvell.com> Reviewed-by: Hanna Hawa <hannah@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2018-09-03plat: marvell: align the sources with mainline TF-AKonstantin Porotchkin
Following the acception of Marvell platform support in the mainline TF-A code, some changes triggered by the TF-A team review should be ported back. This patch introduces changes (mostly cosmetic) that sync between the mainline and LSP code bases. - Limit line length to 80 characters for passing through Linux checkpatch - Make all comment blocks comply the Linux kernel coduing style - Arrange all includes in alphabetical order - Rename plat_config.h to armada_common.h (a8k_common in the mainline, but we should take into account next platform support as well) - Rename plat_private.h to marvell_plat_priv.h - Rename plat_def.h to mvebu_def.h Change-Id: Idd542c8a7d4ff8d8fb67c3601410308be5aed8e5 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/58282 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com>
2018-09-03scripts: add more ignores to patch checking configurationKonstantin Porotchkin
- move back to the default line length of 80 characters for making future mainline code submissions easier - ignore warning about non-constant structures- seems to be too strict and usually ignored anyway - ignore warning abour SPDX header format since it's differs from the kernel headers. Change-Id: I3b81391470d27e6bed7bc6ff6be9fba5fc5d37e8 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/58281 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com>
2018-09-03mvebu: cp110: extend porting layer about sata parametersGrzegorz Jaszczyk
Change-Id: I65ca7109c258b02de286b728e0cec2cc4c651126 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/58024 Reviewed-by: Igal Liberman <igall@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: Kostya Porotchkin <kostap@marvell.com>
2018-09-03mvebu: cp110: fix spelling in register definitionGrzegorz Jaszczyk
Use PF instead of PP post-fix, since it is referring to "Phase Final" (only G3 related register had correct spelling for relevant bit). Change-Id: Ia5a9c9c78b74b15f7f8adde2c3ef4784c513da2c Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/58023 Reviewed-by: Igal Liberman <igall@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2018-09-03mvebu: cp110: do not perform comphy power on/off after rx_training was runGrzegorz Jaszczyk
If the rx_training was triggered (e.g. in U-Boot) do not perform comphy power on/off on the serdes for which the rx training was triggered. Thanks to this change the rx_training results will not be reset after moving from U-Boot to Linux. Change-Id: I6748e570b2f386cb5f65d7dc8cfff69424a9db5e Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/58022 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-09-03mvebu: cp110: introduce porting layer for sfiGrzegorz Jaszczyk
Some of the xfi parameters depends on the hw connection between the SoC and the PHY (~SFP cage) which can vary on different boards e.g. due to different wire length. Define the "porting layer" with some defaults parameters. It ease updating static values which needs to be updated due to board differences, which are now grouped in one place. Example porting layer for a8k-db is under: plat/marvell/a8k/a80x0/board/phy-porting-layer.h If for some boards parameters are not defined (missing phy-porting-layer.h), the default values are used (drivers/marvell/comphy/phy-default-porting-layer.h) and the user is warn: "Using default comphy parameters - it may be need to suit them for your board". Change-Id: I1ab2ad8d282e642afa9c3da128fa48aee7bff48e Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/57530 Reviewed-by: Igal Liberman <igall@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: Kostya Porotchkin <kostap@marvell.com>
2018-09-03mvebu: cp110: introduce new version of rx_training procedureGrzegorz Jaszczyk
The old version of rx_training was not sufficient for all setups. Moreover some parameters was chosen manually (ffe) and then partial training was run in loop with different values and the best result was determined. With new version some steps are added but the whole training is performed by hardware. Change-Id: Iff5cd08094f969ebbbdb59176e895406f27b0e48 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/57529 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2018-09-03mvebu: cp110: align all comphy_index arguments typeGrzegorz Jaszczyk
The biggest comphy index can be equal to 6 so there is no need to use uint64_t for storing it. Change-Id: I14c2b68e51678a560815963c72aed0c37068f926 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/58021 Reviewed-by: Igal Liberman <igall@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-09-03plat: marvell: a70x0: reconfigure CP0 PCIE2 windowsMarcin Wojtas
In order to allow the use of PCIe cards such as graphics cards, whose demands for BAR space are typically much higher than those of network or SATA/USB cards, reconfigure the I/O windows so we can declare two MMIO PCI regions: a 512 MB MMIO32 one at 0xc000_0000 and a 4 GB MMIO64 one at 0x8_0000_0000. In addition, this will leave ample room for an ECAM config space at 0xe000_0000 (up to the ECAM maximum of 256 MB) For compatibility with older kernels or firmware, leave the original 16 MB window in place as well. Change-Id: I80b00691ae8d0a3f3f7285b8e0bfc21c0a095e94 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/58070 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2018-09-03plat: marvell: a80x0: reconfigure CP0 PCIE0 windowsMarcin Wojtas
In order to allow the use of PCIe cards such as graphics cards, whose demands for BAR space are typically much higher than those of network or SATA/USB cards, reconfigure the I/O windows so we can declare two MMIO PCI regions: a 512 MB MMIO32 one at 0xc000_0000 and a 4 GB MMIO64 one at 0x8_0000_0000. In addition, this will leave ample room for an ECAM config space at 0xe000_0000 (up to the ECAM maximum of 256 MB) For compatibility with older kernels or firmware, leave the original 16 MB window in place as well. Change-Id: Ia8177194e542078772f90941eced81b231c16887 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/58071 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-07-18runtime_exceptions: add default lower el system error handlerHanna Hawa
When ATF is built with HANDLE_EA_EL3_FIRST (more in doc), the external aborts and serror interrupts will be trapped in EL3. Add simple weak serror handler for lower level data aborts. Change-Id: I568085d8ddbbafb01648bb71856e3650039264e2 Signed-off-by: Hanna Hawa <hannah@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/57293 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2018-07-10marvell: pm: Cleanup platform PM codeKonstantin Porotchkin
- Stop using named registers for saving GPIO address and data between functions calls. The registers can be re-sued by compiler after function return. Instead switch to local register_t variables and use them in inline assemble PMIC power off procedure. - Replace data barriers implemented by inline assembly blocks with appropriate macros. - Format comments according to Linux coding standards. - Convert long single line expressions to multiline ones. Change-Id: I7c4ee3976543b30e35ff55ff6dd11ca96ed4d8b9 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/57707
2018-07-05scripts: update checkpatch.pl to latest Kernel versionKonstantin Porotchkin
Change-Id: I2d550cde8b16645325207b415f3309d919ffe809 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/57712
2018-07-02fix: driver: marvell: fix print format in mc_trustzone driverKonstantin Porotchkin
Fix the format according to latest data type updates. Change-Id: Ic9f5f50c25fa86af6143d8e4757eb6a396e2c8dd Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/57587 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-by: Igal Liberman <igall@marvell.com>
2018-07-02fix: plat: marvell: Align header names with mainline codeKonstantin Porotchkin
Rename arm_def.h ->> marvell.def.h Rename arm_macros.S ->> marvell_macros.S Fix the source files accordingly. Change-Id: Ic728111ed05fda622303ed7178140c22f8c4f125 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/57586 Reviewed-by: Igal Liberman <igall@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2018-06-28Bump atf-v1.5 to release devel-18.08.0Konstantin Porotchkin
Change-Id: If15013112726f25ed9e12cc3e54be655bd6100c1 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/57505 Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2018-06-28a8k: use the memory controller feature to protect the RT service regionGrzegorz Jaszczyk
Define the RT service space as secure with use of memory controller trustzone feature. Thanks to this protection, any NS-Bootloader nor NS-OS, won't be able to access RT services (e.g. accidentally overwrite it, which will at best result in RT services unavailability). Change-Id: Ie5b6cbe9a1b77879d6d8f8eac5d4e41e468496ce Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/56762 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-06-28drivers: marvell: mc_trustzone: add driver for mc trustzoneGrzegorz Jaszczyk
Add simple driver which allows to configure the memory controller trust zones. It is responsible for opening mc trustzone window, with appropriate base address, size and attributes. Example of usage in upcoming commits. Change-Id: I8bea17754d31451b305040ee7de331fb8db0c63f Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/56760 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-06-28Fix pointer type mismatch of handlersMasahiro Yamada
Commit 4c0d03907652 ("Rework type usage in Trusted Firmware") changed the type usage in struct declarations, but did not touch the definition side. Fix the type mismatch. Change-Id: Id685b5697b49bf8d48d56bbd71e0babdc6b94413 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/57496 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-06-28mvebu: llc: allow llc enablement in runtime using smccc callIgal Liberman
This patch allows to enable LLC from Linux Kernel using smccc call. In addition, perform other required operation for correct LLC functionally: - Set POC to DDR. - Enable L2 UniqueClean evictions. Change-Id: Ia293dc1d1615d9872d153204bb8ffd55bc3efa11 Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/56663 Tested-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-06-28avs: ap807: Modify the default AVS value for AP807Konstantin Porotchkin
Set the default AVS value for AP807 to 820mV. Previously the AVS settings om AP807 was not altered. Change-Id: Ie2f1eef7f8bc7f209daaf5544fdbba82bb244103 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/57423 Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2018-06-28plat: marvell: rearrange platform make filesKonstantin Porotchkin
Move all board specific definition from common platform file to the appropriate platform board make files This patch also fixes DRAM initialization ussue with A3900-A1 board that happen due to wrongly linked ap806 driver instead of the expected ap807. Change-Id: If28ce48969541ae642557f44adfba9ce5b852152 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/57421 Reviewed-by: Ofir Fedida <ofedida@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2018-06-28ble: Update the paltform includes listKonstantin Porotchkin
Extend the platform includes list for easier headers usage in mv_ddr code Change-Id: I7e6b202c211e4d56718d5b0642dff1368a020cc2 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/57420 Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2018-06-27board: Add support for Armada80x0 DB with 32bit DDRjinghua
Add support for Marvell Armada80x0 DB with 32bit DDR bus width. There is no difference besides the DDR bus width, between normal A80x0 DB and the new A80x0 DB. Change-Id: Ib1fd4041e2e05b333c285bde95b1b5167196c715 Signed-off-by: jinghua <jinghua@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/57266 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: Kostya Porotchkin <kostap@marvell.com>
2018-06-26mvebu: add unified api to get number of APsIgal Liberman
This is usefull to make drivers that server different types of APs: 810/806/807 more generic. Change-Id: I7a24b8a80e2b3eed0b77a95b5a2f40b7cad4180c Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/57166 Reviewed-by: Hanna Hawa <hannah@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-06-24runtime_exceptions: add default lower el data abort handlerGrzegorz Jaszczyk
When ATF is built with HANDLE_EA_EL3_FIRST (more in doc), the external aborts and serror interrupts will be trapped in EL3. Add simple weak data abort handler for lower level data aborts. Change-Id: I4342df4e1c42626ba4f7ae0d976244f7af0e5fa9 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/56757 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-by: Hanna Hawa <hannah@marvell.com>
2018-06-24fix: marvell: Adjust data types to the new definitionKonstantin Porotchkin
Apply changes to data formats to be compatible with the mainline patch: "types: use int-ll64 for both aarch32 and aarch64" Change-Id: I1c4c77d5f1a1a513fac03ca9a7c565b13c1f50aa Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/57119
2018-06-24types: use int-ll64 for both aarch32 and aarch64Masahiro Yamada
Since commit 031dbb122472 ("AArch32: Add essential Arch helpers"), it is difficult to use consistent format strings for printf() family between aarch32 and aarch64. For example, uint64_t is defined as 'unsigned long long' for aarch32 and as 'unsigned long' for aarch64. Likewise, uintptr_t is defined as 'unsigned int' for aarch32, and as 'unsigned long' for aarch64. A problem typically arises when you use printf() in common code. One solution could be, to cast the arguments to a type long enough for both architectures. For example, if 'val' is uint64_t type, like this: printf("val = %llx\n", (unsigned long long)val); Or, somebody may suggest to use a macro provided by <inttypes.h>, like this: printf("val = %" PRIx64 "\n", val); But, both would make the code ugly. The solution adopted in Linux kernel is to use the same typedefs for all architectures. The fixed integer types in the kernel-space have been unified into int-ll64, like follows: typedef signed char int8_t; typedef unsigned char uint8_t; typedef signed short int16_t; typedef unsigned short uint16_t; typedef signed int int32_t; typedef unsigned int uint32_t; typedef signed long long int64_t; typedef unsigned long long uint64_t; [ Linux commit: 0c79a8e29b5fcbcbfd611daf9d500cfad8370fcf ] This gets along with the codebase shared between 32 bit and 64 bit, with the data model called ILP32, LP64, respectively. The width for primitive types is defined as follows: ILP32 LP64 int 32 32 long 32 64 long long 64 64 pointer 32 64 'long long' is 64 bit for both, so it is used for defining uint64_t. 'long' has the same width as pointer, so for uintptr_t. We still need an ifdef conditional for (s)size_t. All 64 bit architectures use "unsigned long" size_t, and most 32 bit architectures use "unsigned int" size_t. H8/300, S/390 are known as exceptions; they use "unsigned long" size_t despite their architecture is 32 bit. One idea for simplification might be to define size_t as 'unsigned long' across architectures, then forbid the use of "%z" string format. However, this would cause a distortion between size_t and sizeof() operator. We have unknowledge about the native type of sizeof(), so we need a guess of it anyway. I want the following formula to always return 1: __builtin_types_compatible_p(size_t, typeof(sizeof(int))) Fortunately, ARM is probably a majority case. As far as I know, all 32 bit ARM compilers use "unsigned int" size_t. Change-Id: I20af6905d77bf8fad92808066654a4e6c147c2be Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/57118 Reviewed-by: Omri Itach <omrii@marvell.com> Tested-by: Kostya Porotchkin <kostap@marvell.com>
2018-06-24fix: thermal: Fix the license and platform file nameKonstantin Porotchkin
Set the thermal driver license to BSD 3 instead of GPL 2. Rename marvell_thermal.c to plat_thermal.c to be in sync the rest of files in A8K platform folder. Change-Id: Ie9d8d80d529a7f200198a21f9c66f65be94d78fc Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/57111 Reviewed-by: Omri Itach <omrii@marvell.com>
2018-06-24fix: plat: marvell: Rename the coherent memory regionKonstantin Porotchkin
Fix the wronly named end of coherent memory region: BL_COHERENT_RAM_LIMIT ->> BL_COHERENT_RAM_END Change-Id: Ia1b27153a8b82332d204f971a92a888e3438780a Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/57112 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Omri Itach <omrii@marvell.com>
generated by cgit (git 2.34.1) at 2024-05-05 04:07:00 +0000