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2020-07-06Add Macchiatobin tweaked comphy settingsatf-v1.5-armada-18.12-rmkRussell King
Signed-off-by: Russell King <rmk@armlinux.org.uk>
2019-03-15marvell: comphy: fix build errorRussell King
Signed-off-by: Russell King <rmk@armlinux.org.uk>
2018-12-24scripts: ci: espressobin: add support for emmc boot deviceatf-v1.5-armada-18.12Konstantin Porotchkin
Switching the boot device to eMMC on EspressoBIN platform requires changing 2 parameters when building th flash image: BOOTDEV - from the default SPINOR to EMMCNORM PARTNUM - from the default 0 to 1 This patch adds support for "boot from emmc" builds for Espressobin platform and implements the above changes in build commands. Change-Id: I34414656fdae92ff3cd36fbc851f94b73d59e38c Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/62064
2018-12-19Bump atf-v1.5 to release devel-18.12.2Konstantin Porotchkin
Change-Id: I5759ad43bc342bf11e5134df5acde4c095e9a869 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/61508 Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2018-12-04scripts: ci: add macchiatobin single shot builds to CIBen Peled
Change-Id: I878fad6d6299265425edb57aa41084c3f4d5fbb4 Signed-off-by: Ben Peled <bpeled@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/61506 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-12-04scripts: ci: add a3700 db-C DDR4 rev 3.x builds to CIStefan Chulski
Add builds for a3700 db-C rev 3.x DDR4 Change-Id: I3b46056b4f92122c3a394eb2466a43d8480b2be6 Signed-off-by: Stefan Chulski <stefanc@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/61497 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-11-27Bump atf-v1.5 to release devel-18.12.01Stefan Chulski
Change-Id: I240596bd8a1501a30690bc9d1944c55e23544896 Signed-off-by: Stefan Chulski <stefanc@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/61377
2018-11-26scripts: ci: remove u-boot-2017 builds from supported listKonstantin Porotchkin
Change-Id: I49a1c8c0e0d29d889eca48469c5cc2d69bf443d1 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/61301 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Lior Levin <levin@marvell.com>
2018-11-26scripts: ci: add EspressoBIN builds to CIKonstantin Porotchkin
Add builds for EspressoBIN v7 (DDR4) 1GB/2GB Change-Id: I34f9b5f19262ec173264a1a8c1c701b768b16d92 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/61298 Reviewed-by: Lior Levin <levin@marvell.com>
2018-11-26doc: marvell: Update build manual with new memory layoutsKonstantin Porotchkin
Add description for memory layouts used by EspressoBin v7 (DDR4) Change-Id: I199d8b52580b26e560f14b503a6e99d32de4f284 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/61278 Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2018-11-22Bump atf-v1.5 to release devel-18.12.0Igal Liberman
Change-Id: I98fa8084ec10a9b02c02c3bebff008b5e7d0962d Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/61150 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-11-22svc: Update the EEPROM AVS values processingKonstantin Porotchkin
Update the SVC procedure for EEPROM access. Add support for AP807 AVS values (10 bits wide). Change-Id: Iaf1608bde9d46d6a24a78f5e96617bb27d25d80e Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/60716 Reviewed-by: Igal Liberman <igall@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2018-11-21doc: mvebu: update build instructions with ci scripts usageIgal Liberman
Change-Id: I8a5b52de84e2de7f4021b5ffea6b529677ebc415 Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/61146 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2018-11-21mvebu: cp110: avoid pcie power on/off sequence when called from LinuxIgal Liberman
In Armada 8K DB boards, PCIe initialization can be executed only once because PCIe reset performed during chip power on and it cannot be executed via GPIO later. This means that power on can be executed only once, when it's called from the bootloader. Power on: Read bit 21 of the mode, it marks if the caller is the bootloader or the Linux Kernel. Power off: Check if the comphy was already configured to PCIe, if yes, check if the caller is bootloader, if both conditions are true (PCIe mode and called by Linux) - skip the power-off. In addition, fix incorrect documentation describing mode fields - PCIe width is 3 bits, not 2. NOTE: with this patch, please use LK4.14.76 (LK4.4.120 may not work with it). Change-Id: I4b929011f97a0a1869a51ba378687e78b3eca4ff Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/60959 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-11-21ci: add missing supported buildsLior Levin
Change-Id: Ie26befeeaf6f61f42b5f630dbe0d826f3290b9e9 Signed-off-by: Lior Levin <levin@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/61138
2018-11-20plat: marvell: a3700: do not power off cpu due to errata ref #13Grzegorz Jaszczyk
Do not power off the CPU1 since there is no way to wake it up (wake-up is causing CPU0 reset as well duo to HW bug). Quote from errata Ref #13 [In power saving mode, both cores must be powered off]: "When Core 0 is on and Core 1 is in power-off state, a Core 1 wake-up resets Core 0 as well and puts Core 0 back to ROM". To overcome described HW bug instead of powering the CPU off, let it reach WFI instruction, which is invoked by generic psci_do_cpu_off function after platform handler finishes. This will put the core in low power state and give a chance to wake it up. Before this change, after running secondary kernel via kexec, only one core was up, now both cores are up. Change-Id: I87f144867550728055d9b8a2edb84a14539acab7 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/60935 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-11-20scripts: add ci compile & pack scriptsLior Levin
Change-Id: Ibc35811191d5c1a13cdeed0152807064dc07ef7f Signed-off-by: Lior Levin <levin@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/61066
2018-11-19mvebu: cp110: fix phy selector configuration for XFI1Grzegorz Jaszczyk
Extended phy selector configuration about XFI1 mode. Change-Id: I1309770bbb5fdbfb0127b6f12ee78974d1d6b19f Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/60942 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-11-11fix: plat/marvell: svc: Add i2c initilization to SVC flowKonstantin Porotchkin
Add missing MPP and i2c initilization missing in SVC EEPROM access flow. Change-Id: I0c0276b7c28a0226fd75dd46bbad5190c3bfc9f3 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/60794 Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2018-11-11ble: ap807: Switch to PLL mode and update CPU frequencyChristine Gharzuzi
- Update CPU frequency on AP807 to 2GHz for SAR 0x0. - Increase AVS to 0.88V for 2GHz clock Change-Id: Ic945b682ab2f8543e34294bfc56c3eae2c5e0c8e Signed-off-by: Christine Gharzuzi <chrisg@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/57248 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com>
2018-11-07fix: plat/marvell: a3700: Remove encryption passwordKonstantin Porotchkin
According to "openssl" manual: -K key The actual key to use: this must be represented as a string comprised only of hex digits. If only the key is specified, the IV must additionally specified using the -iv option. When both a key and a password are specified, the key given with the -K option will be used and the IV generated from the password will be taken. It does not make much sense to specify both key and password. This patch removes "-k 0" parameter from the encryption command since we are already using "-K" and "-iv" for the key and IV. Change-Id: Ia333cedaa3207e643c95d2ec7c229f50eeab96db Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/60745 Reviewed-by: Igal Liberman <igall@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Sharon Habet <sharonh@marvell.com>
2018-11-01Bump atf-v1.5 to release devel-18.11.0Igal Liberman
Change-Id: I13f3a7169c9dd360c54748a985e607aa6c62657d Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/60634 Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2018-10-23fix: ble: svc: Fix the SVC code for AP807Konstantin Porotchkin
Stop bypassing SVC procedure for AP807. Fix makefile for proper handling the SVC_TEST parameter. Add a missing call to i2c_init() before starting to acess the AVS corection values stored in i2c EEPROM. Change-Id: I2743b78500ecc310f2839ac218b636ec0294fd34 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/60470 Reviewed-by: Igal Liberman <igall@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2018-10-22plat/marvell: comphy: Add support for SFI on Lane 4Konstantin Porotchkin
Add static configuration for SFI+ 10Gbps interface on SERDES Lane 4. This is just a copy of Lane 2 static values, not optimized. Board-to-board iperf test shows up to 6Gbps transfer speed. Change-Id: I024d2ac132f7fa6c342a64367f3dca2123a27e97 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/60416 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com>
2018-10-18mvebu: cp110: fix rxaui configurationGrzegorz Jaszczyk
Add missing break statement after rxaui power on to prevent invoking usb power on by mistake. Change-Id: I2c03ee524aed00338aac8bb5d82b35bb58b2354a Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/60300 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-10-04fix: a8k: Remove boot warning about BL32 image absenceKonstantin Porotchkin
The TF-A shows a warning when tries to load BL32 (type 4) image: WARNING: Failed to obtain reference to image id=4 (-2) WARNING: Failed to load BL32 (-2) The BL32 image is only tried when the BL32_BASE is defined in platform headers. This patch allows BL32_BASE define only when image is built with BL32=<binary> option, as in case of OP-TEE OS inclusion. Change-Id: I4a6e4d1c258ba29a572a56a4e02f612070576bc5 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/60038 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com>
2018-09-17plat: marvell: a3700: get rid of deprecated sys info and use ddr info driverGrzegorz Jaszczyk
The sys info was used to pass copy dram information to u-boot. This was deprecated method and was removed, since obtaining ddr size is now handled via rt services. Remove all sys info related code and use mvebu_get_dram_size in place where marvell_get_dram_cs_base_size was used. Change-Id: I571043332cd51bf84ec06ad5ef31906cb957c439 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/59827 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-09-17plat: marvell: a3700: allow to read ddr size from mem controllerGrzegorz Jaszczyk
Register new smc fid as runtime service, which will allow to read ddr size from memory controller. It is required since the memory controller registers will be marked as secure, therefore bootloaders will not have direct access to them. Change-Id: Ia05cd51526a4a9aa0969e900dd0c7f3322ae70c6 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/59826 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: Kostya Porotchkin <kostap@marvell.com>
2018-09-16plat: marvell: a3700: add definition for marvell common directoryGrzegorz Jaszczyk
No functional change - only cosmetic. Change-Id: I35a664f46b695207603ec5302bccaff4bafbfd7f Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/59825 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2018-09-16mvebu: a3700: add extra USB3H mode since some existing consumers uses itGrzegorz Jaszczyk
Both USB3H and USB are equivalent from 3700-comphy perspective and some consumers (various version on Linux was using them interchangeably). To not break compatibility with various consumers version, the equivalent mode is added. Change-Id: I52526b4e64ddf57281fc956a375d199a1c42e835 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/59824 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-09-06marvell: a3700: register platform specific SiPGrzegorz Jaszczyk
Currently all registered SiP services are used for comphy handling but they will be extended in the future. Change-Id: I4229e27b8c4e3de5aa01e9dd039feee909265025 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/59676 Reviewed-by: Igal Liberman <igall@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: Kostya Porotchkin <kostap@marvell.com>
2018-09-06mvebu: a3700: add COMPHY driverGrzegorz Jaszczyk
Add COMPHY driver which will be exposed via SiP service. Change-Id: I9d774eb6e7dc7d0a30e9bb6f30c56b4b3a8cda79 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/59675 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-09-03marvell: comphy: extract some functionality to common fileGrzegorz Jaszczyk
Some of those function will be used in upcoming commit which adds support for new comphy driver used in armada-3700 SoC. Change-Id: I6c340deec6460847ad0d3a71514154879fa4cd01 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/59674 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2018-09-03lib: mmio: add 16 bit clear-set-bits accessorGrzegorz Jaszczyk
Change-Id: Ia366ee327c024db517e78c4cdcdbb633a1131699 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/59673 Reviewed-by: Igal Liberman <igall@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2018-09-03mvebu: cp110: remove rx training done check from sata initGrzegorz Jaszczyk
The rx training is related only to SFI/XFI mode, this check was added in sata power on by mistake. Change-Id: I4a19def2a993d30e3ba39b807b0ee5d2344f0469 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/59672 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-09-03a8k: pm: extend MSS_TRIGGER_TIMEOUTIgal Liberman
Very rarely, during cpuidle operations the following error is seen: "PM MSG Trigger Timeout". This is caused by slow handling of message interrutps in the PM FW running on CM3 (under heavy PM operation load). This is not a real issue, so we extend the timeout to avoid the error prints. Change-Id: I92fd6f2ff1ddf208b216c123880ded28a00b6e0e Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/59670 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2018-08-30mvebu: cp110: fix GEN3 SATA linkIgal Liberman
Currently when we connect SATA GEN3 disk, GEN2 link is established. This patch updates 2 comphy parameters, g3_emph and allign_90, fixing this issue. Change-Id: I4e39d180cb8b401490643ddab0fc5d6442c1c220 Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/59563 Reviewed-by: Grzegorz Jaszczyk <jaz@semihalf.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> (cherry picked from commit 800dfa534a578150c903501f44b56009c74b7e49) Reviewed-on: http://vgitil04.il.marvell.com:8080/59594
2018-08-26atf: apn807: add ddr validation eye supportmotib
Change-Id: I3926d086c4650b026d1d01d08fd78ebe7401c058 Signed-off-by: motib <motib@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/59417 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-08-22doc: marvell: Add a notice about CVE-2018-3639 WA enablementKonstantin Porotchkin
Starting Marvell TF-A release 18.09 the CVE-2018-3639 workaround is disabled by default. This patch adds documentation notice about way to enables this WA. Change-Id: I4f8c7c203dd5c0d16f609bab97cc8dc70866ae22 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/59227 Reviewed-by: Igal Liberman <igall@marvell.com> Reviewed-by: Nadav Haklai <nadavh@marvell.com>
2018-08-21mvebu: cp110: restore some sfi/xfi sequencesGrzegorz Jaszczyk
This commit partially reverts the "mvebu: cp110: fix XFI link down problem" patch. The static values introduced by mentioned commit are preserved but other registers accesses used during SFI/SFI configuration are restored. This partially reverts commit 3bfdf10d8b077dc1eb49d872fbf21bddbb7f7c28. Change-Id: I40320d6db7aab14012449c3154a0bcd26f873507 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/59264 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-08-16fix: tools: Fix doimage syntax breaking secure mode buildKonstantin Porotchkin
Missing ")" in fprintf causing build break in secure boot mode. Change-Id: Ice555571683b68bb0d81479e9fc8abc4296809ac Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/59142 Reviewed-by: Igal Liberman <igall@marvell.com>
2018-08-15fix: marvell: Check the required libraries before building doimageKonstantin Porotchkin
Some customers are missing host libraries required for doimage builds. This patch requests for the library installation check for every doimage build and suggest the required installation steps in case of missing headers. Change-Id: Icde18c3d4d6045f65e50d2dc9e6514971f40033e Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/59049 Reviewed-by: Igal Liberman <igall@marvell.com>
2018-08-15ble: Add SLC test prcedures for verificationKonstantin Porotchkin
Add procedures for handling AVS correction based on i2c EEPROM values Change-Id: Id4f52958490c24e7bbe9e1174dacdee2a8ef0127 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/58589 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com>
2018-08-09mvebu: cp110: fix XFI link down problemIgal Liberman
This patch fixes an issue on Armada7040/8040-DB, when a XFI port is enabled, the link is not established. This is caused due to changes in commit: c14a9cf9535f ('commit mvebu: cp110: introduce porting layer for sfi'). This patch has the following updates: - Fix incorrect static values in SFI configuration: g1_rx_selmuff, g1_rx_selmufi, g1_rx_selmupf, g1_rx_selmupi - Update HPIPE_G1_SETTINGS_3_REG configuration. - Remove the following settings: HPIPE_RX_CLK_ALIGN90_AND_TX_IDLE_CALIB_CTRL_REG HPIPE_DFE_REG0 HPIPE_G1_SETTINGS_4_REG In addition, cosmetic change in xfi_static_values_tab struct - add 0x prefix for the values, to avoid inconsistency. Change-Id: I97cb5f63504b6d16ccbc0b73c5ea037a83e8ba49 Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/58930 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2018-08-08xdb: script: update 8k XDB scriptChristine Gharzuzi
- This patch updates the RET address of ble_main function - This is a fixed value, since no code is added to the ble_main function anymore (instead ble_main calls for another function that can edited.) Change-Id: I97ed8562dd9d33e5067c22a47cc98b475d3c61d6 Signed-off-by: Christine Gharzuzi <chrisg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/58770 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-08-08plat: svc: ap807: add SVC configuration for AP807Christine Gharzuzi
- add svc configuration according to values burnt to the chip efuse Change-Id: Icf5d7cc41bc09ac2244d0a126106e681afebb064 Signed-off-by: Christine Gharzuzi <chrisg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/58673 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-07-31Bump atf-v1.5 to release devel-18.09.0Konstantin Porotchkin
Change-Id: I4c729b71e845a4392bbbf8df6c24bf1dfd603107 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/58576 Reviewed-by: Igal Liberman <igall@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2018-07-31docs: marvell: update the porting guide about comphy porting layerGrzegorz Jaszczyk
Change-Id: I41862b1176c27ab815863bc1c3393d29d2f11b7f Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/58400 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-07-31plat: a8k: enable PMU overflow interrupt handlerMarcin Wojtas
This patch enables handling PMU overflow IRQ by GIC SPI's directly in EL3. Also implement additional SMC routine, which can disable the solution on demand in runtime. Change-Id: Ie76aa62ccc4fd7cabfec9e3d5ed9970ada1c1b2a Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/58304 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: Kostya Porotchkin <kostap@marvell.com>
2018-07-30marvell: drivers: correct RTC init sequenceMarcin Wojtas
It turned out that resetting the RTC time register is not necessary during initial configuration. Safely remove it from the sequence. Change-Id: Id2b9c7db44a8c8dbe88a7f8a21695b72a7fd78ee Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/58534 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Nadav Haklai <nadavh@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
generated by cgit (git 2.34.1) at 2024-05-03 00:20:22 +0000