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2017-05-10fix: doc: mvebu: correct DDR topology option number for DDR4 2CSzachary
- There was a wrong DDR Topology option number description issue for DDR4 2CS. - The patch changes its option number from 4 to 3 for DDR4 2CS. Change-Id: If37b885b231f57215ea1b5bc51faa5b0e3d234eb Signed-off-by: zachary <zhangzg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39136 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Wilson Ding <dingwei@marvell.com> Reviewed-by: Gina Tadmore <gina@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com>
2017-05-03plat: marvell: a8k: Rename A80x0 customer to McbinKonstantin Porotchkin
Rename Macciatobin platform from a80x0_cust to a80x0_mcbin Change-Id: I715be80891f7c2d5d68a84f22a0568eb94b26c18 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38411 Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2017-05-03doc: a3700: update build file for adding ddr4 2cs 4GB supportzachary
- This patch adds build option DDR_TOPOLOGY number to support DDR4 2cs 4GB build. - Example: make DEBUG=1 USE_COHERENT_MEM=0 DDR_TOPOLOGY=3 PLAT=a3700 all fip Change-Id: I966dc6630fda5ebab906ba669ef93f4614bd2a36 Signed-off-by: zachary <zhangzg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38864 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Gina Tadmore <gina@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-05-03doc: a3700: update build.txt for new clock preset 1200/750Ken Ma
Change-Id: I0143ffbeae1d48e2700b35107588b4d6de893485 Signed-off-by: Ken Ma <make@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39046 Reviewed-by: Hua Jing <jinghua@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-05-03doc: a3700: add build option of wtmi imageKen Ma
- Update build.txt for the build option - WTMI_IMG. WTMI_IMG can point to a image which does nothing, a image which supports EFUSE or a customized CM3 firmware image. Change-Id: I63304fe39c823d67db39c7ee111972fef063cecd Signed-off-by: Ken Ma <make@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39047 Reviewed-by: Hua Jing <jinghua@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-04-24doc: Update Marvell porting documentationallen yan
- Update Marvell platform porting documents. Change-Id: I6a8d3a0d527dcce342f358e8f0d49ea2598306ac Signed-off-by: allen yan <yanwei@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38689 Reviewed-by: Victor Gu <xigu@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-by: Hua Jing <jinghua@marvell.com>
2017-04-19Introduce ARM GIC-600 driverJeenu Viswambharan
ARM GIC-600 IP complies with ARM GICv3 architecture, but among others, implements a power control register in the Redistributor frame. This register must be programmed to mark the frame as powered on, before accessing other registers in the frame. Rest of initialization sequence remains the same. The driver provides APIs for Redistributor power management, and overrides those in the generic GICv3 driver. The driver data is shared between generic GICv3 driver and that of GIC-600. For FVP platform, the GIC-600 driver is chosen when FVP_USE_GIC_DRIVER is set to FVP_GIC600. Also update user guide. Change-Id: I321b2360728d69f6d4b0a747b2cfcc3fe5a20d67 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38156 Reviewed-by: Haim Boot <hayim@marvell.com> Tested-by: Haim Boot <hayim@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38549 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: Kostya Porotchkin <kostap@marvell.com>
2017-04-02doc: Add Marvell build and porting documentationKonstantin Porotchkin
Add marvell platform build and porting documents. Change-Id: I8e4ffb200269551fb1dd65d2ea4dfa3da399a8ae Signed-off-by: Haim Boot <hayim@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38135
2017-04-02drivers: Add drivers for Marvell A7K and A8K platformsKonstantin Porotchkin
Add Marvell drivers for A7K and A8K SoC families Change-Id: I7fb530e543e4f64782f41f8a058b6aabd82af9e8 Signed-off-by: Haim Boot <hayim@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/37916
2016-10-13Merge pull request #733 from danh-arm/dh/v1.3-finaldavidcunado-arm
Final updates for v1.3 release
2016-10-13Release v1.3: Minor updates to user guideDavid Cunado
Updated the user guide to clarify building FIP for AArch32. The instructions were previously specific to building a FIP for AArch64. Change-Id: I7bd1a6b8e810cfda411f707e04f479006817858e Signed-off-by: David Cunado <david.cunado@arm.com>
2016-10-13Release v1.3: update change-log.mdDavid Cunado
Updated change-log.md with summary of changes since release v1.2. Change-Id: Ia1e18ff4b0da567cf12dfcb53e6317e995100bdf
2016-10-12Merge pull request #732 from dp-arm/dp/pmf-docdanh-arm
PMF: Add documentation
2016-10-12PMF: Add documentationdp-arm
Add a Performance Measurement Framework (PMF) section to the firmware design document. Change-Id: I5953bd3b1067501f190164c8827d2b0d8022fc0b Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2016-10-12Merge pull request #731 from danh-arm/an/fix-juno-docdanh-arm
Fix documentation of bootwrapper boot on juno
2016-10-12Fix documentation of bootwrapper boot on junoAntonio Nino Diaz
The user guide incorrectly claimed that it is possible to load a bootwrapped kernel over JTAG on Juno in the same manner as an EL3 payload. In the EL3 payload boot flow, some of the platform initialisations in BL2 are modified. In particular, the TZC settings are modified to allow unrestricted access to DRAM. This in turn allows the debugger to access the DRAM and therefore to load the image there. In the BL33-preloaded boot flow though, BL2 uses the default TZC programming, which prevent access to most of the DRAM from secure state. When execution reaches the SPIN_ON_BL1_EXIT loop, the MMU is disabled and thus DS-5 presumably issues secure access transactions while trying to load the image, which fails. One way around it is to stop execution at the end of BL2 instead. At this point, the MMU is still enabled and the DRAM is mapped as non-secure memory. Therefore, the debugger is allowed to access this memory in this context and to sucessfully load the bootwrapped kernel in DRAM. The user guide is updated to suggest this alternative method. Co-Authored-By: Sandrine Bailleux <sandrine.bailleux@arm.com> Signed-off-by: Dan Handley <dan.handley@arm.com> Change-Id: I537ea1c6d2f96edc06bc3f512e770c748bcabe94
2016-10-12Merge pull request #728 from yatharth-arm/yk/AArch32_porting_docdanh-arm
AArch32: Update firmware-design.md
2016-10-12Merge pull request #727 from soby-mathew/sm/PSCI_lib_docdanh-arm
AArch32: Update user-guide and add DTBs
2016-10-11AArch32: Update user-guide and add DTBsSoby Mathew
This patch adds necessary updates for building and running Trusted Firmware for AArch32 to user-guide.md. The instructions for running on both `FVP_Base_AEMv8A-AEMv8A` in AArch32 mode and `FVP_Base_Cortex-A32x4` models are added. The device tree files for AArch32 Linux kernel are also added in the `fdts` folder. Change-Id: I0023b6b03e05f32637cb5765fdeda8c8df2d0d3e
2016-10-11AArch32: Update firmware-design.mdYatharth Kochar
This patch updates the firmware-design.md for AArch32 related changes. Change-Id: Idf392a44861ab9c1f59f3de4f3435f508b17c678
2016-10-11Docs: Rename duplicate title in porting guideJeenu Viswambharan
Fix one of the two titles that ended up being the same, although both describe different things. Change-Id: I66ecf369643709898ee4c014659d8f85c0480643
2016-09-28Docs: Add the PSCI library integration guideSoby Mathew
This patch adds the PSCI library integration guide for AArch32 ARMv8-A systems `psci-lib-integration-guide.md` to the documentation. The patch also adds appropriate reference to the new document in the `firmware-design.md` document. Change-Id: I2d5b5c6b612452371713399702e318e3c73a8ee0
2016-09-27Merge pull request #718 from sandrine-bailleux-arm/sb/update-deps-v1.3davidcunado-arm
Upgrade Linaro release, FVPs and mbed TLS versions
2016-09-27Upgrade Linaro release, FVPs and mbed TLS versionsSandrine Bailleux
This patch updates the User Guide to recommend the latest version of some of the software dependencies of ARM Trusted Firmware. - Upgrade Linaro release: 16.02 -> 16.06 - Upgrade FVPs - Foundation v8 FVP: 9.5 -> 10.1 - Base FVPs: 7.6 -> 7.7 - Upgrade mbed TLS library: 2.2.0 -> 2.2.1 Note that the latest release of mbed TLS as of today is 2.3.0 but it has compilations issues with the set of library configuration options that Trusted Firmware uses. 2.2.1 is the next most recent release known to build with TF. This patch also fixes the markdown formatting of a link in the User Guide. Change-Id: Ieb7dd336f4d3110fba060afec4ad580ae707a8f1
2016-09-21AArch32: Common changes needed for BL1/BL2Yatharth Kochar
This patch adds common changes to support AArch32 state in BL1 and BL2. Following are the changes: * Added functions for disabling MMU from Secure state. * Added AArch32 specific SMC function. * Added semihosting support. * Added reporting of unhandled exceptions. * Added uniprocessor stack support. * Added `el3_entrypoint_common` macro that can be shared by BL1 and BL32 (SP_MIN) BL stages. The `el3_entrypoint_common` is similar to the AArch64 counterpart with the main difference in the assembly instructions and the registers that are relevant to AArch32 execution state. * Enabled `LOAD_IMAGE_V2` flag in Makefile for `ARCH=aarch32` and added check to make sure that platform has not overridden to disable it. Change-Id: I33c6d8dfefb2e5d142fdfd06a0f4a7332962e1a3
2016-09-20Add new version of image loading.Yatharth Kochar
This patch adds capability to load BL images based on image descriptors instead of hard coded way of loading BL images. This framework is designed such that it can be readily adapted by any BL stage that needs to load images. In order to provide the above capability the following new platform functions are introduced: bl_load_info_t *plat_get_bl_image_load_info(void); This function returns pointer to the list of images that the platform has populated to load. bl_params_t *plat_get_next_bl_params(void); This function returns a pointer to the shared memory that the platform has kept aside to pass trusted firmware related information that next BL image needs. void plat_flush_next_bl_params(void); This function flushes to main memory all the params that are passed to next image. int bl2_plat_handle_post_image_load(unsigned int image_id) This function can be used by the platforms to update/use image information for given `image_id`. `desc_image_load.c` contains utility functions which can be used by the platforms to generate, load and executable, image list based on the registered image descriptors. This patch also adds new version of `load_image/load_auth_image` functions in-order to achieve the above capability. Following are the changes for the new version as compared to old: - Refactor the signature and only keep image_id and image_info_t arguments. Removed image_base argument as it is already passed through image_info_t. Given that the BL image base addresses and limit/size are already provided by the platforms, the meminfo_t and entry_point_info arguments are not needed to provide/reserve the extent of free memory for the given BL image. - Added check for the image size against the defined max size. This is needed because the image size could come from an unauthenticated source (e.g. the FIP header). To make this check, new member is added to the image_info_t struct for identifying the image maximum size. New flag `LOAD_IMAGE_V2` is added in the Makefile. Default value is 0. NOTE: `TRUSTED_BOARD_BOOT` is currently not supported when `LOAD_IMAGE_V2` is enabled. Change-Id: Ia7b643f4817a170d5a2fbf479b9bc12e63112e79
2016-09-19Merge pull request #702 from jeenu-arm/psci-node-hw-statedanh-arm
Support for PSCI NODE_HW_STATE
2016-09-15PSCI: Add support for PSCI NODE_HW_STATE APIJeenu Viswambharan
This patch adds support for NODE_HW_STATE PSCI API by introducing a new PSCI platform hook (get_node_hw_state). The implementation validates supplied arguments, and then invokes this platform-defined hook and returns its result to the caller. PSCI capabilities are updated accordingly. Also updates porting and firmware design guides. Change-Id: I808e55bdf0c157002a7c104b875779fe50a68a30
2016-09-12fiptool: Add support for printing the sha256 digest with info commanddp-arm
This feature allows one to quickly verify that the expected image is contained in the FIP without extracting the image and running sha256sum(1) on it. The sha256 digest is only shown when the verbose flag is used. This change requires libssl-dev to be installed in order to build Trusted Firmware. Previously, libssl-dev was optionally needed only to support Trusted Board Boot configurations. Fixes ARM-Software/tf-issues#124 Change-Id: Ifb1408d17f483d482bb270a589ee74add25ec5a6
2016-08-18Merge pull request #678 from soby-mathew/sm/PSCI_AArch32danh-arm
Introduce AArch32 support for PSCI library
2016-08-16Move up to Base FVP version 7.6Sandrine Bailleux
This patch updates the User Guide to move up from version 7.2 to 7.6 of the Base FVP. Change-Id: I792b2250deb4836266e14b40992ae59a5ab5f729
2016-08-15AArch32: Enable build at top level Makefile for FVPSoby Mathew
This patch enables the AArch32 build including SP_MIN in the top level Makefile. The build flag `ARCH` now can specify either `aarch64`(default) or `aarch32`. Currently only FVP AEM model is supported for AArch32 build. Another new build flag `AARCH32_SP` is introduced to specify the AArch32 secure payload to be built. Change-Id: Ie1198cb9e52d7da1b79b93243338fc3868b08faa
2016-08-09Merge pull request #661 from dp-arm/masterdanh-arm
Replace fip_create with fiptool
2016-07-29Replace fip_create with fiptooldp-arm
fiptool provides a more consistent and intuitive interface compared to the fip_create program. It serves as a better base to build on more features in the future. fiptool supports various subcommands. Below are the currently supported subcommands: 1) info - List the images contained in a FIP file. 2) create - Create a new FIP file with the given images. 3) update - Update an existing FIP with the given images. 4) unpack - Extract a selected set or all the images from a FIP file. 5) remove - Remove images from a FIP file. This is a new command that was not present in fip_create. To create a new FIP file, replace "fip_create" with "fiptool create". To update a FIP file, replace "fip_create" with "fiptool update". To dump the contents of a FIP file, replace "fip_create --dump" with "fiptool info". A compatibility script that emulates the basic functionality of fip_create is provided. Existing scripts might or might not work with the compatibility script. Users are strongly encouraged to migrate to fiptool. Fixes ARM-Software/tf-issues#87 Fixes ARM-Software/tf-issues#108 Fixes ARM-Software/tf-issues#361 Change-Id: I7ee4da7ac60179cc83cf46af890fd8bc61a53330
2016-07-28Merge pull request #668 from sandrine-bailleux-arm/sb/rodata-xn-docdanh-arm
Documentation for SEPARATE_CODE_AND_RODATA build flag
2016-07-28Documentation for SEPARATE_CODE_AND_RODATA build flagSandrine Bailleux
This patch documents the effect, cost and benefits of the SEPARATE_CODE_AND_RODATA build flag. Change-Id: Ic8daf0563fa6335930ad6c70b9c35f678e84d39d
2016-07-28Merge pull request #671 from antonio-nino-diaz-arm/an/unoptimised-memdanh-arm
ARM platforms: Define common image sizes
2016-07-25ARM platforms: Define common image sizesAntonio Nino Diaz
Compile option `ARM_BOARD_OPTIMISE_MMAP` has been renamed to `ARM_BOARD_OPTIMISE_MEM` because it now applies not only to defines related to the translation tables but to the image size as well. The defines `PLAT_ARM_MAX_BL1_RW_SIZE`, `PLAT_ARM_MAX_BL2_SIZE` and `PLAT_ARM_MAX_BL31_SIZE` have been moved to the file board_arm_def.h. This way, ARM platforms no longer have to set their own values if `ARM_BOARD_OPTIMISE_MEM=0` and they can specify optimized values otherwise. The common sizes have been set to the highest values used for any of the current build configurations. This is needed because in some build configurations some images are running out of space. This way there is a common set of values known to work for all of them and it can be optimized for each particular platform if needed. The space reserved for BL2 when `TRUSTED_BOARD_BOOT=0` has been increased. This is needed because when memory optimisations are disabled the values for Juno of `PLAT_ARM_MMAP_ENTRIES` and `MAX_XLAT_TABLES` are higher. If in this situation the code is compiled in debug mode and with "-O0", the code won't fit. Change-Id: I70a3d8d3a0b0cad1d6b602c01a7ea334776e718e
2016-07-19Introduce PSCI Library InterfaceSoby Mathew
This patch introduces the PSCI Library interface. The major changes introduced are as follows: * Earlier BL31 was responsible for Architectural initialization during cold boot via bl31_arch_setup() whereas PSCI was responsible for the same during warm boot. This functionality is now consolidated by the PSCI library and it does Architectural initialization via psci_arch_setup() during both cold and warm boots. * Earlier the warm boot entry point was always `psci_entrypoint()`. This was not flexible enough as a library interface. Now PSCI expects the runtime firmware to provide the entry point via `psci_setup()`. A new function `bl31_warm_entrypoint` is introduced in BL31 and the previous `psci_entrypoint()` is deprecated. * The `smc_helpers.h` is reorganized to separate the SMC Calling Convention defines from the Trusted Firmware SMC helpers. The former is now in a new header file `smcc.h` and the SMC helpers are moved to Architecture specific header. * The CPU context is used by PSCI for context initialization and restoration after power down (PSCI Context). It is also used by BL31 for SMC handling and context management during Normal-Secure world switch (SMC Context). The `psci_smc_handler()` interface is redefined to not use SMC helper macros thus enabling to decouple the PSCI context from EL3 runtime firmware SMC context. This enables PSCI to be integrated with other runtime firmware using a different SMC context. NOTE: With this patch the architectural setup done in `bl31_arch_setup()` is done as part of `psci_setup()` and hence `bl31_platform_setup()` will be invoked prior to architectural setup. It is highly unlikely that the platform setup will depend on architectural setup and cause any failure. Please be be aware of this change in sequence. Change-Id: I7f497a08d33be234bbb822c28146250cb20dab73
2016-07-18Introduce `el3_runtime` and `PSCI` librariesSoby Mathew
This patch moves the PSCI services and BL31 frameworks like context management and per-cpu data into new library components `PSCI` and `el3_runtime` respectively. This enables PSCI to be built independently from BL31. A new `psci_lib.mk` makefile is introduced which adds the relevant PSCI library sources and gets included by `bl31.mk`. Other changes which are done as part of this patch are: * The runtime services framework is now moved to the `common/` folder to enable reuse. * The `asm_macros.S` and `assert_macros.S` helpers are moved to architecture specific folder. * The `plat_psci_common.c` is moved from the `plat/common/aarch64/` folder to `plat/common` folder. The original file location now has a stub which just includes the file from new location to maintain platform compatibility. Most of the changes wouldn't affect platform builds as they just involve changes to the generic bl1.mk and bl31.mk makefiles. NOTE: THE `plat_psci_common.c` FILE HAS MOVED LOCATION AND THE STUB FILE AT THE ORIGINAL LOCATION IS NOW DEPRECATED. PLATFORMS SHOULD MODIFY THEIR MAKEFILES TO INCLUDE THE FILE FROM THE NEW LOCATION. Change-Id: I6bd87d5b59424995c6a65ef8076d4fda91ad5e86
2016-07-18Rework type usage in Trusted FirmwareSoby Mathew
This patch reworks type usage in generic code, drivers and ARM platform files to make it more portable. The major changes done with respect to type usage are as listed below: * Use uintptr_t for storing address instead of uint64_t or unsigned long. * Review usage of unsigned long as it can no longer be assumed to be 64 bit. * Use u_register_t for register values whose width varies depending on whether AArch64 or AArch32. * Use generic C types where-ever possible. In addition to the above changes, this patch also modifies format specifiers in print invocations so that they are AArch64/AArch32 agnostic. Only files related to upcoming feature development have been reworked. Change-Id: I9f8c78347c5a52ba7027ff389791f1dad63ee5f8
2016-07-08Introduce SEPARATE_CODE_AND_RODATA build flagSandrine Bailleux
At the moment, all BL images share a similar memory layout: they start with their code section, followed by their read-only data section. The two sections are contiguous in memory. Therefore, the end of the code section and the beginning of the read-only data one might share a memory page. This forces both to be mapped with the same memory attributes. As the code needs to be executable, this means that the read-only data stored on the same memory page as the code are executable as well. This could potentially be exploited as part of a security attack. This patch introduces a new build flag called SEPARATE_CODE_AND_RODATA, which isolates the code and read-only data on separate memory pages. This in turn allows independent control of the access permissions for the code and read-only data. This has an impact on memory footprint, as padding bytes need to be introduced between the code and read-only data to ensure the segragation of the two. To limit the memory cost, the memory layout of the read-only section has been changed in this case. - When SEPARATE_CODE_AND_RODATA=0, the layout is unchanged, i.e. the read-only section still looks like this (padding omitted): | ... | +-------------------+ | Exception vectors | +-------------------+ | Read-only data | +-------------------+ | Code | +-------------------+ BLx_BASE In this case, the linker script provides the limits of the whole read-only section. - When SEPARATE_CODE_AND_RODATA=1, the exception vectors and read-only data are swapped, such that the code and exception vectors are contiguous, followed by the read-only data. This gives the following new layout (padding omitted): | ... | +-------------------+ | Read-only data | +-------------------+ | Exception vectors | +-------------------+ | Code | +-------------------+ BLx_BASE In this case, the linker script now exports 2 sets of addresses instead: the limits of the code and the limits of the read-only data. Refer to the Firmware Design guide for more details. This provides platform code with a finer-grained view of the image layout and allows it to map these 2 regions with the appropriate access permissions. Note that SEPARATE_CODE_AND_RODATA applies to all BL images. Change-Id: I936cf80164f6b66b6ad52b8edacadc532c935a49
2016-07-08BL1: Add linker symbol identifying end of ROM contentSandrine Bailleux
This patch adds a new linker symbol in BL1's linker script named '__BL1_ROM_END__', which marks the end of BL1's ROM content. This covers BL1's code, read-only data and read-write data to relocate in Trusted SRAM. The address of this new linker symbol is exported to C code through the 'BL1_ROM_END' macro. The section related to linker symbols in the Firmware Design guide has been updated and improved. Change-Id: I5c442ff497c78d865ffba1d7d044511c134e11c7
2016-07-04Merge pull request #651 from Xilinx/zynqmp_uartdanh-arm
zynqmp: Make UART selectable
2016-07-04Merge pull request #652 from soby-mathew/sm/pmf_psci_statdanh-arm
Introduce PMF and implement PSCI STAT APIs
2016-06-16Add optional PSCI STAT residency & count functionsYatharth Kochar
This patch adds following optional PSCI STAT functions: - PSCI_STAT_RESIDENCY: This call returns the amount of time spent in power_state in microseconds, by the node represented by the `target_cpu` and the highest level of `power_state`. - PSCI_STAT_COUNT: This call returns the number of times a `power_state` has been used by the node represented by the `target_cpu` and the highest power level of `power_state`. These APIs provides residency statistics for power states that has been used by the platform. They are implemented according to v1.0 of the PSCI specification. By default this optional feature is disabled in the PSCI implementation. To enable it, set the boolean flag `ENABLE_PSCI_STAT` to 1. This also sets `ENABLE_PMF` to 1. Change-Id: Ie62e9d37d6d416ccb1813acd7f616d1ddd3e8aff
2016-06-16Add Performance Measurement Framework(PMF)Yatharth Kochar
This patch adds Performance Measurement Framework(PMF) in the ARM Trusted Firmware. PMF is implemented as a library and the SMC interface is provided through ARM SiP service. The PMF provides capturing, storing, dumping and retrieving the time-stamps, by enabling the development of services by different providers, that can be easily integrated into ARM Trusted Firmware. The PMF capture and retrieval APIs can also do appropriate cache maintenance operations to the timestamp memory when the caller indicates so. `pmf_main.c` consists of core functions that implement service registration, initialization, storing, dumping and retrieving the time-stamp. `pmf_smc.c` consists SMC handling for registered PMF services. `pmf.h` consists of the macros that can be used by the PMF service providers to register service and declare time-stamp functions. `pmf_helpers.h` consists of internal macros that are used by `pmf.h` By default this feature is disabled in the ARM trusted firmware. To enable it set the boolean flag `ENABLE_PMF` to 1. NOTE: The caller is responsible for specifying the appropriate cache maintenance flags and for acquiring/releasing appropriate locks before/after capturing/retrieving the time-stamps. Change-Id: Ib45219ac07c2a81b9726ef6bd9c190cc55e81854
2016-06-15zynqmp: Add option to select between Cadence UARTsSoren Brinkmann
Add build time option 'cadence1' for ZYNQMP_CONSOLE to select the 2nd UART available in the SoC. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Acked-by: Michal Simek <michal.simek@xilinx.com>
2016-06-15Merge pull request #650 from Xilinx/zynqmp-updatesdanh-arm
Zynqmp updates
2016-06-09Add support for QEMU virt ARMv8-A targetJens Wiklander
This patch adds support for the QEMU virt ARMv8-A target. Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
generated by cgit (git 2.34.1) at 2024-06-17 15:09:06 +0000