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2018-04-15Report errata workaround status to consoleJeenu Viswambharan
The errata reporting policy is as follows: - If an errata workaround is enabled - If it applies (i.e. the CPU is affected by the errata), an INFO message is printed, confirming that the errata workaround has been applied. - If it does not apply, a VERBOSE message is printed, confirming that the errata workaround has been skipped. - If an errata workaround is not enabled, but would have applied had it been, a WARN message is printed, alerting that errata workaround is missing. The CPU errata messages are printed by both BL1 (primary CPU only) and runtime firmware on debug builds, once for each CPU/errata combination. Relevant output from Juno r1 console when ARM Trusted Firmware is built with PLAT=juno LOG_LEVEL=50 DEBUG=1: VERBOSE: BL1: cortex_a57: errata workaround for 806969 was not applied VERBOSE: BL1: cortex_a57: errata workaround for 813420 was not applied INFO: BL1: cortex_a57: errata workaround for disable_ldnp_overread was applied WARNING: BL1: cortex_a57: errata workaround for 826974 was missing! WARNING: BL1: cortex_a57: errata workaround for 826977 was missing! WARNING: BL1: cortex_a57: errata workaround for 828024 was missing! WARNING: BL1: cortex_a57: errata workaround for 829520 was missing! WARNING: BL1: cortex_a57: errata workaround for 833471 was missing! ... VERBOSE: BL31: cortex_a57: errata workaround for 806969 was not applied VERBOSE: BL31: cortex_a57: errata workaround for 813420 was not applied INFO: BL31: cortex_a57: errata workaround for disable_ldnp_overread was applied WARNING: BL31: cortex_a57: errata workaround for 826974 was missing! WARNING: BL31: cortex_a57: errata workaround for 826977 was missing! WARNING: BL31: cortex_a57: errata workaround for 828024 was missing! WARNING: BL31: cortex_a57: errata workaround for 829520 was missing! WARNING: BL31: cortex_a57: errata workaround for 833471 was missing! ... VERBOSE: BL31: cortex_a53: errata workaround for 826319 was not applied INFO: BL31: cortex_a53: errata workaround for disable_non_temporal_hint was applied Also update documentation. Change-Id: Iccf059d3348adb876ca121cdf5207bdbbacf2aba Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/52569 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-11-21plat: marvell: a8k: make SCP_BL2 image mandatory for a8k familyGrzegorz Jaszczyk
Force build with SCP_BL2 on a80x0 boards. This enforcement ensures that the required service CPU executable is always incluided in the final system flash image. Change-Id: I6efe32ec20ab5e193e56273b016a76f646d2c4ee Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/46209 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Yoav Gvili <ygvili@marvell.com>
2017-08-27mvebu: io-win: add parameter for ccu function to set AP numberHanna Hawa
Part of AP810 preparation and driver changes, change IO_WIN driver to get the number of AP it should initialize, to get the AP base address and window map. No functional changes introduced by this patch. Change-Id: I20522ebcdd9bcea4691a4d65cb839bcb5d46f4e6 Signed-off-by: Hanna Hawa <hannah@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43397 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2017-08-27mvebu: ccu: add parameter for ccu function to set AP numberHanna Hawa
Part of AP810 preparation and driver changes, change CCU driver to get the number of AP it should initialize, to get the AP base address and window map. No functional changes introduced by this patch. Change-Id: I6f221b6da68a11e6ff93e0997eb633c12309723d Signed-off-by: Hanna Hawa <hannah@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43396 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2017-08-27Adjusted documentation files to new Sphinx tool.Nir Erez
Change-Id: Ifb8ddb39543a0a82772ea2ec0c7f9b11591efcec Signed-off-by: Nir Erez <nerez@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43409 Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2017-08-21fix: ap806: io-win: change the name of RFU window to be IO-WINHanna Hawa
The name of RFU used in old AP806-Z SoC. This patch update the used name to be IO-WIN, the correct unit name in AP806-Ax, and AP810-A0 Change-Id: I9fc12e25c34aa97aa09a7b9b21837e71092058d9 Signed-off-by: Hanna Hawa <hannah@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43184 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-08-13makefile: aro: add define flag for ARO.Christine Gharzuzi
Add define flag for ARO and set it by default to 1. No functional change Change-Id: Id5ae19f8fa9d1096b80615fffa9ccec1eb8f4f9c Signed-off-by: Christine Gharzuzi <chrisg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/42866 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-by: Hanna Hawa <hannah@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2017-08-10plat: marvell: a8k: add support for scp_bl2 concatenated imageGrzegorz Jaszczyk
The Armada 8K has 5 service CPUs and Armada 7K has 3. Therefore it was required to provide a method for loading firmware to all of the service CPUs. To achieve that, the scp_bl2 image in fact is file containing up to 5 concatenated firmwares. This patch allows to recognize new format of scp_bl2 image, interpret it correctly, restore built-in images and load particular image to appropriate service CPU pointed in image header. The new scp_bl2 file format is: 0x0: File header (magic, nr_of_images) 0x8: Image header 0 (type, length, version) 0x14: Image header 1 (type, length, version) ... 0xyy Build-in image described by image header 0 0xzz Build-in image described by image header 1 The possible images that can be built in scp_bl2 image are firmwares for: mss ap cm3, mss cp0 cm3, mss cp1 cm3, mg cp0 cm3 and mg cp1 cm3. Thanks to the file format and headers for each file, ATF platform code is able to recognise how many files are built-in and what is their destination (to which co-processor they need to be loaded). Change-Id: I07719eb10f43a028ebea4713ccf149b86db81ec4 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/42635 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: Kostya Porotchkin <kostap@marvell.com>
2017-08-01fix: marvell: doc: Change the BL image name to match the real oneKonstantin Porotchkin
Change the generic SCP_BL2 name in the build manual to the real binary name (FreeRTOS) - RTOSDemo-cm3.bin Change-Id: Ic2f1f8f79f5f509ed04ed8b9f89d19b55ae20e15 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/42482 Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2017-07-06doc: a3700: update build file to add ddr3 1cs 1GB supportzachary
This patch adds build option DDR_TOPOLOGY number to support DDR3 1cs 1GB build. Example: make DEBUG=1 USE_COHERENT_MEM=0 DDR_TOPOLOGY=4 PLAT=a3700 all fip Change-Id: If19dd6636847fba4c03172c1315aab0a646f9d26 Signed-off-by: zachary <zhangzg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/40547 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Hua Jing <jinghua@marvell.com> Reviewed-by: Wilson Ding <dingwei@marvell.com> Reviewed-by: Gina Tadmore <gina@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com>
2017-06-29fix: doc: porting: Fix wrong file name of the address mapKonstantin Porotchkin
Fix wrong reference to the file name containing the SoC memory map. Change-Id: Ia95b2eff64d96b8517714bb2674b65756fd8d0eb Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/40605 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Neta Zur Hershkovits <neta@marvell.com>
2017-06-04doc: a3700: update build.txt for wtptp tool updatejinghua
This patch udpates the build doc for A3700: - Adds build option WTP, which points to wtp tool source code tree directory. - Removes tbb tools installation part, since it is not needed anymore. Change-Id: I6fcdf67435aae0b86e9682d8a05d00fcf719737e Signed-off-by: jinghua <jinghua@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/40080 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/40118 Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2017-05-10fix: doc: mvebu: correct DDR topology option number for DDR4 2CSzachary
- There was a wrong DDR Topology option number description issue for DDR4 2CS. - The patch changes its option number from 4 to 3 for DDR4 2CS. Change-Id: If37b885b231f57215ea1b5bc51faa5b0e3d234eb Signed-off-by: zachary <zhangzg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39136 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Wilson Ding <dingwei@marvell.com> Reviewed-by: Gina Tadmore <gina@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com>
2017-05-03plat: marvell: a8k: Rename A80x0 customer to McbinKonstantin Porotchkin
Rename Macciatobin platform from a80x0_cust to a80x0_mcbin Change-Id: I715be80891f7c2d5d68a84f22a0568eb94b26c18 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38411 Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2017-05-03doc: a3700: update build file for adding ddr4 2cs 4GB supportzachary
- This patch adds build option DDR_TOPOLOGY number to support DDR4 2cs 4GB build. - Example: make DEBUG=1 USE_COHERENT_MEM=0 DDR_TOPOLOGY=3 PLAT=a3700 all fip Change-Id: I966dc6630fda5ebab906ba669ef93f4614bd2a36 Signed-off-by: zachary <zhangzg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38864 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Gina Tadmore <gina@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-05-03doc: a3700: update build.txt for new clock preset 1200/750Ken Ma
Change-Id: I0143ffbeae1d48e2700b35107588b4d6de893485 Signed-off-by: Ken Ma <make@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39046 Reviewed-by: Hua Jing <jinghua@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-05-03doc: a3700: add build option of wtmi imageKen Ma
- Update build.txt for the build option - WTMI_IMG. WTMI_IMG can point to a image which does nothing, a image which supports EFUSE or a customized CM3 firmware image. Change-Id: I63304fe39c823d67db39c7ee111972fef063cecd Signed-off-by: Ken Ma <make@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39047 Reviewed-by: Hua Jing <jinghua@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-04-24doc: Update Marvell porting documentationallen yan
- Update Marvell platform porting documents. Change-Id: I6a8d3a0d527dcce342f358e8f0d49ea2598306ac Signed-off-by: allen yan <yanwei@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38689 Reviewed-by: Victor Gu <xigu@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-by: Hua Jing <jinghua@marvell.com>
2017-04-19Introduce ARM GIC-600 driverJeenu Viswambharan
ARM GIC-600 IP complies with ARM GICv3 architecture, but among others, implements a power control register in the Redistributor frame. This register must be programmed to mark the frame as powered on, before accessing other registers in the frame. Rest of initialization sequence remains the same. The driver provides APIs for Redistributor power management, and overrides those in the generic GICv3 driver. The driver data is shared between generic GICv3 driver and that of GIC-600. For FVP platform, the GIC-600 driver is chosen when FVP_USE_GIC_DRIVER is set to FVP_GIC600. Also update user guide. Change-Id: I321b2360728d69f6d4b0a747b2cfcc3fe5a20d67 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38156 Reviewed-by: Haim Boot <hayim@marvell.com> Tested-by: Haim Boot <hayim@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38549 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: Kostya Porotchkin <kostap@marvell.com>
2017-04-02doc: Add Marvell build and porting documentationKonstantin Porotchkin
Add marvell platform build and porting documents. Change-Id: I8e4ffb200269551fb1dd65d2ea4dfa3da399a8ae Signed-off-by: Haim Boot <hayim@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38135
2017-04-02drivers: Add drivers for Marvell A7K and A8K platformsKonstantin Porotchkin
Add Marvell drivers for A7K and A8K SoC families Change-Id: I7fb530e543e4f64782f41f8a058b6aabd82af9e8 Signed-off-by: Haim Boot <hayim@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/37916
2016-10-13Merge pull request #733 from danh-arm/dh/v1.3-finaldavidcunado-arm
Final updates for v1.3 release
2016-10-13Release v1.3: Minor updates to user guideDavid Cunado
Updated the user guide to clarify building FIP for AArch32. The instructions were previously specific to building a FIP for AArch64. Change-Id: I7bd1a6b8e810cfda411f707e04f479006817858e Signed-off-by: David Cunado <david.cunado@arm.com>
2016-10-13Release v1.3: update change-log.mdDavid Cunado
Updated change-log.md with summary of changes since release v1.2. Change-Id: Ia1e18ff4b0da567cf12dfcb53e6317e995100bdf
2016-10-12Merge pull request #732 from dp-arm/dp/pmf-docdanh-arm
PMF: Add documentation
2016-10-12PMF: Add documentationdp-arm
Add a Performance Measurement Framework (PMF) section to the firmware design document. Change-Id: I5953bd3b1067501f190164c8827d2b0d8022fc0b Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2016-10-12Merge pull request #731 from danh-arm/an/fix-juno-docdanh-arm
Fix documentation of bootwrapper boot on juno
2016-10-12Fix documentation of bootwrapper boot on junoAntonio Nino Diaz
The user guide incorrectly claimed that it is possible to load a bootwrapped kernel over JTAG on Juno in the same manner as an EL3 payload. In the EL3 payload boot flow, some of the platform initialisations in BL2 are modified. In particular, the TZC settings are modified to allow unrestricted access to DRAM. This in turn allows the debugger to access the DRAM and therefore to load the image there. In the BL33-preloaded boot flow though, BL2 uses the default TZC programming, which prevent access to most of the DRAM from secure state. When execution reaches the SPIN_ON_BL1_EXIT loop, the MMU is disabled and thus DS-5 presumably issues secure access transactions while trying to load the image, which fails. One way around it is to stop execution at the end of BL2 instead. At this point, the MMU is still enabled and the DRAM is mapped as non-secure memory. Therefore, the debugger is allowed to access this memory in this context and to sucessfully load the bootwrapped kernel in DRAM. The user guide is updated to suggest this alternative method. Co-Authored-By: Sandrine Bailleux <sandrine.bailleux@arm.com> Signed-off-by: Dan Handley <dan.handley@arm.com> Change-Id: I537ea1c6d2f96edc06bc3f512e770c748bcabe94
2016-10-12Merge pull request #728 from yatharth-arm/yk/AArch32_porting_docdanh-arm
AArch32: Update firmware-design.md
2016-10-12Merge pull request #727 from soby-mathew/sm/PSCI_lib_docdanh-arm
AArch32: Update user-guide and add DTBs
2016-10-11AArch32: Update user-guide and add DTBsSoby Mathew
This patch adds necessary updates for building and running Trusted Firmware for AArch32 to user-guide.md. The instructions for running on both `FVP_Base_AEMv8A-AEMv8A` in AArch32 mode and `FVP_Base_Cortex-A32x4` models are added. The device tree files for AArch32 Linux kernel are also added in the `fdts` folder. Change-Id: I0023b6b03e05f32637cb5765fdeda8c8df2d0d3e
2016-10-11AArch32: Update firmware-design.mdYatharth Kochar
This patch updates the firmware-design.md for AArch32 related changes. Change-Id: Idf392a44861ab9c1f59f3de4f3435f508b17c678
2016-10-11Docs: Rename duplicate title in porting guideJeenu Viswambharan
Fix one of the two titles that ended up being the same, although both describe different things. Change-Id: I66ecf369643709898ee4c014659d8f85c0480643
2016-09-28Docs: Add the PSCI library integration guideSoby Mathew
This patch adds the PSCI library integration guide for AArch32 ARMv8-A systems `psci-lib-integration-guide.md` to the documentation. The patch also adds appropriate reference to the new document in the `firmware-design.md` document. Change-Id: I2d5b5c6b612452371713399702e318e3c73a8ee0
2016-09-27Merge pull request #718 from sandrine-bailleux-arm/sb/update-deps-v1.3davidcunado-arm
Upgrade Linaro release, FVPs and mbed TLS versions
2016-09-27Upgrade Linaro release, FVPs and mbed TLS versionsSandrine Bailleux
This patch updates the User Guide to recommend the latest version of some of the software dependencies of ARM Trusted Firmware. - Upgrade Linaro release: 16.02 -> 16.06 - Upgrade FVPs - Foundation v8 FVP: 9.5 -> 10.1 - Base FVPs: 7.6 -> 7.7 - Upgrade mbed TLS library: 2.2.0 -> 2.2.1 Note that the latest release of mbed TLS as of today is 2.3.0 but it has compilations issues with the set of library configuration options that Trusted Firmware uses. 2.2.1 is the next most recent release known to build with TF. This patch also fixes the markdown formatting of a link in the User Guide. Change-Id: Ieb7dd336f4d3110fba060afec4ad580ae707a8f1
2016-09-21AArch32: Common changes needed for BL1/BL2Yatharth Kochar
This patch adds common changes to support AArch32 state in BL1 and BL2. Following are the changes: * Added functions for disabling MMU from Secure state. * Added AArch32 specific SMC function. * Added semihosting support. * Added reporting of unhandled exceptions. * Added uniprocessor stack support. * Added `el3_entrypoint_common` macro that can be shared by BL1 and BL32 (SP_MIN) BL stages. The `el3_entrypoint_common` is similar to the AArch64 counterpart with the main difference in the assembly instructions and the registers that are relevant to AArch32 execution state. * Enabled `LOAD_IMAGE_V2` flag in Makefile for `ARCH=aarch32` and added check to make sure that platform has not overridden to disable it. Change-Id: I33c6d8dfefb2e5d142fdfd06a0f4a7332962e1a3
2016-09-20Add new version of image loading.Yatharth Kochar
This patch adds capability to load BL images based on image descriptors instead of hard coded way of loading BL images. This framework is designed such that it can be readily adapted by any BL stage that needs to load images. In order to provide the above capability the following new platform functions are introduced: bl_load_info_t *plat_get_bl_image_load_info(void); This function returns pointer to the list of images that the platform has populated to load. bl_params_t *plat_get_next_bl_params(void); This function returns a pointer to the shared memory that the platform has kept aside to pass trusted firmware related information that next BL image needs. void plat_flush_next_bl_params(void); This function flushes to main memory all the params that are passed to next image. int bl2_plat_handle_post_image_load(unsigned int image_id) This function can be used by the platforms to update/use image information for given `image_id`. `desc_image_load.c` contains utility functions which can be used by the platforms to generate, load and executable, image list based on the registered image descriptors. This patch also adds new version of `load_image/load_auth_image` functions in-order to achieve the above capability. Following are the changes for the new version as compared to old: - Refactor the signature and only keep image_id and image_info_t arguments. Removed image_base argument as it is already passed through image_info_t. Given that the BL image base addresses and limit/size are already provided by the platforms, the meminfo_t and entry_point_info arguments are not needed to provide/reserve the extent of free memory for the given BL image. - Added check for the image size against the defined max size. This is needed because the image size could come from an unauthenticated source (e.g. the FIP header). To make this check, new member is added to the image_info_t struct for identifying the image maximum size. New flag `LOAD_IMAGE_V2` is added in the Makefile. Default value is 0. NOTE: `TRUSTED_BOARD_BOOT` is currently not supported when `LOAD_IMAGE_V2` is enabled. Change-Id: Ia7b643f4817a170d5a2fbf479b9bc12e63112e79
2016-09-19Merge pull request #702 from jeenu-arm/psci-node-hw-statedanh-arm
Support for PSCI NODE_HW_STATE
2016-09-15PSCI: Add support for PSCI NODE_HW_STATE APIJeenu Viswambharan
This patch adds support for NODE_HW_STATE PSCI API by introducing a new PSCI platform hook (get_node_hw_state). The implementation validates supplied arguments, and then invokes this platform-defined hook and returns its result to the caller. PSCI capabilities are updated accordingly. Also updates porting and firmware design guides. Change-Id: I808e55bdf0c157002a7c104b875779fe50a68a30
2016-09-12fiptool: Add support for printing the sha256 digest with info commanddp-arm
This feature allows one to quickly verify that the expected image is contained in the FIP without extracting the image and running sha256sum(1) on it. The sha256 digest is only shown when the verbose flag is used. This change requires libssl-dev to be installed in order to build Trusted Firmware. Previously, libssl-dev was optionally needed only to support Trusted Board Boot configurations. Fixes ARM-Software/tf-issues#124 Change-Id: Ifb1408d17f483d482bb270a589ee74add25ec5a6
2016-08-18Merge pull request #678 from soby-mathew/sm/PSCI_AArch32danh-arm
Introduce AArch32 support for PSCI library
2016-08-16Move up to Base FVP version 7.6Sandrine Bailleux
This patch updates the User Guide to move up from version 7.2 to 7.6 of the Base FVP. Change-Id: I792b2250deb4836266e14b40992ae59a5ab5f729
2016-08-15AArch32: Enable build at top level Makefile for FVPSoby Mathew
This patch enables the AArch32 build including SP_MIN in the top level Makefile. The build flag `ARCH` now can specify either `aarch64`(default) or `aarch32`. Currently only FVP AEM model is supported for AArch32 build. Another new build flag `AARCH32_SP` is introduced to specify the AArch32 secure payload to be built. Change-Id: Ie1198cb9e52d7da1b79b93243338fc3868b08faa
2016-08-09Merge pull request #661 from dp-arm/masterdanh-arm
Replace fip_create with fiptool
2016-07-29Replace fip_create with fiptooldp-arm
fiptool provides a more consistent and intuitive interface compared to the fip_create program. It serves as a better base to build on more features in the future. fiptool supports various subcommands. Below are the currently supported subcommands: 1) info - List the images contained in a FIP file. 2) create - Create a new FIP file with the given images. 3) update - Update an existing FIP with the given images. 4) unpack - Extract a selected set or all the images from a FIP file. 5) remove - Remove images from a FIP file. This is a new command that was not present in fip_create. To create a new FIP file, replace "fip_create" with "fiptool create". To update a FIP file, replace "fip_create" with "fiptool update". To dump the contents of a FIP file, replace "fip_create --dump" with "fiptool info". A compatibility script that emulates the basic functionality of fip_create is provided. Existing scripts might or might not work with the compatibility script. Users are strongly encouraged to migrate to fiptool. Fixes ARM-Software/tf-issues#87 Fixes ARM-Software/tf-issues#108 Fixes ARM-Software/tf-issues#361 Change-Id: I7ee4da7ac60179cc83cf46af890fd8bc61a53330
2016-07-28Merge pull request #668 from sandrine-bailleux-arm/sb/rodata-xn-docdanh-arm
Documentation for SEPARATE_CODE_AND_RODATA build flag
2016-07-28Documentation for SEPARATE_CODE_AND_RODATA build flagSandrine Bailleux
This patch documents the effect, cost and benefits of the SEPARATE_CODE_AND_RODATA build flag. Change-Id: Ic8daf0563fa6335930ad6c70b9c35f678e84d39d
2016-07-28Merge pull request #671 from antonio-nino-diaz-arm/an/unoptimised-memdanh-arm
ARM platforms: Define common image sizes
2016-07-25ARM platforms: Define common image sizesAntonio Nino Diaz
Compile option `ARM_BOARD_OPTIMISE_MMAP` has been renamed to `ARM_BOARD_OPTIMISE_MEM` because it now applies not only to defines related to the translation tables but to the image size as well. The defines `PLAT_ARM_MAX_BL1_RW_SIZE`, `PLAT_ARM_MAX_BL2_SIZE` and `PLAT_ARM_MAX_BL31_SIZE` have been moved to the file board_arm_def.h. This way, ARM platforms no longer have to set their own values if `ARM_BOARD_OPTIMISE_MEM=0` and they can specify optimized values otherwise. The common sizes have been set to the highest values used for any of the current build configurations. This is needed because in some build configurations some images are running out of space. This way there is a common set of values known to work for all of them and it can be optimized for each particular platform if needed. The space reserved for BL2 when `TRUSTED_BOARD_BOOT=0` has been increased. This is needed because when memory optimisations are disabled the values for Juno of `PLAT_ARM_MMAP_ENTRIES` and `MAX_XLAT_TABLES` are higher. If in this situation the code is compiled in debug mode and with "-O0", the code won't fit. Change-Id: I70a3d8d3a0b0cad1d6b602c01a7ea334776e718e
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