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2017-09-24fix: mci: fix uart recovery by correctly determining when to skip mci confGrzegorz Jaszczyk
The process of enabling MCI simultaneous transactions is performed in bootrom when the source id is SAR_MCIX4. Because according to design guidelines the MCI simultaneous transaction shouldn't be enabled more then once, atf code verified if this configuration was performed by bootrom, by determining boot source. Hitherto verification wasn't sufficient in case of uart recovery(boot from uart) since the bootrom flow is different and mentioned initialization is skipped even if boot source is SAR_MCIX4. The new verification base on appropriate mci's register content: if the appropriate reg contains 0x0 it means that the bootrom didn't perform required mci configuration. Before this patch after uart recovery the CPU hang was observed, since MCI wasn't configured to allow simultaneous read/write transaction (e.g. doing AP to CP1 access over MCI and vice-versa triggered the issue). Change-Id: I9514bbd7ecac4282206be54a98b278cdf2ddd4e8 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/44567 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-08-31pcie: a8040_ocp: pcie stabilization configurationsIgal Liberman
This patch optimizes the pcie comphy receiver and transmitter configuration. It includes the following optimizations: RX - Force FFE constant values instead of trained values TX - Increase the full swing value and update all presets (p0 - p10) accordingly Change-Id: I6e48d543eb343b453ed804d9b48bcfec86c30225 Signed-off-by: Ofir Fedida <ofedida@marvell.com> Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43426 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-08-31fix: mci: adjust backoff thresholds and the outstanding transactions limitsOmri Itach
update parameters for various backoff thresholds and the limits of the outstanding transactions. This is to prevent backoff at all the queues, except for the PQ of AP (writes from CP to AP), which cannot be prevented. Changes list: 1) Global RX backoff threshold changed from 0xB to 0x3f (bits 22:16 of register 25 of IHB on both ends) 2) PQ backoff threshold at AP side changed from 0x7 to 0x6 (IHB register 0 of AP, bits 22:16) 3) RX Delta changed from 0x2 to 0xf (IHB register 0 on both sides, bits 7:4) 4) set AP read & write oustanding limits to 4. 5) set CP write oustanding limit to 18, and CP read oustanding to 12. Change-Id: I31869f134a368f681ac769caae880d2e45e37c21 Signed-off-by: Omri Itach <omrii@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/40930 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-08-29mvebu: io_win: move GCR offset to be defined in platformHanna Hawa
As part of AP810 preparation and driver changes, move GCR offset to be defined in platform file and not in IO_WIN driver as AP810 & AP806 have different GCR offset. No functional changes introduced by this patch. Change-Id: Iadb4d7294909fa764bf26aa6b7442bb8a33a9c53 Signed-off-by: Hanna Hawa <hannah@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43469 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com>
2017-08-29fix: mvebu: ccu: remove skip window functionHanna Hawa
Skip window function as we don't use it any more, this function was added to skip the SRAM window in old u-boot revision, since we move all the window configuration to ATF, no need for it. Skip window #1, because it configured by default to internal registers. Change-Id: I9ad3fedfb3ac770652430db3c8679ebefda4fae2 Signed-off-by: Hanna Hawa <hannah@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43465 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com>
2017-08-27mvebu: io-win: add function to get the target ID of GCRHanna Hawa
Part of AP810 preparation and driver changes, may some north bridge have different target IDs for the GCR. Change-Id: I06221baf00f2f69d40382e27d49fe166ab43de4e Signed-off-by: Hanna Hawa <hannah@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43402 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2017-08-27mvebu: ccu: add function to get the target ID of GCRHanna Hawa
Part of AP810 preparation and driver changes, may some north bridge have different target IDs for the GCR. Change-Id: I4c25baf5414c016374c61ec979cf1c40fa6cde4c Signed-off-by: Hanna Hawa <hannah@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43401 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-08-27thermal: a8k: add thermal sensor driverVictor Axelrod
This patch adds thermal sensor driver for a8k external thermal sensor. The driver was ported from u-boot 2015.01 (mvebu_ext_thermal_28nm.c). Its functionality was reduced to one sensor only (a few are available on ap). The api provides with thermal sensor's configuration get, thermal sensor's init, and temperature read functions. Change-Id: I0fd456b95d115b23e575fd6c6e09ac88ff73c3da Signed-off-by: Victor Axelrod <victora@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43424 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-08-27mvebu: llc: add support for multiple AP for LLC driverHanna Hawa
Part of AP810 preparation and driver changes, change LLC driver to get the number of AP it should initialize, to get the AP base address of LLC. No functional changes introduced by this patch. Change-Id: Ia6b1d4c0de4c6ded11f964c87163d8df45856bbc Signed-off-by: Hanna Hawa <hannah@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43398 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-08-27mvebu: io-win: add parameter for ccu function to set AP numberHanna Hawa
Part of AP810 preparation and driver changes, change IO_WIN driver to get the number of AP it should initialize, to get the AP base address and window map. No functional changes introduced by this patch. Change-Id: I20522ebcdd9bcea4691a4d65cb839bcb5d46f4e6 Signed-off-by: Hanna Hawa <hannah@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43397 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2017-08-27mvebu: ccu: add parameter for ccu function to set AP numberHanna Hawa
Part of AP810 preparation and driver changes, change CCU driver to get the number of AP it should initialize, to get the AP base address and window map. No functional changes introduced by this patch. Change-Id: I6f221b6da68a11e6ff93e0997eb633c12309723d Signed-off-by: Hanna Hawa <hannah@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43396 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2017-08-27fix: ap806: io-win: fix typo in dump IO Windows functionHanna Hawa
Change-Id: Id416824e93e781e2a72953ef63cb1108c0869acc Signed-off-by: Hanna Hawa <hannah@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43389 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-08-21fix: ap806: io-win: change the name of RFU window to be IO-WINHanna Hawa
The name of RFU used in old AP806-Z SoC. This patch update the used name to be IO-WIN, the correct unit name in AP806-Ax, and AP810-A0 Change-Id: I9fc12e25c34aa97aa09a7b9b21837e71092058d9 Signed-off-by: Hanna Hawa <hannah@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43184 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-08-10plat: marvell: a8k: add ccu configuration for cp0 and cp1 in bl2 stageGrzegorz Jaszczyk
Since the scp_bl2 image can contain firmware for cp1 and cp0 coprocessors, the access to cp0 and cp1 need to be provided. More precisely it is required to: - get the information about device id which is stored in cp0 registers (to distinguish between cases where we have cp0 and cp1 or standalone cp0) - get the access to cp which is needed for loading fw for cp0/cp1 coprocessors Change-Id: I9cd92778aed5c2f66365538becbfa591a116c602 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/42634 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-08-07Add GIC SGIR R/W functions as common functionsZhoujie Wu
The new GIC driver has no GICD_SGIR operation functions in neither GIC v2 or v3 drivers. The GICD_SGIR is a common register in GIC v2 & v3, so add the sgir functions as common functions. Previously the functions are only GIC v2 functions in include/drivers/arm/gic_v2.h Change-Id: Ia2a7ee0195ead09d85d20c5ffd5b57d2c519a20d Signed-off-by: Zhoujie Wu <zjwu@marvell.com> Signed-off-by: Kevin Peng <kevinp@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38638 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-08-07drivers: mochi: cp110: Enable I2C for CP in debug modeKonstantin Porotchkin
Add SW WA for ERRATA FE-6163379 (STORM-1443). Enable i2c when CP i2c init is selected by SAR. Change-Id: Ifd31e342028e31b3c58393a5beef6107ae39e452 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/42419 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Omri Itach <omrii@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com>
2017-08-01drivers: marvell: i2c: Reduce delays in the driverKonstantin Porotchkin
Reduce i2c delays in the driver taken from legacy code. - remove delay at IRQ clear start - reduce delay after soft reset from 2ms to 200us - reduce delays after register set from 1ms to 1us Change-Id: Icda910d20895c6e1ba40e6214d0db289aec03437 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/42364 Reviewed-by: Igal Liberman <igall@marvell.com> Reviewed-by: Yoav Gvili <ygvili@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2017-08-01fix: mci: a8k: fix enter/exit flow of PIDI mode for CPDavid Sniatkiwicz
Bit 25 of reg 7 enables access to the PHY registers. In order to access CP PHY this bit should be enabled. Change-Id: I0e89c2264db6671dce842825746bb640ef976001 Signed-off-by: David Sniatkiwicz <davidsn@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/41999 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-by: Omri Itach <omrii@marvell.com>
2017-07-24fix: aro: Missing break command in switch caseChristine Gharzuzi
in case the chosen frequency is 1000/800 the frequency is configured as 2000 Mhz due to missing break command in the case for 1000/800 so it is configured to the default frequency Change-Id: I86555f386d0661328e164f47c6681b9e809e96b2 Signed-off-by: Christine Gharzuzi <chrisg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/42047 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-07-19fix: mvebu: pcie_dw: set preset request vector to preset4Igal Liberman
This preset is used during the initial part of the equalization master phase. According to hardware measurements, our PCIe hardware can use preset4 or preset6. However, when we try both preset4 and preset6, we might get timeouts, which may cause failure for PCIe endpoint operation. This patch updates the MAC and the PHY to use only preset4. This solves an issue, observed when A7040 PCAC opernates as NIC in a PC (inmod of SNIC module fails). Change-Id: I056cc2ddf93eed937539d3417611f1b16a6aea38 Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/41771 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/41814
2017-07-19fix: mvebu: pcie_dw: set correct hints to lane equalization registerIgal Liberman
Currently, we don't modify the default preset values in lane equalization register which may cause issues with some PCIe GEN3 devices which fail to link up. According to hardware measurements, we must modify the preset values to improve PCIe GEN3 link establishment. Change-Id: Ib93656ee75e6125c0a270550d1fb384111f406f6 Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/41770 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/41813
2017-07-18fix: aro: Fix equation for cpu frequency calculationChristine Gharzuzi
wrong parentheses in the equations for calculating the clusters' frequency which caused booting to freeze when 2000 MHz frequency is chosen Change-Id: I47cd7b7368e4f07ff9e5d7ea55d845613e495558 Signed-off-by: Christine Gharzuzi <chrisg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/41780 Verified-Armada8K: Igal Liberman <igall@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2017-07-16atf: ARO: Introduce Adaptive Ring OscillatorChristine Gharzuzi
is a clock generator, which is used in AP806 as a source clock for the CPU clusters. In AP806 the ARO is not the major clock, and this document discuss the way to switch from PLL mode (which is the default mode) to ARO mode. The motivation for ARO usage is improving the Yield of the device at 2Ghz and improving the power consumption at that work point. In general – ARO allow lower Vmin for running in this premium work point which serves both cause (yield and power). Change-Id: I76a391a29cd98abedcd003f52d37a60459ee8b80 Signed-off-by: Christine Gharzuzi <chrisg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/40640 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Hanna Hawa <hannah@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-06-27Revert "fix: pcie: temporarily disable pcie clock fix"Igal Liberman
This reverts commit 3cf300e7695e6883787ce01d5c4b97ced96bb8c1. Following u-boot 2017 fix, we can use the correct setting for PCIe clock direction. Change-Id: If65ffad0bb507392d7815d00ef6dff62d5ccb9dc Reviewed-on: http://vgitil04.il.marvell.com:8080/40780 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-06-18i2c: a8k: unstuck when start clear bit timeoutsAnton
When performing back-to-back resets (~1s apart) SPD I2C fails as the bus gets stuck: ERROR: Start clear bit timeout Release the bus using the "unstuck" register. This requires to soft-reset to complete successfully (otherwise I2C drives to finish the requested start/stop and interferes with unstuck FSM). On successful completion of unstuck process reset i2c again. The solution assumes failure occurs on the first access, therefore -EAGAIN returned triggers a re-try and SPD access is completed successfully: NOTICE: Gathering DRAM information ERROR: Start clear bit timeout Trying to "unstuck i2c"... ok mv_ddr: version 16.12.1 mv_ddr: scrubbing memory... Change-Id: I6a3a5ccb45edd0472de770ba55b747e6b6d357ff Signed-off-by: Anton <antone@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/40573 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-06-18i2c: a8k: add comment which describes baudrate settingsNeta Zur
Change-Id: I6b62e8ff3089542bd9d1c49ff7f85eab98533deb Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Neta Zur <neta@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/40574 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-05-22fix: mci: remove redundant enablement of register-mode accessOmri Itach
according to design guidelines, enablement of register-mode access (mci_enable_phy_regs_access) is redundant and should not performed as a part of MCI initialization for A80x0-A1. Change-Id: I7b8fb70a4d6fa518ee56c64556305210a183f7a6 Signed-off-by: Omri Itach <omrii@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39746 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39761
2017-05-22fix: mci: Fine tune of MCI parametersOmri Itach
At AP and CP //reg[15:8] – RX NQ threshold reduced to 0x7 //reg[23:16] – RX PQ threshold reduced to 0x7 //reg[31:24] – RX RQ threshold reduced to 0x7 //reg[7:4] – RX delta threshold reduced to 0x2 At AP: //reg[4:0] – WR outstanding reduced to 0x6 (0x5 written to reg) //reg[10:6] – RD outstanding reduced to 0x6 (0x5 written to reg) At CP: //reg[10:6] – RD outstanding reduced to d’14 (d’13 written to reg) Change-Id: I00d1f22501d22171015873a1b12224e0c0443fbe Signed-off-by: Omri Itach <omrii@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39526 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> (cherry picked from commit cbcf48899360940826678e370d5c247bb782938d) Reviewed-on: http://vgitil04.il.marvell.com:8080/39797
2017-05-22fix: mci: ap806: skip setting MCI ID assignment when booting from MCIOmri Itach
When boot source is from MCI, bootROM is already enabling MCI simultaneous transactions (ID assignment), so in that case we must avoid enabling it for the 2nd time (according to design guidelines). Change-Id: I3967fc3526e27356f9e8ebf184b52cc21003e3c1 Signed-off-by: Omri Itach <omrii@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39557 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> (cherry picked from commit c721c97f7ea0724d3eaed92168897db4fc1b9b03) Reviewed-on: http://vgitil04.il.marvell.com:8080/39795
2017-05-22fix: pcie: temporarily disable pcie clock fixIgal Liberman
After commit "f82b49e fix: pcie: cp110: fix pcie clock selection" we encountered some instabilities in PCIe. This patch disables the PCIe clock fix temporarily, until we figure out the root cause for this this issue. Change-Id: I521e4495118fab2bcbe1e99e6080d1cbb2b08f39 Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39663 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39759
2017-05-17fix: pcie: fix pcie clock selection for A2 revisionIgal Liberman
This patch fixes incorrect handling of pcie clock: If pcie_clk is set to input (by the Sample-at-Reset), PCIE refclk buffer 0/1 source field in PCIe_Reference_Clock_Buffer_Control register should be set to 1 and not 0 as it done now. Change-Id: I14fedce9d3299b5b85eb742048f03b17f1f9ab14 Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39456 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39544
2017-05-16fix: mvebu: pcie: set correct preset4 valueIgal Liberman
Currently, incorrect preset4 value is used. This patch fixes the preset4 according to HW measurments. Change-Id: I839a6c843e912182bb0c71e3ab836dac27ce8a97 Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39421 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39491
2017-05-16fix: pcie: cp110: update analog parameters according to latest ETPIgal Liberman
Add PCIE analog parameters initialization values according to latest ETP. Change-Id: I3f5892702610e46ebaba7485e3cef5817f1518b5 Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/36995 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39411 Reviewed-on: http://vgitil04.il.marvell.com:8080/39490
2017-05-11fix: ap806: enable 48-bit virtual addressMarcin Wojtas
Issue found when enable 48-bit Virtual Address in kernel In ARMv8 the CPU can work with 48-bit virtual address, at this case for propagating TLB maintenance 44-bit of Physical address are needed. Marvell interconnect is configured to be 40-bit address by default, therefore AxAddr[43:40] are not propagated so the DVM is not working. Change-Id: I7b8a3ec7960697814079f2c932fd06962bfa4c75 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39185 Reviewed-by: Igal Liberman <igall@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Hanna Hawa <hannah@marvell.com>
2017-05-11fix: pcie: move pcie initialization to cp110_ble_initIgal Liberman
In addition, add a call to cp110_pcie_clk_cfg(). This function is responsible for configuring PCIe ref clock and must me called before configuring PCIe interface. Change-Id: I807a4466d9c4459f9403b2542d771c961f07a46e Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39257 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-05-11fix: mvebu: pcie: improve PCIE mac configurationIgal Liberman
This patch does the following: - Disable auto flush If auto flash is enabled, we can't enable/disable the link and perform "hot reset" - Set link equalization training to preset4 According to ETP, this is the best preset that our receiver can handle. - Remove VPD capability from the capability list It's not supported - Remove SRIOV capability from the capability list It's not supported - In end point mode: unmask the reset request: The hot reset and link disable/enable must penetrate and reset the MAC configurations. Change-Id: Ia189aaef29b175eb351ee9a861ae3883b3677fa9 Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39226 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-05-11fix: pcie: cp110: fix pcie clock selectionIgal Liberman
There's a difference between PCIe clock configuration. in CP110 revision A1 and CP110 revision A2 CP110 revision A1: The SatR that decides if the PCIE uses internal refclock or external refclock does not work properly. When the clock is set to input we need to do extra configuration in order to make the input clock functional. (Iboth PCIe clocks must be aligned, so if one set to input, we must Performe the configuration). CP110 revision A2: PCIe Reference Clock Buffer Control register must be set according to the clock direction (input/output), there's a field for each refclock (pcie0 and pcie1) which are set accordingly to the clock configuration. Change-Id: I6b0150293bfd2d7595d19016c1fd82c4d4ed326a Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/39297 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-04-21gicv3: arm: support SPI and PPI irq save and restoreVictor Gu
During suspend and resume, some SoC will issue warm reset and the SPI and PPI irq states are cleared, so IO devices can not continue to work after resume. Thus the SPI and PPI irq states should be saved and restored. This patch adds the SPI and PPI irq state PM support in ARM GICv3 driver. Change-Id: Ief459375b5cd4f02ba2df015eed2f72d208cf0d1 Signed-off-by: Victor Gu <xigu@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/37430 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Haim Boot <hayim@marvell.com> Reviewed-by: Hua Jing <jinghua@marvell.com> Signed-off-by: zachary <zhangzg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38075 Tested-by: Hua Jing <jinghua@marvell.com> Signed-off-by: zachary <zhangzg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38608
2017-04-19Introduce ARM GIC-600 driverJeenu Viswambharan
ARM GIC-600 IP complies with ARM GICv3 architecture, but among others, implements a power control register in the Redistributor frame. This register must be programmed to mark the frame as powered on, before accessing other registers in the frame. Rest of initialization sequence remains the same. The driver provides APIs for Redistributor power management, and overrides those in the generic GICv3 driver. The driver data is shared between generic GICv3 driver and that of GIC-600. For FVP platform, the GIC-600 driver is chosen when FVP_USE_GIC_DRIVER is set to FVP_GIC600. Also update user guide. Change-Id: I321b2360728d69f6d4b0a747b2cfcc3fe5a20d67 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38156 Reviewed-by: Haim Boot <hayim@marvell.com> Tested-by: Haim Boot <hayim@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38549 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: Kostya Porotchkin <kostap@marvell.com>
2017-04-19GICv3: Introduce power management APIs for RedistributorJeenu Viswambharan
Some GICv3 implementations have provision for power management operations at Redistributor level. This patch introduces and provides place-holders for Redistributor power management. The default implementations are empty stubs, but are weakly bound so as to enable implementation-specific drivers to override them. Change-Id: I4fec1358693d3603ca5dce242a2f7f0e730516d8 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38155 Reviewed-by: Haim Boot <hayim@marvell.com> Tested-by: Haim Boot <hayim@marvell.com> (cherry picked from commit 3d3fb7dfabb67e2a893296b8188ae394d329763b) Reviewed-on: http://vgitil04.il.marvell.com:8080/38548 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: Kostya Porotchkin <kostap@marvell.com>
2017-04-10drivers: a3700: Add drivers for Marvell A3700 platformszachary
- Add UART drivers for Marvell A3700 SoC families Change-Id: Ie3363f98414317acd8958814698fc8fb4fc26c73 Signed-off-by: zachary <zhangzg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38604 Reviewed-by: Hua Jing <jinghua@marvell.com> Tested-by: Hua Jing <jinghua@marvell.com>
2017-04-04fix: cp110: enable optional RTC reconfigurationMarcin Wojtas
This commit enables optional reset of the RTC, in case its registers' contents did not sustain the reboot or power-off/on sequence. Without it, further usage of RTC is impossible (e.g. writing values to RTC_TIME register will not succeed). JIRA: A7K8K-1243 The reset is performed only if Clock Correction register does not comprise MVEBU_RTC_NOMINAL_TIMING, what helps to distinguish, whether the software configured RTC before or it comprises the default value. Change-Id: I9d6288ac85a453c545c1ec0b773b32144aea1759 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38377 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: Kostya Porotchkin <kostap@marvell.com>
2017-04-02drivers: Add drivers for Marvell A7K and A8K platformsKonstantin Porotchkin
Add Marvell drivers for A7K and A8K SoC families Change-Id: I7fb530e543e4f64782f41f8a058b6aabd82af9e8 Signed-off-by: Haim Boot <hayim@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/37916
2017-04-02io: Allow image load to address zeroKonstantin Porotchkin
Allow zero-address assertion bypass if requested by platform compilation flag PLAT_ALLOW_ZERO_ADDR_COPY. This patch allows loading BL33 (u-boot) to address 0x0 Change-Id: I10518db13466017110358437790ce5212d52d9e6 Signed-off-by: Haim Boot <hayim@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/37914
2017-04-02delay_timer: Add timer value get functionsKonstantin Porotchkin
Add ability to get timer value in micro- and milliseconds. Change-Id: I864619c23fe8a2a01cef86795e39d1b0bfd2e3d3 Signed-off-by: Victor Axelrod <victora@marvell.com> Signed-off-by: Ofir Fedida <ofedida@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/37913 Reviewed-by: Haim Boot <hayim@marvell.com>
2016-09-12GICv3: Allow either G1S or G0 interrupts to be configuredYatharth Kochar
Currently the GICv3 driver mandates that platform populate both G1S and G0 interrupts. However, it is possible that a given platform is not interested in both the groups and just needs to specify either one of them. This patch modifies the `gicv3_rdistif_init()` & `gicv3_distif_init()` functions to allow either G1S or G0 interrupts to be configured. Fixes ARM-software/tf-issues#400 Change-Id: I43572b0e08ae30bed5af9334f25d35bf439b0d2b
2016-08-18Merge pull request #678 from soby-mathew/sm/PSCI_AArch32danh-arm
Introduce AArch32 support for PSCI library
2016-08-17Merge pull request #682 from sudeep-holla/gicv3_ns_intrdanh-arm
gicv3: disable Group1 NonSecure interrupts during core powerdown
2016-08-17Merge pull request #680 from hzhuang1/emmc_cmd23_v2danh-arm
emmc: support CMD23
2016-08-12emmc: support CMD23Haojian Zhuang
Support CMD23. When CMD23 is used, CMD12 could be avoided. Two scenarios: 1. CMD17 for single block, CMD18 + CMD12 for multiple blocks. 2. CMD23 + CMD18 for both single block and multiple blocks. The emmc_init() should initialize whether CMD23 is supported or not. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
generated by cgit (git 2.34.1) at 2024-06-15 14:56:15 +0000