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2018-04-16Implement support for SMCCC v1.1Dimitris Papastamos
SMCCC v1.1 comes with a relaxed calling convention for AArch64 callers. The caller only needs to save x0-x3 before doing an SMC call. This patch adds support for SMCCC_VERSION and SMCCC_ARCH_FEATURES. Refer to "Firmware Interfaces for mitigating CVE_2017_5715 System Software on Arm Systems"[0] for more information. [0] https://developer.arm.com/-/media/developer/pdf/ARM%20DEN%200070A%20Firmware%20interfaces%20for%20mitigating%20CVE-2017-5715_V1.0.pdf Change-Id: If5b1c55c17d6c5c7cb9c2c3ed355d3a91cdad0a9 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/53235 Tested-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-04-16Optimize/cleanup BPIALL workaroundDimitris Papastamos
In the initial implementation of this workaround we used a dedicated workaround context to save/restore state. This patch reduces the footprint as no additional context is needed. Additionally, this patch reduces the memory loads and stores by 20%, reduces the instruction count and exploits static branch prediction to optimize the SMC path. Change-Id: Ia9f6bf06fbf8a9037cfe7f1f1fb32e8aec38ec7d Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/53233 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-04-16Workaround for CVE-2017-5715 on Cortex A73 and A75Dimitris Papastamos
Invalidate the Branch Target Buffer (BTB) on entry to EL3 by temporarily dropping into AArch32 Secure-EL1 and executing the `BPIALL` instruction. This is achieved by using 3 vector tables. There is the runtime vector table which is used to handle exceptions and 2 additional tables which are required to implement this workaround. The additional tables are `vbar0` and `vbar1`. The sequence of events for handling a single exception is as follows: 1) Install vector table `vbar0` which saves the CPU context on entry to EL3 and sets up the Secure-EL1 context to execute in AArch32 mode with the MMU disabled and I$ enabled. This is the default vector table. 2) Before doing an ERET into Secure-EL1, switch vbar to point to another vector table `vbar1`. This is required to restore EL3 state when returning from the workaround, before proceeding with normal EL3 exception handling. 3) While in Secure-EL1, the `BPIALL` instruction is executed and an SMC call back to EL3 is performed. 4) On entry to EL3 from Secure-EL1, the saved context from step 1) is restored. The vbar is switched to point to `vbar0` in preparation to handle further exceptions. Finally a branch to the runtime vector table entry is taken to complete the handling of the original exception. This workaround is enabled by default on the affected CPUs. NOTE ==== There are 4 different stubs in Secure-EL1. Each stub corresponds to an exception type such as Sync/IRQ/FIQ/SError. Each stub will move a different value in `R0` before doing an SMC call back into EL3. Without this piece of information it would not be possible to know what the original exception type was as we cannot use `ESR_EL3` to distinguish between IRQs and FIQs. Change-Id: I90b32d14a3735290b48685d43c70c99daaa4b434 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/53232 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-04-16Cortex-A72: Implement workaround for erratum 859971Eleanor Bonnici
Erratum 855971 applies to revision r0p3 or earlier Cortex-A72 CPUs. The recommended workaround is to disable instruction prefetch. Change-Id: I7fde74ee2a8a23b2a8a1891b260f0eb909fad4bf Signed-off-by: Eleanor Bonnici <Eleanor.bonnici@arm.com> Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/53228 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-08-22Define write function for ICC_SGI1R_EL1wangwen
GICv3 driver has no ICC_SGI1R_EL1 write function, so add write function for ICC_SGI1R_EL1 Change-Id: I71084673f960f17453ea850bfd4b4bb48e682445 Signed-off-by: wangwen <wangwen@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/41098 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-06-28Merge pull request #978 from etienne-lms/minor-builddanh-arm
Minor build fixes
2017-06-23Merge pull request #997 from dp-arm/dp/spedavidcunado-arm
aarch64: Enable Statistical Profiling Extensions for lower ELs
2017-06-23Merge pull request #995 from davidcunado-arm/dc/init_regdavidcunado-arm
Fully initialise essential control registers
2017-06-23context_mgmt: declare extern cm_set_next_context() for AArch32Etienne Carriere
This change avoids warning when setting -Wmissing-prototypes to compile bl1_context_mgmt.c. Reported-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
2017-06-23bl: security_state should be of type unsigned intEtienne Carriere
security_state is either 0 or 1. Prevent sign conversion potential error (setting -Werror=sign-conversion results in a build error). Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
2017-06-22aarch32: Apply workaround for errata 813419 of Cortex-A57Dimitris Papastamos
TLBI instructions for monitor mode won't have the desired effect under specific circumstances in Cortex-A57 r0p0. The workaround is to execute DSB and TLBI twice each time. Even though this errata is only needed in r0p0, the current errata framework is not prepared to apply run-time workarounds. The current one is always applied if compiled in, regardless of the CPU or its revision. The `DSB` instruction used when initializing the translation tables has been changed to `DSB ISH` as an optimization and to be consistent with the barriers used for the workaround. NOTE: This workaround is present in AArch64 TF and already enabled by default on Juno. Change-Id: I10b0baa304ed64b13b7b26ea766e61461e759dfa Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2017-06-22aarch64: Enable Statistical Profiling Extensions for lower ELsdp-arm
SPE is only supported in non-secure state. Accesses to SPE specific registers from SEL1 will trap to EL3. During a world switch, before `TTBR` is modified the SPE profiling buffers are drained. This is to avoid a potential invalid memory access in SEL1. SPE is architecturally specified only for AArch64. Change-Id: I04a96427d9f9d586c331913d815fdc726855f6b0 Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-06-21Fully initialise essential control registersDavid Cunado
This patch updates the el3_arch_init_common macro so that it fully initialises essential control registers rather then relying on hardware to set the reset values. The context management functions are also updated to fully initialise the appropriate control registers when initialising the non-secure and secure context structures and when preparing to leave EL3 for a lower EL. This gives better alignement with the ARM ARM which states that software must initialise RES0 and RES1 fields with 0 / 1. This patch also corrects the following typos: "NASCR definitions" -> "NSACR definitions" Change-Id: Ia8940b8351dc27bc09e2138b011e249655041cfc Signed-off-by: David Cunado <david.cunado@arm.com>
2017-06-20aarch32: Fix L2CTRL definition for Cortex A57 and A72Dimitris Papastamos
Fixes ARM-software/tf-issues#495 Change-Id: I6a0aea78f670cc199873218a18af1d9cc2a6fafd Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2017-06-20aarch32: Implement errata workarounds for Cortex A53Dimitris Papastamos
This brings the implementation on par with the software errata workarounds for AArch64. Change-Id: Id103602e35b1c0ad3705a5b2b7cdb34dd8a8c5e2 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
2017-06-14include: add U()/ULL() macros for constantsVarun Wadekar
This patch uses the U() and ULL() macros for constants, to fix some of the signed-ness defects flagged by the MISRA scanner. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-06-14Add U() macro to share constants between C and other sourcesVarun Wadekar
This patch adds the U(_x) macros to utils_def.h to allow constants to be shared between C and other sources. Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-06-14Unique names for defines in the CPU librariesVarun Wadekar
This patch makes all the defines in the CPU libraries unique, by prefixing them with the CPU name. NOTE: PLATFORMS USING THESE MACROS WILL HAVE TO UPDATE THEIR CODE TO START USING THE UPDATED NAMES Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
2017-06-09Fix stdlib defines for AArch32Soby Mathew
Some of the macro defines in the header files of `include/lib/stdlib/machine/` folder are not correct for AArch32. This patch fixes the same. Change-Id: I8bfaf638a7986fd902648d2074537bd26c313cb3 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
2017-06-07stdlib: support AARCH32 in endian head fileHaojian Zhuang
Add the support of AARCH32 in endian head file. The code is also imported from FreeBSD 11.0. It's based on commit in below. commit 4e3a5b429989b4ff621682ff1462f801237bd551 Author: mmel <mmel@FreeBSD.org> Date: Tue Nov 10 12:02:41 2015 +0000 ARM: Remove trailing whitespace from sys/arm/include No functional changes. Approved by: kib (mentor) Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2017-06-07stdlib: import endian head file from freebsdHaojian Zhuang
Import endian head files from FreeBSD 11.0. The link of FreeBSD source code is https://github.com/freebsd/freebsd Import machine/endian.h from sys/arm64/include/endian.h in FreeBSD. commit d09ff72cef8e35dbf62f7363dcbf07b453f06243 Author: andrew <andrew@FreeBSD.org> Date: Mon Mar 23 11:54:56 2015 +0000 Add the start of the arm64 machine headers. This is the subset needed to start getting userland libraries building. Reviewed by: imp Sponsored by: The FreeBSD Foundation Import sys/endian.h from sys/sys/endian.h in FreeBSD. commit 3c3fa2f5b0c7640373fcbcc3f667bf7794e8e609 Author: phk <phk@FreeBSD.org> Date: Thu May 20 06:16:13 2010 +0000 Fix some way-past-brucification complaints from FlexeLint. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
2017-06-01Add support for Cortex-A75 and Cortex-A55 CPUsDavid Wang
Both Cortex-A75 and Cortex-A55 CPUs use the ARM DynamIQ Shared Unit (DSU). The power-down and power-up sequences are therefore mostly managed in hardware, and required software operations are considerably simpler. Change-Id: I68b30e6e1ebe7c041d5e67f39c59f08575fc7ecc Co-authored-by: Sandrine Bailleux <sandrine.bailleux@arm.com> Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2017-05-24Cortex-A53: add some bit definitionsHaojian Zhuang
Add some bit definitions of CPUACTLR register in Cortex-A53 CPU library. Change-Id: I142fd8ac4b06dd651a32e22951e71cdebbea123a Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org> Signed-off-by: Dan Handley <dan.handley@arm.com>
2017-05-24build: Introduce clang supportdp-arm
Only the compiler is switched to clang. The assembler and linker are provided by the GCC toolchain. clang is used to build TF when the base name of the path assigned to `CC` contains the string 'clang'. `CROSS_COMPILE` is still needed and should point to the appropriate GCC toolchain. Tested with clang 3.9.x and 4.0.x. Change-Id: I53236d64e3c83ad27fc843bae5fcdae30f2e325e Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-05-24Merge pull request #938 from masahir0y/tools_sharedanh-arm
Collect headers shared between TF and host-tools into include/tools_share
2017-05-23fip: move headers shared between TF and fiptool to include/tools_shareMasahiro Yamada
Some header files need to be shared between TF and host programs. For fiptool, two headers are copied to the tools/fiptool directory, but it looks clumsy. This commit introduces a new directory, include/tools_share, which collects headers that should be shared between TF and host programs. This will clarify the interface exposed to host tools. We should add new headers to this directory only when we really need to do so. For clarification, I inserted a blank line between headers from the include/ directory (#include <...>) and ones from a local directory (#include "..." ). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
2017-05-22Merge pull request #939 from dp-arm/dp/AArch32_tbbrdanh-arm
Add TBBR and FWU support for AArch32
2017-05-16Simplify assert() to reduce memory usageAntonio Nino Diaz
The behaviour of assert() now depends on the value of the new optional platform define `PLAT_LOG_LEVEL_ASSERT`. This defaults to `LOG_LEVEL` if not defined by the platform. - If `PLAT_LOG_LEVEL_ASSERT` >= `LOG_LEVEL_VERBOSE`, it prints the file name, line and asserted expression. - If `PLAT_LOG_LEVEL_ASSERT` >= `LOG_LEVEL_INFO`, it prints the file name and line. - If not, it doesn't print anything. Note the old behaviour was to print the function name whereas now it prints the file name. This reduces memory usage because the file name is shared between all assert calls in a given file. Also, the default behaviour in debug builds is to no longer print the asserted expression, greatly reducing the string usage. For FVP debug builds this change saves approximately: No TBBR TBBR BL1 1.6 KB 2.2 KB BL2 1.7 KB 2.1 KB BL31 2.6 KB 3.3 KB Change-Id: I2947569d593df0b25611dc3c7a6096f42155c115 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2017-05-12Merge pull request #930 from antonio-nino-diaz-arm/an/fixes-xlat-v2davidcunado-arm
Minor fixes to the xlat tables lib v2
2017-05-12AArch32: Rework SMC context save and restore mechanismSoby Mathew
The current SMC context data structure `smc_ctx_t` and related helpers are optimized for case when SMC call does not result in world switch. This was the case for SP_MIN and BL1 cold boot flow. But the firmware update usecase requires world switch as a result of SMC and the current SMC context helpers were not helping very much in this regard. Therefore this patch does the following changes to improve this: 1. Add monitor stack pointer, `spmon` to `smc_ctx_t` The C Runtime stack pointer in monitor mode, `sp_mon` is added to the SMC context, and the `smc_ctx_t` pointer is cached in `sp_mon` prior to exit from Monitor mode. This makes is easier to retrieve the context when the next SMC call happens. As a result of this change, the SMC context helpers no longer depend on the stack to save and restore the register. This aligns it with the context save and restore mechanism in AArch64. 2. Add SCR in `smc_ctx_t` Adding the SCR register to `smc_ctx_t` makes it easier to manage this register state when switching between non secure and secure world as a result of an SMC call. Change-Id: I5e12a7056107c1701b457b8f7363fdbf892230bf Signed-off-by: Soby Mathew <soby.mathew@arm.com> Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-05-11Merge pull request #927 from jeenu-arm/state-switchdavidcunado-arm
Execution state switch
2017-05-09Minor fixes to the xlat tables lib v2Antonio Nino Diaz
- Fix some comments. - Remove duplicated definition. - Make xlat_arch_get_max_supported_pa() private in aarch64. Change-Id: I629237209cfb2ce7b0c4bd539d63dd81d45b2edd Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2017-05-05Merge pull request #924 from antonio-nino-diaz-arm/an/fix-xn-bitdavidcunado-arm
Fix execute-never permissions in xlat tables libs
2017-05-04Merge pull request #925 from dp-arm/dp/spdxdavidcunado-arm
Use SPDX license identifiers
2017-05-04Introduce ARM SiP service to switch execution stateJeenu Viswambharan
In AArch64, privileged exception levels control the execution state (a.k.a. register width) of the immediate lower Exception Level; i.e. whether the lower exception level executes in AArch64 or AArch32 state. For an exception level to have its execution state changed at run time, it must request the change by raising a synchronous exception to the higher exception level. This patch implements and adds such a provision to the ARM SiP service, by which an immediate lower exception level can request to switch its execution state. The execution state is switched if the request is: - raised from non-secure world; - raised on the primary CPU, before any secondaries are brought online with CPU_ON PSCI call; - raised from an exception level immediately below EL3: EL2, if implemented; otherwise NS EL1. If successful, the SMC doesn't return to the caller, but to the entry point supplied with the call. Otherwise, the caller will observe the SMC returning with STATE_SW_E_DENIED code. If ARM Trusted Firmware is built for AArch32, the feature is not supported, and the call will always fail. For the ARM SiP service: - Add SMC function IDs for both AArch32 and AArch64; - Increment the SiP service minor version to 2; - Adjust the number of supported SiP service calls. Add documentation for ARM SiP service. Fixes ARM-software/tf-issues#436 Change-Id: I4347f2d6232e69fbfbe333b340fcd0caed0a4cea Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2017-05-03Use SPDX license identifiersdp-arm
To make software license auditing simpler, use SPDX[0] license identifiers instead of duplicating the license text in every file. NOTE: Files that have been imported by FreeBSD have not been modified. [0]: https://spdx.org/ Change-Id: I80a00e1f641b8cc075ca5a95b10607ed9ed8761a Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-05-02Merge pull request #919 from davidcunado-arm/dc/smc_yielding_genericdavidcunado-arm
Update terminology: standard SMC to yielding SMC
2017-05-02Add macro to check whether the CPU implements an ELJeenu Viswambharan
Replace all instances of checks with the new macro. Change-Id: I0eec39b9376475a1a9707a3115de9d36f88f8a2a Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
2017-05-02Fix execute-never permissions in xlat tables libsAntonio Nino Diaz
Translation regimes that only support one virtual address space (such as the ones for EL2 and EL3) can flag memory regions as execute-never by setting to 1 the XN bit in the Upper Attributes field in the translation tables descriptors. Translation regimes that support two different virtual address spaces (such as the one shared by EL1 and EL0) use bits PXN and UXN instead. The Trusted Firmware runs at EL3 and EL1, it has to handle translation tables of both translation regimes, but the previous code handled both regimes the same way, as if both had only 1 VA range. When trying to set a descriptor as execute-never it would set the XN bit correctly in EL3, but it would set the XN bit in EL1 as well. XN is at the same bit position as UXN, which means that EL0 was being prevented from executing code at this region, not EL1 as the code intended. Therefore, the PXN bit was unset to 0 all the time. The result is that, in AArch64 mode, read-only data sections of BL2 weren't protected from being executed. This patch adds support of translation regimes with two virtual address spaces to both versions of the translation tables library, fixing the execute-never permissions for translation tables in EL1. The library currently does not support initializing translation tables for EL0 software, therefore it does not set/unset the UXN bit. If EL1 software needs to initialize translation tables for EL0 software, it should use a different library instead. Change-Id: If27588f9820ff42988851d90dc92801c8ecbe0c9 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
2017-04-29Merge branch 'integration' into tf_issue_461Scott Branden
2017-04-29Move defines in utils.h to utils_def.h to fix shared header compile issuesScott Branden
utils.h is included in various header files for the defines in it. Some of the other header files only contain defines. This allows the header files to be shared between host and target builds for shared defines. Recently types.h has been included in utils.h as well as some function prototypes. Because of the inclusion of types.h conflicts exist building host tools abd these header files now. To solve this problem, move the defines to utils_def.h and have this included by utils.h and change header files to only include utils_def.h and not pick up the new types.h being introduced. Fixes ARM-software/tf-issues#461 Signed-off-by: Scott Branden <scott.branden@broadcom.com> Remove utils_def.h from utils.h This patch removes utils_def.h from utils.h as it is not required. And also makes a minor change to ensure Juno platform compiles. Change-Id: I10cf1fb51e44a8fa6dcec02980354eb9ecc9fa29
2017-04-26Update terminology: standard SMC to yielding SMCDavid Cunado
Since Issue B (November 2016) of the SMC Calling Convention document standard SMC calls are renamed to yielding SMC calls to help avoid confusion with the standard service SMC range, which remains unchanged. http://infocenter.arm.com/help/topic/com.arm.doc.den0028b/ARM_DEN0028B_SMC_Calling_Convention.pdf This patch adds a new define for yielding SMC call type and deprecates the current standard SMC call type. The tsp is migrated to use this new terminology and, additionally, the documentation and code comments are updated to use this new terminology. Change-Id: I0d7cc0224667ee6c050af976745f18c55906a793 Signed-off-by: David Cunado <david.cunado@arm.com>
2017-04-26Merge pull request #907 from antonio-nino-diaz-arm/an/smc-ret0davidcunado-arm
tspd:FWU:Fix usage of SMC_RET0
2017-04-25Merge pull request #901 from vwadekar/freebsd-stdbool-headerdavidcunado-arm
lib: stdbool header from the FreeBSD project
2017-04-24Merge pull request #909 from sandrine-bailleux-arm/sb/xlat-lib-misc-improvementsdavidcunado-arm
xlat lib: Use mmap_attr_t type consistently
2017-04-21Merge pull request #910 from dp-arm/dp/AArch32-juno-portdavidcunado-arm
Add AArch32 support for Juno
2017-04-20AArch32: Add SP_MIN support for JUNOYatharth Kochar
This patch adds support for SP_MIN on JUNO platform. The changes include addition of AArch32 assembly files, JUNO specific SP_MIN make file and miscellaneous changes in ARM platform files to enable support for SP_MIN. Change-Id: Id1303f422fc9b98b9362c757b1a4225a16fffc0b Signed-off-by: Yatharth Kochar <yatharth.kochar@arm.com> Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-04-20Changes to support execution in AArch32 state for JUNOYatharth Kochar
Following steps are required to boot JUNO in AArch32 state: 1> BL1, in AArch64 state, loads BL2. 2> BL2, in AArch64 state, initializes DDR. Loads SP_MIN & BL33 (AArch32 executable)images. Calls RUN_IMAGE SMC to go back to BL1. 3> BL1 writes AArch32 executable opcodes, to load and branch at the entrypoint address of SP_MIN, at HI-VECTOR address and then request for warm reset in AArch32 state using RMR_EL3. This patch makes following changes to facilitate above steps: * Added assembly function to carry out step 3 above. * Added region in TZC that enables Secure access to the HI-VECTOR(0xFFFF0000) address space. * AArch32 image descriptor is used, in BL2, to load SP_MIN and BL33 AArch32 executable images. A new flag `JUNO_AARCH32_EL3_RUNTIME` is introduced that controls above changes. By default this flag is disabled. NOTE: BL1 and BL2 are not supported in AArch32 state for JUNO. Change-Id: I091d56a0e6d36663e6d9d2bb53c92c672195d1ec Signed-off-by: Yatharth Kochar <yatharth.kochar@arm.com> Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-04-20AArch32: Add support for ARM Cortex-A53/57/72 MPCore ProcessorYatharth Kochar
This patch adds AArch32 state support for ARM Cortex-A53, Cortex-A57 and Cortex-A72 MPCore Processor in the CPU specific operations framework. NOTE: CPU errata handling code is not present in this patch. Change-Id: I01eb3e028e40dde37565707ebc99e06e7a0c113d Signed-off-by: Yatharth Kochar <yatharth.kochar@arm.com> Signed-off-by: dp-arm <dimitris.papastamos@arm.com>
2017-04-20xlat lib: Use mmap_attr_t type consistentlySandrine Bailleux
This patch modifies both versions of the translation table library to use the mmap_attr_t type consistently wherever it is manipulating MT_* attributes variables. It used to use mmap_attr_t or plain integer types interchangeably, which compiles fine because an enumeration type can be silently converted to an integer, but which is semantically incorrect. This patch removes this assumption by using the abstract type 'mmap_attr_t' all the time. Change-Id: Id1f099025d2cb962b275bb7e39ad2c4dbb4e366c Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
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