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2018-04-15plat: marvell: Enable CA72 Errata 859971 handlingKonstantin Porotchkin
Enable handling of CA72 Errata 859971 on A8K platform. Change-Id: I7fade6519c630c2f3840ac7c3f1fc5b7416eba05 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/52579 Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2018-04-15Disable workaround for CVE-2017-5715 on unaffected platformsDimitris Papastamos
Change-Id: Ib67b841ab621ca1ace3280e44cf3e1d83052cb73 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/52572 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2018-01-28fix: a8k: svc: Fix the voltage settings for a7040 @ 1600MHzKonstantin Porotchkin
For A7040 running at 1600MHz the SVC workpoint should not be changed. Change-Id: Ied44e34ffd71989b5a309f07ae29ba5a52d497ff Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/49627 Reviewed-by: Ilan Dahan <iland@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Igor Shapiro <ishapiro@marvell.com>
2017-12-18marvell: svc: Update the SVC algorithm to v0.10Konstantin Porotchkin
Update SVC flow according to definitions v0.10 Change-Id: I36934e915554401a203f6617bf25da1e0419909f Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/47625 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com>
2017-11-27marvell: svc: Update the SVC algorithm to v0.8Konstantin Porotchkin
Add parity check for WP efuse values according to SVC definition version 0.8 Change-Id: I5221975bbc2ec02cf07b2ca68b5a4f36aa6087a9 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/46753 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Ilan Dahan <iland@marvell.com> Reviewed-by: Neta Zur Hershkovits <neta@marvell.com>
2017-11-23plat/marvell: a70x0: configure Direct Mode window for SPI flashMarcin Wojtas
In order to be able to support UEFI variables, direct mode access to the SPI flash is required. The variables will be placed at 4MB - 256KB offset. For this purpose at offset 0xf9000000 configure new window pointing to the CP0 SPI1 CS0 device. Change-Id: I61402b8741a07cf12e35050de48bbf39baeb4cbb Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/46713 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-11-23plat/marvell: a80x0: configure Direct Mode window for SPI flashMarcin Wojtas
In order to be able to support UEFI variables, direct mode access to the SPI flash is required. The variables will be placed at 4MB - 256KB offset. For this purpose at offset 0xf9000000 configure new window pointing to the CP1 SPI1 CS0 device. Because the platform supports maximum amount of 6 IO windows, existing window for CP1 PCIE0 was extended to cover the SPI area as well. Change-Id: I5ef5eb4ac95f86d78a4af7f474127a04dd083254 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/46712 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-11-23plat/marvell: a80x0_mcbin: configure Direct Mode window for SPI flashMarcin Wojtas
In order to be able to support UEFI variables, direct mode access to the SPI flash is required. The variables will be placed at 4MB - 256KB offset. For this purpose at offset 0xf9000000 configure new window pointing to the CP1 SPI1 CS0 device. Because the platform supports maximum amount of 6 IO windows, CP1 PCIE0 window had to be be extended to cover the SPI area as well. Change-Id: I125ebfb5259549e2ea0d0d2c76296e4167c6ca45 Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/46711 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-11-22pm: mvebu: remove operation before jumping back to ATFVictor Gu
Before jumping back DDR to execute ATF during system resume, need to run cache maintenance operations. This patch removes current code, another patch will re-write the code to be more generic. Change-Id: I6059525abfe04c1a6c80486a3483b8c671f48270 Signed-off-by: Victor Gu <xigu@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/46246 Reviewed-by: Neta Zur Hershkovits <neta@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/46631
2017-11-21plat: marvell: a8k: make SCP_BL2 image mandatory for a8k familyGrzegorz Jaszczyk
Force build with SCP_BL2 on a80x0 boards. This enforcement ensures that the required service CPU executable is always incluided in the final system flash image. Change-Id: I6efe32ec20ab5e193e56273b016a76f646d2c4ee Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/46209 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Yoav Gvili <ygvili@marvell.com>
2017-10-03a8k: svc: Update the SVC flow to version 0.6Konstantin Porotchkin
Update the SVC flow according to the version 0.6 specification. Change-Id: I2af1e14a407a01badb965b2394986d86370f4499 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/44997 Reviewed-by: Neta Zur Hershkovits <neta@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2017-09-07plat: marvell: a8k: add missing check for scp bl2 addrNeta Zur
Commit "plat: marvell: a8k: allow to load scp_bl2 firmware that doesn't contain PM FW" add scp_bl2 related checks done at runtime. Nevertheless it occurred that during build with debugs enabled and SCP_BL2 undefined, the build error was triggered. Adding preprocessor checks for SCP_BL2_BASE fixes that issue. Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Change-Id: I8aa127ef389c7549035b43cb63e67d83edb831c1 Signed-off-by: Neta Zur <neta@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43973 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Omri Itach <omrii@marvell.com>
2017-08-31pcie: a8040_ocp: pcie stabilization configurationsIgal Liberman
This patch optimizes the pcie comphy receiver and transmitter configuration. It includes the following optimizations: RX - Force FFE constant values instead of trained values TX - Increase the full swing value and update all presets (p0 - p10) accordingly Change-Id: I6e48d543eb343b453ed804d9b48bcfec86c30225 Signed-off-by: Ofir Fedida <ofedida@marvell.com> Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43426 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-08-31plat: marvell: a8k: allow to load scp_bl2 firmware that doesn't contain PM FWGrzegorz Jaszczyk
Hitherto if the SCP_BL2 path was defined, Marvell platform code (plat/marvell/a8k/common/a8k_common.mk via plat/marvell/a8k/common/mss/mss_common.mk) was defining SCP_IMAGE, which was used in power management related code(mainly in plat_pm.c) for choosing proper PM related code. Therefore there were two different situation: 1) The SCP_BL2 was not defined, then the ATF used its own PM related code 2) The SCP_BL2 was defined and ATF assumed that during SCP_BL2 stage the firmware with PM support was loaded into MSS AP CM3 and PM was managed mainly via IPC messages between ATF and MSS AP CM3 firmware. Now in some cases the firmware for MSS AP CM3 does not support PM therefore it causes some issue: during Linux boot only one CPU was brought out from reset and all secondary CPUs remained down. After this change the Marvell platform code can verify if the firmware loaded to MSS AP CM3 has PM support at runtime and does not make assumption basing on SCP_BL2 definition anymore. In other words all preprocessor condition of SCP_IMAGE was replaced by runtime condition that allows to really distinguish between situation where we are running PM firmware or not, so three different scenario are possible and handled correctly now: 1) The SCP_BL2 is not used at all then the ATF uses its own PM related code. 2) The SCP_BL2 contains firmware for MSS AP CM3 and it supports PM, then ATF manage PM mainly via IPC messages between ATF and MSS AP CM3 firmware. 3) The SCP_BL2 does not contain firmware for MSS AP CM3 or it contain firmware that does not support PM, then ATF uses its own PM related code. Change-Id: I26da4db968966cb5e61714ff192fb645a3a57875 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43573 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-by: Omri Itach <omrii@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com>
2017-08-30fix: llc: ocp, pcac: temporarily force disable of LLCOmri Itach
Force disable of LLC for A8k-OCP and A7k-PCAC boards, regardless of LLC_DISABLE compilation flag. This is due to an issue observed while running iperf with smartNIC End Poind driver/application, while LLC is enabled. As a temporary workaround, until issue is solved, we disable LLC. Change-Id: Ie8362dafcf227112a8c48e865f74bfe69c8598d5 Signed-off-by: Omri Itach <omrii@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/42127 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-08-29plat: a70x0_amc: Increase the PCIe address rangeKonstantin Porotchkin
Increase the PCIe address range for A7K AMC board to 96MB as required by CPSS Linux drivers. Change-Id: I78a762eb91a7454c9c86f1ded513b95582583768 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43448 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Hanna Hawa <hannah@marvell.com> Reviewed-by: Victor Gu <xigu@marvell.com>
2017-08-29mvebu: io_win: move GCR offset to be defined in platformHanna Hawa
As part of AP810 preparation and driver changes, move GCR offset to be defined in platform file and not in IO_WIN driver as AP810 & AP806 have different GCR offset. No functional changes introduced by this patch. Change-Id: Iadb4d7294909fa764bf26aa6b7442bb8a33a9c53 Signed-off-by: Hanna Hawa <hannah@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43469 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com>
2017-08-28fix: a8k: Correct bad IRQ mapping macrosKonstantin Porotchkin
Corect wrongly defined PLAT_MARVELL_G0_IRQS and PLAT_MARVELL_G1S_IRQS macros in A8K platform common files Change-Id: Ic538f448188cbfb86703074658e7b9b0b6b7debf Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43453 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Hanna Hawa <hannah@marvell.com>
2017-08-28pm: a8k: change the GPIO toggling sequenceVictor Gu
In order to support multiple times of power off the system by PMIC, the GPIO toggling sequence for Armada80x0 board should be "1-0-1-0-1-0-1" instead of "1-0-1-0-1". Change-Id: Ia03330e7ff8e115ea7b841a8a10f7641f4cc7b65 Signed-off-by: Victor Gu <xigu@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43437 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-08-28plat: mvebu: add check of north bridge number to marvell_check_mpidr functionHanna Hawa
Part of AP810 preparation and driver changes, add check of north bridge number to marvell_check_mpidr function. For Armada-8k family and Armada-37xx family, no functional change, they have single north bridge die. Armada-8k-plus family can contain 4 north bridge dies, so need to check the value of the die number. Change-Id: I1f3b9fa46e6b099f83024e411828f586bb8927c2 Signed-off-by: Hanna Hawa <hannah@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43400 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Hua Jing <jinghua@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-08-28plat: mvebu: add die parameter for psci_arch_init functionHanna Hawa
As part of AP810 preparation and driver changes, add die parameter for psci_arch_init function. For Armada-8k family and Armada-37xx family, no functional change, they have single north bridge die (die #0), add die 0 for all psci_arch_init functions. Armada-8k-plus family can contain 4 north bridge die, so need to call psci_arch_init with different die number. No functional changes introduced by this patch. Change-Id: I5e334ce5bb75103236c322b389a0bc5e216fbe2a Signed-off-by: Hanna Hawa <hannah@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43399 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Hua Jing <jinghua@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-08-27mvebu: pm: a8k: move armada-8k functions to be staticHanna Hawa
Change-Id: Ib5a70cf178f055a1ba506ba77592d452e9730321 Signed-off-by: Hanna Hawa <hannah@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43394 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-08-27mvebu: io-win: add function to get the target ID of GCRHanna Hawa
Part of AP810 preparation and driver changes, may some north bridge have different target IDs for the GCR. Change-Id: I06221baf00f2f69d40382e27d49fe166ab43de4e Signed-off-by: Hanna Hawa <hannah@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43402 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2017-08-27mvebu: ccu: add function to get the target ID of GCRHanna Hawa
Part of AP810 preparation and driver changes, may some north bridge have different target IDs for the GCR. Change-Id: I4c25baf5414c016374c61ec979cf1c40fa6cde4c Signed-off-by: Hanna Hawa <hannah@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43401 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-08-27thermal: a8k: add thermal sensor driverVictor Axelrod
This patch adds thermal sensor driver for a8k external thermal sensor. The driver was ported from u-boot 2015.01 (mvebu_ext_thermal_28nm.c). Its functionality was reduced to one sensor only (a few are available on ap). The api provides with thermal sensor's configuration get, thermal sensor's init, and temperature read functions. Change-Id: I0fd456b95d115b23e575fd6c6e09ac88ff73c3da Signed-off-by: Victor Axelrod <victora@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43424 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-08-27mvebu: llc: add support for multiple AP for LLC driverHanna Hawa
Part of AP810 preparation and driver changes, change LLC driver to get the number of AP it should initialize, to get the AP base address of LLC. No functional changes introduced by this patch. Change-Id: Ia6b1d4c0de4c6ded11f964c87163d8df45856bbc Signed-off-by: Hanna Hawa <hannah@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43398 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-08-27mvebu: io-win: add parameter for ccu function to set AP numberHanna Hawa
Part of AP810 preparation and driver changes, change IO_WIN driver to get the number of AP it should initialize, to get the AP base address and window map. No functional changes introduced by this patch. Change-Id: I20522ebcdd9bcea4691a4d65cb839bcb5d46f4e6 Signed-off-by: Hanna Hawa <hannah@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43397 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2017-08-27mvebu: ccu: add parameter for ccu function to set AP numberHanna Hawa
Part of AP810 preparation and driver changes, change CCU driver to get the number of AP it should initialize, to get the AP base address and window map. No functional changes introduced by this patch. Change-Id: I6f221b6da68a11e6ff93e0997eb633c12309723d Signed-off-by: Hanna Hawa <hannah@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43396 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2017-08-27platform: a8k: update .mk file to be more genericHanna Hawa
Update path of common platform files to be more generic Change-Id: I63467c23da8deb60c0d347a38f37965e8f6bd20d Signed-off-by: Hanna Hawa <hannah@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43395 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2017-08-27mvebu: pm: a8k: use __func__ instead of function nameHanna Hawa
Change-Id: I146037d95b5790e4627ed330c487dce6913d9368 Signed-off-by: Hanna Hawa <hannah@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43393 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-08-27fix: mvebu: pm: a8k: update cpu unreset definesHanna Hawa
Change-Id: I3034e01025aad9d343194b9419b840e6d495068a Signed-off-by: Hanna Hawa <hannah@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43392 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-08-27fix: mvebu: pm: a8k: remove duplicated define of cores per clusterHanna Hawa
Change-Id: Ieca22c49c02d21bfe15dad4cfcfbbb9f07c46171 Signed-off-by: Hanna Hawa <hannah@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43391 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-08-27fix: mvebu: a8k: remove duplicated define of AP MPP registerHanna Hawa
Change-Id: Ia553d13a2e2d53dc06224bee5c83af74bdb735d5 Signed-off-by: Hanna Hawa <hannah@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43390 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2017-08-21fix: ap806: io-win: change the name of RFU window to be IO-WINHanna Hawa
The name of RFU used in old AP806-Z SoC. This patch update the used name to be IO-WIN, the correct unit name in AP806-Ax, and AP810-A0 Change-Id: I9fc12e25c34aa97aa09a7b9b21837e71092058d9 Signed-off-by: Hanna Hawa <hannah@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43184 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-08-16pm: a8k: flush and disable LLC before power offKonstantin Porotchkin
The content of LLC (shared L3 cache) must be flushed before CPU goes off the power. The llc_disable() function flushes and disables the LLC, so all its current content does not lost. Change-Id: I677b2d8bb79ae2fe8f19e8c697ca9daf98bb42fc Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/42553 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Victor Gu <xigu@marvell.com>
2017-08-16pm: a8k: support GPIO toggling to power off system by PMICVictor Gu
A specific board configuration is added for Armada80x0 board to power off the PMIC by GPIO. Change-Id: Id4dc5087fb9e23ad0312626028df52c049402e08 Signed-off-by: Victor Gu <xigu@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43050 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-08-16pm: a8k: enable DDR self-refresh during system suspendVictor Gu
During system suspend, the DDR self-refresh should be enabled to keep the DRAM data while the SoC or the CPU processor are powered off. This patch implements the DDR self-refresh for Armada 8k DDR controller and calls it during system suspend. Change-Id: I1653c5516e4285133b96df051332252f399463a9 Signed-off-by: Victor Gu <xigu@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43048 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-08-16pm: a8k: add generic system power off supportVictor Gu
A generic data structure is defined to implement the system power off. Currently only power off by GPIO is supported. Multiple GPIOs are supported to notify the PMIC to power off the system, also the sequence and delay can be configured. The GPIO power off flow is divided into prepare and trigger stages, because need to issue DDR self-refresh between them. After DDR self-refresh is enabled, no DRAM access is allowed, thus it is not allowed to access DRAM in GPIO trigger routine. Change-Id: I72066dff362030fef47c0e7ad645282bd3ede026 Signed-off-by: Victor Gu <xigu@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43047 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-08-16pm: a8k: adjust the pm codeVictor Gu
This patch improves the PM driver code a bit: 1. move the plat_marvell_system_reset() routine be adjacent to a8k_system_reset() 2. move the suspend relevant routines be adjacent to a8k_pwr_domain_suspend 3. remove routine and define them in a8k_pwr_domain_suspend Change-Id: I591c56a3efea09e1da7ca486c918f5ad6f76f082 Signed-off-by: Victor Gu <xigu@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/43044 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-08-14fix: a80x0_mcbin: disable unsupported u-boot recovery buttonChristine Gharzuzi
A80x0-MCBIN board doesn't support U-Boot recovery button. this button is triggering GPIO-in signal, and used to instruct ATF to boot secondery U-Boot image from flash, for recovery in case first U-Boot isn't functional. Change-Id: Ieae328d1284f3586cec84cc0126ca18cca3c63c9 Signed-off-by: Christine Gharzuzi <chrisg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/42993 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-08-13makefile: aro: add define flag for ARO.Christine Gharzuzi
Add define flag for ARO and set it by default to 1. No functional change Change-Id: Id5ae19f8fa9d1096b80615fffa9ccec1eb8f4f9c Signed-off-by: Christine Gharzuzi <chrisg@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/42866 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-by: Hanna Hawa <hannah@marvell.com> Tested-by: iSoC Platform CI <ykjenk@marvell.com>
2017-08-10plat: marvell: a8k: add support for scp_bl2 concatenated imageGrzegorz Jaszczyk
The Armada 8K has 5 service CPUs and Armada 7K has 3. Therefore it was required to provide a method for loading firmware to all of the service CPUs. To achieve that, the scp_bl2 image in fact is file containing up to 5 concatenated firmwares. This patch allows to recognize new format of scp_bl2 image, interpret it correctly, restore built-in images and load particular image to appropriate service CPU pointed in image header. The new scp_bl2 file format is: 0x0: File header (magic, nr_of_images) 0x8: Image header 0 (type, length, version) 0x14: Image header 1 (type, length, version) ... 0xyy Build-in image described by image header 0 0xzz Build-in image described by image header 1 The possible images that can be built in scp_bl2 image are firmwares for: mss ap cm3, mss cp0 cm3, mss cp1 cm3, mg cp0 cm3 and mg cp1 cm3. Thanks to the file format and headers for each file, ATF platform code is able to recognise how many files are built-in and what is their destination (to which co-processor they need to be loaded). Change-Id: I07719eb10f43a028ebea4713ccf149b86db81ec4 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/42635 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: Kostya Porotchkin <kostap@marvell.com>
2017-08-10plat: marvell: a8k: add ccu configuration for cp0 and cp1 in bl2 stageGrzegorz Jaszczyk
Since the scp_bl2 image can contain firmware for cp1 and cp0 coprocessors, the access to cp0 and cp1 need to be provided. More precisely it is required to: - get the information about device id which is stored in cp0 registers (to distinguish between cases where we have cp0 and cp1 or standalone cp0) - get the access to cp which is needed for loading fw for cp0/cp1 coprocessors Change-Id: I9cd92778aed5c2f66365538becbfa591a116c602 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/42634 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-08-07plat: a3700: add BL32 support for armada3700wangwen
This patch adds BL32(Security OS) support for armada3700. 1) Security OS needs 16M RAM resource, so changed PLAT_MARVELL_TRUSTED_DRAM_BASE starts from 0x4400000 and reserved 16M for it. Change-Id: Ifc0f797d4aafbc838e48d7e7487adb9065ea029b Signed-off-by: wangwen <wangwen@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/40090 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-08-07drivers: mochi: cp110: Enable I2C for CP in debug modeKonstantin Porotchkin
Add SW WA for ERRATA FE-6163379 (STORM-1443). Enable i2c when CP i2c init is selected by SAR. Change-Id: Ifd31e342028e31b3c58393a5beef6107ae39e452 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/42419 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Omri Itach <omrii@marvell.com> Reviewed-by: Igal Liberman <igall@marvell.com>
2017-08-06pm: a8k: Remove code duplicates from the suspend to RAM codeKonstantin Porotchkin
Remove redundant calls to psci_arch_init and gicv2_cpuif_enable from a8k_pwr_domain_suspend_finish. Both these functions are called from within marvell_bl31_platform_setup Change-Id: I4f68a2970694be92e12292ff33b96322a516bf2f Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/42552 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Victor Gu <xigu@marvell.com>
2017-08-03fix: a70x0_pcac: disable unsupported u-boot recovery buttonOmri Itach
A70x0-PCAC board doesn't support U-Boot recovery button. this button is triggering GPIO-in signal, and used to instruct ATF to boot secondery U-Boot image from flash, for recovery in case first U-Boot isn't functional. on A7k-PCAC this MPP is part of the RGMII mpp's, and once RGMII port was connected, it triggered by mistake this GPIO recovery signal, and this affected boot from UART which eventually didn't work. Change-Id: Icb5e66838358d6d89765a683d19aca02bb443f04 Signed-off-by: Omri Itach <omrii@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/42546 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-08-01marvell: ble: svc: fix the frequency mode macroKonstantin Porotchkin
Fix macro SAR_CLOCK_FREQ_MODE that used bitfiled offset instead of mask Change-Id: I5f3490860af49b01720867ee62772b767c1b78b9 Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/42459 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Omri Itach <omrii@marvell.com>
2017-08-01pm: a8k: fix compilation error when PM_TRACE_ENABLE is definedIgal Liberman
Move plat_my_core_pos into the trace define. Change-Id: I615277c0141e4f7e9c1729c6ec82f035f9533783 Signed-off-by: Igal Liberman <igall@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/41861 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
2017-08-01plat: a8k: add BL32 support for armada7k/8kZhoujie Wu
This patch adds BL32(security OS) support for armada7k/8k. 1) Since security OS needs 16M RAM resource, so changed PLAT_MARVELL_TRUSTED_DRAM_BASE starts from 0x4400000 and reserve 16M for it. 2) add BL32_BASE and bl2_plat_get_bl32_meminfo, also added BL32 into io storage for BL2 to get the BL32 mem information and load BL32 to the expected memory for execution. Change-Id: Ic9ab377ce4413048031005e7b802585439321cc9 Signed-off-by: Zhoujie Wu <zjwu@marvell.com> Reviewed-on: http://vgitil04.il.marvell.com:8080/38640 Tested-by: iSoC Platform CI <ykjenk@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com>
generated by cgit (git 2.34.1) at 2024-06-19 13:33:45 +0000