From 07aa2d08e601409eb1e3f9f717bb13a9655fbd70 Mon Sep 17 00:00:00 2001 From: Ofir Fedida Date: Mon, 17 Jul 2017 10:40:26 +0300 Subject: a80x0: add support for Armada 8k OCP board this patch introduces support for new Armada 8k OCP board. - added new platform a80x0_ocp - enabled PCIe EP driver with delay_cfg=1 to allow later EP driver in Linux. - ddr configuration: 1CS 8Gb x5 Samsung devices K4A8G165WB BCRC speed bin 2400S device width x16 verified interfaces: 2 * 10G ethernet ports SPI MMC UART Change-Id: Id723b4a7b4b2f9c590a56417b9ceebe22d5727db Signed-off-by: Ofir Fedida Reviewed-on: http://vgitil04.il.marvell.com:8080/41853 Tested-by: iSoC Platform CI Reviewed-by: Kostya Porotchkin --- Makefile | 3 + plat/marvell/a8k/a80x0_ocp/board/dram_port.c | 108 ++++++++++++ .../a8k/a80x0_ocp/board/marvell_plat_config.c | 193 +++++++++++++++++++++ plat/marvell/a8k/a80x0_ocp/plat_def.h | 42 +++++ plat/marvell/a8k/a80x0_ocp/platform.mk | 35 ++++ 5 files changed, 381 insertions(+) create mode 100644 plat/marvell/a8k/a80x0_ocp/board/dram_port.c create mode 100644 plat/marvell/a8k/a80x0_ocp/board/marvell_plat_config.c create mode 100644 plat/marvell/a8k/a80x0_ocp/plat_def.h create mode 100644 plat/marvell/a8k/a80x0_ocp/platform.mk diff --git a/Makefile b/Makefile index ed91b23c..762a65ac 100644 --- a/Makefile +++ b/Makefile @@ -131,6 +131,9 @@ PCI_EP_SUPPORT := 1 else PCI_EP_SUPPORT := 0 endif +ifeq ($(PLAT),$(filter $(PLAT),a80x0_ocp)) +PCI_EP_SUPPORT := 1 +endif # Marvell images BOOT_IMAGE := boot-image.bin diff --git a/plat/marvell/a8k/a80x0_ocp/board/dram_port.c b/plat/marvell/a8k/a80x0_ocp/board/dram_port.c new file mode 100644 index 00000000..1e2a8011 --- /dev/null +++ b/plat/marvell/a8k/a80x0_ocp/board/dram_port.c @@ -0,0 +1,108 @@ +/* + * *************************************************************************** + * Copyright (C) 2017 SolidRun ltd. + * *************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of Marvell nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *************************************************************************** + */ + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +struct dram_config dram_cfg; + +/* + * This struct provides the DRAM training code with + * the appropriate board DRAM configuration + */ +static struct mv_ddr_topology_map board_topology_map = { + /* Board with 1CS 8Gb x5 devices of Samsung K4A8G165WB BCRC */ + DEBUG_LEVEL_ERROR, + 0x1, /* active interfaces */ + /* cs_mask, mirror, dqs_swap, ck_swap X subphys */ + { { { {0x1, 0x0, 0, 0}, /* FIXME: change the cs mask for all 64 bit */ + {0x1, 0x0, 0, 0}, + {0x1, 0x0, 0, 0}, + {0x1, 0x0, 0, 0}, + {0x1, 0x0, 0, 0}, + {0x1, 0x0, 0, 0}, + {0x1, 0x0, 0, 0}, + {0x1, 0x0, 0, 0}, + {0x1, 0x0, 0, 0} }, + SPEED_BIN_DDR_2400S, /* speed_bin */ + MV_DDR_DEV_WIDTH_16BIT, /* sdram device width */ + MV_DDR_DIE_CAP_8GBIT, /* die capacity */ + DDR_FREQ_SAR, /* frequency */ + 0, 0, /* cas_l, cas_wl */ + MV_DDR_TEMP_LOW} }, /* temperature */ + MV_DDR_64BIT_ECC_PUP8_BUS_MASK, /* subphys mask */ + MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ + { {0} }, /* raw spd data */ + {0} /* timing parameters */ +}; + +struct mv_ddr_topology_map *mv_ddr_topology_map_get(void) +{ + /* Return the board topology as defined in the board code */ + return &board_topology_map; +} + +struct dram_config *mv_ddr_dram_config_get(void) +{ + /* Return dram configuration as defined in the board code */ + return &dram_cfg; +} + +/* + * This function may modify the default DRAM parameters + * based on information recieved from SPD or bootloader + * configuration located on non volatile storage + */ +int update_dram_info(struct dram_config *cfg) +{ + return 0; +} + +void *plat_get_dram_data(void) +{ + /* Update DRAM for dynamic platforms */ + update_dram_info(&dram_cfg); + + return &dram_cfg; +} diff --git a/plat/marvell/a8k/a80x0_ocp/board/marvell_plat_config.c b/plat/marvell/a8k/a80x0_ocp/board/marvell_plat_config.c new file mode 100644 index 00000000..0eb72030 --- /dev/null +++ b/plat/marvell/a8k/a80x0_ocp/board/marvell_plat_config.c @@ -0,0 +1,193 @@ +/* + * *************************************************************************** + * Copyright (C) 2016 Marvell International Ltd. + * *************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of Marvell nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *************************************************************************** + */ + +#include +/* + * If bootrom is currently at BLE there's no need to include the memory + * maps structure at this point + */ +#include +#ifndef IMAGE_BLE + +/******************************************************************************* + * AMB Configuration + ******************************************************************************/ +struct amb_win *amb_memory_map; + +uintptr_t marvell_get_amb_reg_offs(int cp_index) +{ + return MVEBU_AMB_ADEC_BASE(cp_index); +} + +int marvell_get_amb_memory_map(struct amb_win **win, uint32_t *size) +{ + *win = amb_memory_map; + if (*win == NULL) + *size = 0; + else + *size = sizeof(amb_memory_map)/sizeof(struct amb_win); + + return 0; +} + +/******************************************************************************* + * RFU Configuration + ******************************************************************************/ + +struct rfu_win rfu_memory_map[] = { + /* CP1 (MCI0) internal regs */ + {0x0, 0xf4000000, 0x0, 0x2000000, MCI_0_TID}, + /* MCI 0 indirect window */ + {0x0, MVEBU_MCI_REG_BASE_REMAP(0), 0x0, 0x100000, MCI_0_TID}, + /* MCI 1 indirect window */ + {0x0, MVEBU_MCI_REG_BASE_REMAP(1), 0x0, 0x100000, MCI_1_TID}, +}; + +uintptr_t marvell_get_rfu_reg_offs(void) +{ + return MVEBU_RFU_BASE; +} + +int marvell_get_rfu_memory_map(struct rfu_win **win, uint32_t *size) +{ + *win = rfu_memory_map; + if (*win == NULL) + *size = 0; + else + *size = sizeof(rfu_memory_map)/sizeof(struct rfu_win); + + return 0; +} + +/******************************************************************************* + * IOB Configuration + ******************************************************************************/ +#define MARVELL_IOB_MAX_WIN 16 + +struct iob_win iob_memory_map_cp0[] = { + /* CP1 */ + /* PEX0_X4 window */ + {0x80, 0x00000000, 0x80, 0x0000000, PEX0_TID} +}; + +uintptr_t marvell_get_iob_reg_offs(int cp_index) +{ + return MVEBU_IOB_BASE(cp_index); +} + +int marvell_get_iob_max_win(void) +{ + return MARVELL_IOB_MAX_WIN; +} + +int marvell_get_iob_memory_map(struct iob_win **win, + uint32_t *size, int cp_index) +{ + switch (cp_index) { + case 0: + *win = iob_memory_map_cp0; + *size = sizeof(iob_memory_map_cp0)/sizeof(struct iob_win); + return 0; + case 1: + *size = 0; + *win = 0; + return 0; + default: + *size = 0; + *win = 0; + return 1; + } +} + +/******************************************************************************* + * CCU Configuration + ******************************************************************************/ +#define MARVELL_CCU_MAX_WIN 8 + +struct ccu_win ccu_memory_map[] = { + {0x0, 0xf2000000, 0x0, 0xe000000, IO_0_TID}, /* IO window */ + {0x80, 0x00000000, 0x80, 0x0000000, IO_0_TID}, /* IO window */ +}; + +uintptr_t marvell_get_ccu_reg_offs(void) +{ + return MVEBU_CCU_BASE; +} + +int marvell_get_ccu_max_win(void) +{ + return MARVELL_CCU_MAX_WIN; +} + +int marvell_get_ccu_memory_map(struct ccu_win **win, uint32_t *size) +{ + *win = ccu_memory_map; + *size = sizeof(ccu_memory_map)/sizeof(struct ccu_win); + + return 0; +} +/* In reference to #ifndef IMAGE_BLE, this part is used for BLE only. */ +#else +/******************************************************************************* + * PCIe Configuration + ******************************************************************************/ +struct pci_hw_cfg ocp_pci_hw_cfg = { + .delay_cfg = 1, + .master_en = 1, + .lane_width = 4, + .lane_ids = {0, 1, 2, 3}, + .clk_src = 0, + .clk_out = 0, /* clk is not output */ + .is_end_point = 1, + .mac_base = MVEBU_PCIE_X4_MAC_BASE(0), + .comphy_base = MVEBU_COMPHY_BASE(0), + .hpipe_base = MVEBU_HPIPE_BASE(0), + .dfx_base = MVEBU_CP_DFX_BASE(0), +}; + +struct pci_hw_cfg *plat_get_pcie_hw_data(void) +{ + return &ocp_pci_hw_cfg; +} + +/******************************************************************************* + * SKIP IMAGE Configuration + ******************************************************************************/ + +void *plat_get_skip_image_data(void) +{ + /* Return the skip_image configurations */ + return NULL; +} +#endif diff --git a/plat/marvell/a8k/a80x0_ocp/plat_def.h b/plat/marvell/a8k/a80x0_ocp/plat_def.h new file mode 100644 index 00000000..03a59a9b --- /dev/null +++ b/plat/marvell/a8k/a80x0_ocp/plat_def.h @@ -0,0 +1,42 @@ +/* + * *************************************************************************** + * Copyright (C) 2017 Marvell International Ltd. + * *************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of Marvell nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *************************************************************************** + */ + +#ifndef __MVEBU_DEF_H__ +#define __MVEBU_DEF_H__ + +#include + +#define CP_COUNT 2 /* A80x0 has both CP0 & CP1 */ + +#endif /* __MVEBU_DEF_H__ */ diff --git a/plat/marvell/a8k/a80x0_ocp/platform.mk b/plat/marvell/a8k/a80x0_ocp/platform.mk new file mode 100644 index 00000000..2646ba03 --- /dev/null +++ b/plat/marvell/a8k/a80x0_ocp/platform.mk @@ -0,0 +1,35 @@ +# +# *************************************************************************** +# Copyright (C) 2017 Marvell International Ltd. +# *************************************************************************** +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are met: +# +# Redistributions of source code must retain the above copyright notice, this +# list of conditions and the following disclaimer. +# +# Redistributions in binary form must reproduce the above copyright notice, +# this list of conditions and the following disclaimer in the documentation +# and/or other materials provided with the distribution. +# +# Neither the name of Marvell nor the names of its contributors may be used +# to endorse or promote products derived from this software without specific +# prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, +# OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# + +include plat/marvell/a8k/common/a8k_common.mk + +include plat/marvell/common/marvell_common.mk -- cgit