From 3217eeaf17a8ed652317c4f0151a1c60fb815d95 Mon Sep 17 00:00:00 2001 From: Igal Liberman Date: Tue, 28 Aug 2018 18:15:08 +0300 Subject: mvebu: cp110: fix GEN3 SATA link Currently when we connect SATA GEN3 disk, GEN2 link is established. This patch updates 2 comphy parameters, g3_emph and allign_90, fixing this issue. Change-Id: I4e39d180cb8b401490643ddab0fc5d6442c1c220 Signed-off-by: Igal Liberman Reviewed-on: http://vgitil04.il.marvell.com:8080/59563 Reviewed-by: Grzegorz Jaszczyk Tested-by: iSoC Platform CI Reviewed-by: Kostya Porotchkin (cherry picked from commit 800dfa534a578150c903501f44b56009c74b7e49) Reviewed-on: http://vgitil04.il.marvell.com:8080/59594 --- drivers/marvell/comphy/phy-default-porting-layer.h | 4 ++-- plat/marvell/a8k/a80x0/board/phy-porting-layer.h | 16 ++++++++-------- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/marvell/comphy/phy-default-porting-layer.h b/drivers/marvell/comphy/phy-default-porting-layer.h index 6999b5cb..b88b4535 100644 --- a/drivers/marvell/comphy/phy-default-porting-layer.h +++ b/drivers/marvell/comphy/phy-default-porting-layer.h @@ -26,13 +26,13 @@ static const struct xfi_params xfi_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR static const struct sata_params sata_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = { [0 ... AP_NUM-1][0 ... CP_NUM-1][0 ... MAX_LANE_NR-1] = { .g1_amp = 0x8, .g2_amp = 0xa, .g3_amp = 0x1e, - .g1_emph = 0x1, .g2_emph = 0x2, .g3_emph = 0x6, + .g1_emph = 0x1, .g2_emph = 0x2, .g3_emph = 0xe, .g1_emph_en = 0x1, .g2_emph_en = 0x1, .g3_emph_en = 0x1, .g1_tx_amp_adj = 0x1, .g2_tx_amp_adj = 0x1, .g3_tx_amp_adj = 0x1, .g1_tx_emph_en = 0x0, .g2_tx_emph_en = 0x0, .g3_tx_emph_en = 0x0, .g1_tx_emph = 0x1, .g2_tx_emph = 0x1, .g3_tx_emph = 0x1, .g3_dfe_res = 0x1, .g3_ffe_res_sel = 0x4, .g3_ffe_cap_sel = 0xf, - .allign_90 = 0x1c, + .allign_90 = 0x61, .g1_rx_selmuff = 0x3, .g2_rx_selmuff = 0x3, .g3_rx_selmuff = 0x3, .g1_rx_selmufi = 0x0, .g2_rx_selmufi = 0x0, .g3_rx_selmufi = 0x3, .g1_rx_selmupf = 0x1, .g2_rx_selmupf = 0x1, .g3_rx_selmupf = 0x2, diff --git a/plat/marvell/a8k/a80x0/board/phy-porting-layer.h b/plat/marvell/a8k/a80x0/board/phy-porting-layer.h index 08a0f150..6e17f47a 100644 --- a/plat/marvell/a8k/a80x0/board/phy-porting-layer.h +++ b/plat/marvell/a8k/a80x0/board/phy-porting-layer.h @@ -54,13 +54,13 @@ static const struct sata_params sata_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_ { { 0 }, /* Comphy0 */ { .g1_amp = 0x8, .g2_amp = 0xa, .g3_amp = 0x1e, - .g1_emph = 0x1, .g2_emph = 0x2, .g3_emph = 0x6, + .g1_emph = 0x1, .g2_emph = 0x2, .g3_emph = 0xe, .g1_emph_en = 0x1, .g2_emph_en = 0x1, .g3_emph_en = 0x1, .g1_tx_amp_adj = 0x1, .g2_tx_amp_adj = 0x1, .g3_tx_amp_adj = 0x1, .g1_tx_emph_en = 0x0, .g2_tx_emph_en = 0x0, .g3_tx_emph_en = 0x0, .g1_tx_emph = 0x1, .g2_tx_emph = 0x1, .g3_tx_emph = 0x1, .g3_dfe_res = 0x1, .g3_ffe_res_sel = 0x4, .g3_ffe_cap_sel = 0xf, - .allign_90 = 0x1c, + .allign_90 = 0x61, .g1_rx_selmuff = 0x3, .g2_rx_selmuff = 0x3, .g3_rx_selmuff = 0x3, .g1_rx_selmufi = 0x0, .g2_rx_selmufi = 0x0, .g3_rx_selmufi = 0x3, .g1_rx_selmupf = 0x1, .g2_rx_selmupf = 0x1, .g3_rx_selmupf = 0x2, @@ -69,13 +69,13 @@ static const struct sata_params sata_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_ }, /* Comphy1 */ { 0 }, /* Comphy2 */ { .g1_amp = 0x8, .g2_amp = 0xa, .g3_amp = 0x1e, - .g1_emph = 0x1, .g2_emph = 0x2, .g3_emph = 0x6, + .g1_emph = 0x1, .g2_emph = 0x2, .g3_emph = 0xe, .g1_emph_en = 0x1, .g2_emph_en = 0x1, .g3_emph_en = 0x1, .g1_tx_amp_adj = 0x1, .g2_tx_amp_adj = 0x1, .g3_tx_amp_adj = 0x1, .g1_tx_emph_en = 0x0, .g2_tx_emph_en = 0x0, .g3_tx_emph_en = 0x0, .g1_tx_emph = 0x1, .g2_tx_emph = 0x1, .g3_tx_emph = 0x1, .g3_dfe_res = 0x1, .g3_ffe_res_sel = 0x4, .g3_ffe_cap_sel = 0xf, - .allign_90 = 0x1c, + .allign_90 = 0x61, .g1_rx_selmuff = 0x3, .g2_rx_selmuff = 0x3, .g3_rx_selmuff = 0x3, .g1_rx_selmufi = 0x0, .g2_rx_selmufi = 0x0, .g3_rx_selmufi = 0x3, .g1_rx_selmupf = 0x1, .g2_rx_selmupf = 0x1, .g3_rx_selmupf = 0x2, @@ -90,13 +90,13 @@ static const struct sata_params sata_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_ { { 0 }, /* Comphy0 */ { .g1_amp = 0x8, .g2_amp = 0xa, .g3_amp = 0x1e, - .g1_emph = 0x1, .g2_emph = 0x2, .g3_emph = 0x6, + .g1_emph = 0x1, .g2_emph = 0x2, .g3_emph = 0xe, .g1_emph_en = 0x1, .g2_emph_en = 0x1, .g3_emph_en = 0x1, .g1_tx_amp_adj = 0x1, .g2_tx_amp_adj = 0x1, .g3_tx_amp_adj = 0x1, .g1_tx_emph_en = 0x0, .g2_tx_emph_en = 0x0, .g3_tx_emph_en = 0x0, .g1_tx_emph = 0x1, .g2_tx_emph = 0x1, .g3_tx_emph = 0x1, .g3_dfe_res = 0x1, .g3_ffe_res_sel = 0x4, .g3_ffe_cap_sel = 0xf, - .allign_90 = 0x1c, + .allign_90 = 0x61, .g1_rx_selmuff = 0x3, .g2_rx_selmuff = 0x3, .g3_rx_selmuff = 0x3, .g1_rx_selmufi = 0x0, .g2_rx_selmufi = 0x0, .g3_rx_selmufi = 0x3, .g1_rx_selmupf = 0x1, .g2_rx_selmupf = 0x1, .g3_rx_selmupf = 0x2, @@ -105,13 +105,13 @@ static const struct sata_params sata_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_ }, /* Comphy1 */ { 0 }, /* Comphy2 */ { .g1_amp = 0x8, .g2_amp = 0xa, .g3_amp = 0x1e, - .g1_emph = 0x1, .g2_emph = 0x2, .g3_emph = 0x6, + .g1_emph = 0x1, .g2_emph = 0x2, .g3_emph = 0xe, .g1_emph_en = 0x1, .g2_emph_en = 0x1, .g3_emph_en = 0x1, .g1_tx_amp_adj = 0x1, .g2_tx_amp_adj = 0x1, .g3_tx_amp_adj = 0x1, .g1_tx_emph_en = 0x0, .g2_tx_emph_en = 0x0, .g3_tx_emph_en = 0x0, .g1_tx_emph = 0x1, .g2_tx_emph = 0x1, .g3_tx_emph = 0x1, .g3_dfe_res = 0x1, .g3_ffe_res_sel = 0x4, .g3_ffe_cap_sel = 0xf, - .allign_90 = 0x1c, + .allign_90 = 0x61, .g1_rx_selmuff = 0x3, .g2_rx_selmuff = 0x3, .g3_rx_selmuff = 0x3, .g1_rx_selmufi = 0x0, .g2_rx_selmufi = 0x0, .g3_rx_selmufi = 0x3, .g1_rx_selmupf = 0x1, .g2_rx_selmupf = 0x1, .g3_rx_selmupf = 0x2, -- cgit