From 5979705ce0fa4fa36d00870fd21bcdb7665e05b1 Mon Sep 17 00:00:00 2001 From: wei yan Date: Mon, 10 Apr 2017 14:37:21 +0800 Subject: pm: a3700: support uart port as wake up source - For uart1, the first step is setting uart tx and rx pin as gpio mode, and then set gpio 18/19 as wake up source. - For uart0, the first step is setting uart tx and rx pin as gpio mode, and then set gpio 25/26 as wake up source. - Default config uart1 as wake up source. Change-Id: I8deb16266300af5b1d72d7a13ebd7a2e5cecc451 Signed-off-by: wei yan Signed-off-by: allen yan Reviewed-on: http://vgitil04.il.marvell.com:8080/38685 Tested-by: iSoC Platform CI Reviewed-by: Hua Jing --- plat/marvell/a3700/a3700/board/pm_src.c | 5 +++- plat/marvell/a3700/common/plat_pm.c | 46 ++++++++++++++++++++++++++++++--- 2 files changed, 47 insertions(+), 4 deletions(-) diff --git a/plat/marvell/a3700/a3700/board/pm_src.c b/plat/marvell/a3700/a3700/board/pm_src.c index 636c1c2d..5d2e23f0 100644 --- a/plat/marvell/a3700/a3700/board/pm_src.c +++ b/plat/marvell/a3700/a3700/board/pm_src.c @@ -37,7 +37,7 @@ /* This struct provides the PM wake up src configuration */ static struct pm_wake_up_src_config wake_up_src_cfg = { - .wake_up_src_num = 2, + .wake_up_src_num = 3, .wake_up_src[0] = { .wake_up_src_type = WAKE_UP_SRC_GPIO, .wake_up_data = { @@ -51,6 +51,9 @@ static struct pm_wake_up_src_config wake_up_src_cfg = { .gpio_data.bank_num = 1, /* South Bridge */ .gpio_data.gpio_num = 2 } + }, + .wake_up_src[2] = { + .wake_up_src_type = WAKE_UP_SRC_UART1, } }; diff --git a/plat/marvell/a3700/common/plat_pm.c b/plat/marvell/a3700/common/plat_pm.c index 5b2cba17..23fa9915 100644 --- a/plat/marvell/a3700/common/plat_pm.c +++ b/plat/marvell/a3700/common/plat_pm.c @@ -53,6 +53,13 @@ #define MVEBU_WARM_RESET_REG (MVEBU_NB_REGS_BASE + 0x840) #define MVEBU_WARM_RESET_MAGIC 0x1D1E +/* North Bridge GPIO1 SEL register */ +#define MVEBU_NB_GPIO1_SEL_REG (MVEBU_NB_REGS_BASE + 0x830) + #define MVEBU_NB_GPIO1_UART1_SEL BIT(19) + #define MVEBU_NB_GPIO1_GPIO_25_26_EN BIT(17) + #define MVEBU_NB_GPIO1_GPIO_19_EN BIT(14) + #define MVEBU_NB_GPIO1_GPIO_18_EN BIT(13) + /* CPU 1 reset register */ #define MVEBU_CPU_1_RESET_VECTOR (MVEBU_REGS_BASE + 0x14044) #define MVEBU_CPU_1_RESET_REG (MVEBU_REGS_BASE + 0xD00C) @@ -186,6 +193,11 @@ #define MVEBU_NB_STEP_DOWN_INT_EN_REG MVEBU_NB_STEP_DOWN_REG_BASE #define MVEBU_NB_GPIO_INT_WAKE_WCPU_CLK BIT(8) +#define MVEBU_NB_GPIO_18 18 +#define MVEBU_NB_GPIO_19 19 +#define MVEBU_NB_GPIO_25 25 +#define MVEBU_NB_GPIO_26 26 + typedef int (*wake_up_src_func)(union pm_wake_up_src_data *); struct wake_up_src_func_map { @@ -524,12 +536,40 @@ int a3700_pm_src_gpio(union pm_wake_up_src_data *src_data) return 0; } +int a3700_pm_src_uart1(union pm_wake_up_src_data *src_data) +{ + /* Clear Uart1 select */ + mmio_clrbits_32(MVEBU_NB_GPIO1_SEL_REG, MVEBU_NB_GPIO1_UART1_SEL); + /* set pin 19 gpio usage*/ + mmio_setbits_32(MVEBU_NB_GPIO1_SEL_REG, MVEBU_NB_GPIO1_GPIO_19_EN); + /* Enable gpio wake-up*/ + a3700_pm_en_nb_gpio(MVEBU_NB_GPIO_19); + /* set pin 18 gpio usage*/ + mmio_setbits_32(MVEBU_NB_GPIO1_SEL_REG, MVEBU_NB_GPIO1_GPIO_18_EN); + /* Enable gpio wake-up*/ + a3700_pm_en_nb_gpio(MVEBU_NB_GPIO_18); + + return 0; +} + +int a3700_pm_src_uart0(union pm_wake_up_src_data *src_data) +{ + /* set pin 25/26 gpio usage*/ + mmio_setbits_32(MVEBU_NB_GPIO1_SEL_REG, MVEBU_NB_GPIO1_GPIO_25_26_EN); + /* Enable gpio wake-up*/ + a3700_pm_en_nb_gpio(MVEBU_NB_GPIO_25); + /* Enable gpio wake-up*/ + a3700_pm_en_nb_gpio(MVEBU_NB_GPIO_26); + + return 0; +} + struct wake_up_src_func_map src_func_table[WAKE_UP_SRC_MAX] = { {WAKE_UP_SRC_GPIO, a3700_pm_src_gpio}, + {WAKE_UP_SRC_UART1, a3700_pm_src_uart1}, + {WAKE_UP_SRC_UART0, a3700_pm_src_uart0}, /* FOLLOWING SRC NOT SUPPORTED YET */ - {WAKE_UP_SRC_TIMER, NULL}, - {WAKE_UP_SRC_UART0, NULL}, - {WAKE_UP_SRC_UART1, NULL} + {WAKE_UP_SRC_TIMER, NULL} }; static wake_up_src_func a3700_get_wake_up_src_func(enum pm_wake_up_src_type type) -- cgit