From 8a3290cb8f52b1575350e03f44dc2e6785c5267a Mon Sep 17 00:00:00 2001 From: Terry Zhou Date: Mon, 19 Mar 2018 17:59:45 +0200 Subject: apn806: delete all the WA for the A0 chip We don't support A0 chip anymore Change-Id: I720df05591bf48a6506e441120f6a68bd9815db5 Signed-off-by: Terry Zhou Reviewed-on: http://vgitil04.il.marvell.com:8080/52186 Reviewed-by: Kostya Porotchkin Tested-by: iSoC Platform CI Reviewed-by: Hanna Hawa --- drivers/marvell/mochi/apn806_setup.c | 20 -------------------- include/drivers/marvell/mochi/ap_setup.h | 1 - plat/marvell/a8k/common/include/a8k_plat_def.h | 3 --- plat/marvell/a8k/common/plat_ble_setup.c | 4 ---- 4 files changed, 28 deletions(-) diff --git a/drivers/marvell/mochi/apn806_setup.c b/drivers/marvell/mochi/apn806_setup.c index 6485e3bc..9a8424de 100644 --- a/drivers/marvell/mochi/apn806_setup.c +++ b/drivers/marvell/mochi/apn806_setup.c @@ -165,15 +165,6 @@ static void init_aurora2(void) reg = mmio_read_32(CCU_HTC_CR); reg |= (0x1 << CCU_SET_POC_OFFSET); mmio_write_32(CCU_HTC_CR, reg); - - /* A0 Only: cache line clean & invalidate instead of) - ** cache line invalidate only - to avoid system hang - ** due to memory coherency issue */ - if (ap_rev_id_get() == APN806_REV_ID_A0) { - reg = mmio_read_32(CCU_LTC_CR); - reg |= (0x1 << CCU_CLEAN_INV_WRITE_OFFSET); - mmio_write_32(CCU_LTC_CR, reg); - } #endif /* !LLC_DISABLE */ apn806_errata_wa_init(); @@ -288,14 +279,3 @@ void ap_ble_init(void) { } -int ap_rev_id_get(void) -{ - /* Returns: - * - 0 (APN806_REV_ID_A0) for A0 - * - 1 (APN806_REV_ID_A1) for A1 - */ - return (mmio_read_32(MVEBU_CSS_GWD_CTRL_IIDR2_REG) >> - GWD_IIDR2_REV_ID_OFFSET) & - GWD_IIDR2_REV_ID_MASK; -} - diff --git a/include/drivers/marvell/mochi/ap_setup.h b/include/drivers/marvell/mochi/ap_setup.h index 256edd9d..a2cbfba5 100644 --- a/include/drivers/marvell/mochi/ap_setup.h +++ b/include/drivers/marvell/mochi/ap_setup.h @@ -36,5 +36,4 @@ void ap_init(void); void ap_ble_init(void); -int ap_rev_id_get(void); #endif /* __AP_SETUP_H__ */ diff --git a/plat/marvell/a8k/common/include/a8k_plat_def.h b/plat/marvell/a8k/common/include/a8k_plat_def.h index d5179241..b3a5a378 100644 --- a/plat/marvell/a8k/common/include/a8k_plat_def.h +++ b/plat/marvell/a8k/common/include/a8k_plat_def.h @@ -40,9 +40,6 @@ #define MVEBU_PRIMARY_CPU 0x0 #define MVEBU_AP0 0x0 -#define APN806_REV_ID_A0 0 -#define APN806_REV_ID_A1 1 - /* APN806 revision ID */ #define MVEBU_CSS_GWD_CTRL_IIDR2_REG (MVEBU_REGS_BASE + 0x610FCC) #define GWD_IIDR2_REV_ID_OFFSET 12 diff --git a/plat/marvell/a8k/common/plat_ble_setup.c b/plat/marvell/a8k/common/plat_ble_setup.c index 38ec2d6c..c8b02954 100644 --- a/plat/marvell/a8k/common/plat_ble_setup.c +++ b/plat/marvell/a8k/common/plat_ble_setup.c @@ -180,10 +180,6 @@ static void ble_plat_avs_config(void) { uint32_t reg_val, device_id; - /* Do nothing on A0 revision SoCs */ - if (ap_rev_id_get() == APN806_REV_ID_A0) - return; - /* Check which SoC is running and act accordingly */ device_id = cp110_device_id_get(MVEBU_CP_REGS_BASE(0)); switch (device_id) { -- cgit