From 9ad8ec8d83ee48298c1d550763596a6a53d447a3 Mon Sep 17 00:00:00 2001 From: Eleanor Bonnici Date: Wed, 2 Aug 2017 18:33:41 +0100 Subject: Cortex-A72: Implement workaround for erratum 859971 Erratum 855971 applies to revision r0p3 or earlier Cortex-A72 CPUs. The recommended workaround is to disable instruction prefetch. Change-Id: I7fde74ee2a8a23b2a8a1891b260f0eb909fad4bf Signed-off-by: Eleanor Bonnici Signed-off-by: Jeenu Viswambharan Reviewed-on: http://vgitil04.il.marvell.com:8080/52568 Tested-by: iSoC Platform CI Reviewed-by: Kostya Porotchkin --- include/lib/cpus/aarch64/cortex_a72.h | 1 + lib/cpus/aarch64/cortex_a72.S | 57 +++++++++++++++++++++++++++++++++-- lib/cpus/cpu-ops.mk | 8 +++++ 3 files changed, 64 insertions(+), 2 deletions(-) diff --git a/include/lib/cpus/aarch64/cortex_a72.h b/include/lib/cpus/aarch64/cortex_a72.h index 01edf43b..0648efe2 100644 --- a/include/lib/cpus/aarch64/cortex_a72.h +++ b/include/lib/cpus/aarch64/cortex_a72.h @@ -57,6 +57,7 @@ #define CPUACTLR_DISABLE_L1_DCACHE_HW_PFTCH (1 << 56) #define CPUACTLR_NO_ALLOC_WBWA (1 << 49) #define CPUACTLR_DCC_AS_DCCI (1 << 44) +#define CPUACTLR_EL1_DIS_INSTR_PREFETCH (1 << 32) /******************************************************************************* * L2 Control register specific definitions. diff --git a/lib/cpus/aarch64/cortex_a72.S b/lib/cpus/aarch64/cortex_a72.S index ba40d467..0210bdcd 100644 --- a/lib/cpus/aarch64/cortex_a72.S +++ b/lib/cpus/aarch64/cortex_a72.S @@ -97,11 +97,43 @@ func cortex_a72_disable_ext_debug ret endfunc cortex_a72_disable_ext_debug + /* -------------------------------------------------- + * Errata Workaround for Cortex A72 Errata #859971. + * This applies only to revision <= r0p3 of Cortex A72. + * Inputs: + * x0: variant[4:7] and revision[0:3] of current cpu. + * Shall clobber: + * -------------------------------------------------- + */ +func errata_a72_859971_wa + mov x17,x30 + bl check_errata_859971 + cbz x0, 1f + mrs x1, CPUACTLR_EL1 + orr x1, x1, #CPUACTLR_EL1_DIS_INSTR_PREFETCH + msr CPUACTLR_EL1, x1 +1: + ret x17 +endfunc errata_a72_859971_wa + +func check_errata_859971 + mov x1, #0x03 + b cpu_rev_var_ls +endfunc check_errata_859971 + /* ------------------------------------------------- * The CPU Ops reset function for Cortex-A72. * ------------------------------------------------- */ func cortex_a72_reset_func + mov x19, x30 + bl cpu_get_rev_var + mov x18, x0 + +#if ERRATA_A72_859971 + mov x0, x18 + bl errata_a72_859971_wa +#endif #if IMAGE_BL31 && WORKAROUND_CVE_2017_5715 adr x0, workaround_mmu_runtime_exceptions @@ -109,14 +141,14 @@ func cortex_a72_reset_func #endif /* --------------------------------------------- - * As a bare minimum enable the SMP bit. + * Enable the SMP bit. * --------------------------------------------- */ mrs x0, CPUECTLR_EL1 orr x0, x0, #CPUECTLR_SMP_BIT msr CPUECTLR_EL1, x0 isb - ret + ret x19 endfunc cortex_a72_reset_func /* ---------------------------------------------------- @@ -226,6 +258,27 @@ func cortex_a72_cluster_pwr_dwn b cortex_a72_disable_ext_debug endfunc cortex_a72_cluster_pwr_dwn +#if REPORT_ERRATA +/* + * Errata printing function for Cortex A72. Must follow AAPCS. + */ +func cortex_a72_errata_report + stp x8, x30, [sp, #-16]! + + bl cpu_get_rev_var + mov x8, x0 + + /* + * Report all errata. The revision-variant information is passed to + * checking functions of each errata. + */ + report_errata ERRATA_A72_859971, cortex_a72, 859971 + + ldp x8, x30, [sp], #16 + ret +endfunc cortex_a72_errata_report +#endif + /* --------------------------------------------- * This function provides cortex_a72 specific * register information for crash reporting. diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index d1144247..0c67eec1 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -99,6 +99,10 @@ ERRATA_A57_829520 ?=0 # only to revision <= r1p2 of the Cortex A57 cpu. ERRATA_A57_833471 ?=0 +# Flag to apply erratum 855971 workaround during reset. This erratum applies +# only to revision <= r0p3 of the Cortex A72 cpu. +ERRATA_A72_859971 ?=0 + # Process ERRATA_A53_826319 flag $(eval $(call assert_boolean,ERRATA_A53_826319)) $(eval $(call add_define,ERRATA_A53_826319)) @@ -134,3 +138,7 @@ $(eval $(call add_define,ERRATA_A57_829520)) # Process ERRATA_A57_833471 flag $(eval $(call assert_boolean,ERRATA_A57_833471)) $(eval $(call add_define,ERRATA_A57_833471)) + +# Process ERRATA_A72_859971 flag +$(eval $(call assert_boolean,ERRATA_A72_859971)) +$(eval $(call add_define,ERRATA_A72_859971)) -- cgit