From 3b9c18c667b6e363e292ad639e92bfeb6780b579 Mon Sep 17 00:00:00 2001 From: Konstantin Porotchkin Date: Wed, 29 Mar 2017 12:43:19 +0300 Subject: platform: Add support for Marvell A7K/A8K platforms Add platform support files for Marvell A7K and A7K SoC families. Change-Id: I4f8b0a7cd222be5b7f43577172f1cdba58ffc124 Signed-off-by: Haim Boot Signed-off-by: Konstantin Porotchkin Reviewed-on: http://vgitil04.il.marvell.com:8080/37918 --- plat/marvell/a8k/common/mss/mss_pm_ipc.h | 88 ++++++++++++++++++++++++++++++++ 1 file changed, 88 insertions(+) create mode 100644 plat/marvell/a8k/common/mss/mss_pm_ipc.h (limited to 'plat/marvell/a8k/common/mss/mss_pm_ipc.h') diff --git a/plat/marvell/a8k/common/mss/mss_pm_ipc.h b/plat/marvell/a8k/common/mss/mss_pm_ipc.h new file mode 100644 index 00000000..16044c06 --- /dev/null +++ b/plat/marvell/a8k/common/mss/mss_pm_ipc.h @@ -0,0 +1,88 @@ +/* + * *************************************************************************** + * Copyright (C) 2016 Marvell International Ltd. + * *************************************************************************** + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * Neither the name of Marvell nor the names of its contributors may be used + * to endorse or promote products derived from this software without specific + * prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, + * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *************************************************************************** + */ + +#ifndef __MSS_PM_IPC_H +#define __MSS_PM_IPC_H + + +#include +/* Currently MSS does not support Cluster level Power Down */ +#define DISABLE_CLUSTER_LEVEL + + +/******************************************************************************* + * mss_pm_ipc_msg_send + * + * DESCRIPTION: create and transmit IPC message + ****************************************************************************** + */ +int mss_pm_ipc_msg_send(unsigned int channel_id, + const psci_power_state_t *target_state); + +/******************************************************************************* + * mss_pm_ipc_msg_recv + * + * DESCRIPTION: wait from reception of IPC message indication, + * once received, read the message from IPC channel, + * mark IPC channel as Free, and validate reply + ****************************************************************************** + */ +int mss_pm_ipc_msg_recv(unsigned int channel_id, unsigned int msg_id); + +/******************************************************************************* + * mss_pm_ipc_on_msg_trigger + * + * DESCRIPTION: Trigger IPC ON message interrupt to MSS + ****************************************************************************** + */ +int mss_pm_ipc_on_msg_trigger(unsigned int cpu_id); + +/******************************************************************************* + * mss_pm_ipc_on_msg_trigger + * + * DESCRIPTION: Trigger IPC OFF message interrupt to MSS + ****************************************************************************** + */ +int mss_pm_ipc_off_msg_trigger(unsigned int cpu_id); + +/******************************************************************************* + * mss_pm_ipc_on_msg_trigger + * + * DESCRIPTION: Trigger IPC SUSPEND message interrupt to MSS + ****************************************************************************** + */ +int mss_pm_ipc_suspend_msg_trigger(unsigned int cpu_id); + + +#endif /* __MSS_PM_IPC_H */ -- cgit