Base pixel formats that can be used as source or destination for the 2D engine. Additional formats can be supported by using RGBA or UV swizzles. Unlike the shader engine, the 2D engine has no full swizzle capability. Four predefined common swizzles are available, however these can be specified for both the source and destination. To calculate the stride multiply the surface width in pixels (8-pixel aligned) by the number of bytes per pixel. 90 degree rotation configuration for the source surface. Width field specifies the width of the surface in pixels. If set to ABSOLUTE, the source coordinates are treated as absolute coordinates inside the source surface. If set to RELATIVE, the source coordinates are treated as the offsets from the destination coordinates with the source size equal to the size of the destination. Set to STREAM for mono expansion blits or masked blits. For mono expansion blits the complete bitmap comes from the command stream. For masked blits the source data comes from the memory and the mask from the command stream. Determines how many horizontal pixels there are per each 32-bit chunk. For example, if set to PACKED8, each 32-bit chunk is 8-pixel wide, which also means that it defines 4 vertical lines of pixels. Absolute or relative (determined by the SRC_RELATIVE field of the SRC_CONFIG register) X and Y coordinates in pixels of the top left corner of the source rectangle within the source surface. The width and height of the source rectangle in pixels. If the source is relative, or a regular bitblt is being performed without stretching, this register is ignored and the source size is assumed to be the same as the destination size. Raster operation foreground and background codes. Even though ROP is not used in CLEAR, HOR_FILTER_BLT, VER_FILTER_BLT and alpha-enabled BIT_BLTs, ROP code still has to be programmed, because the engine makes the decision whether source, destination and pattern are involved in the current operation and the correct decision is essential for the engine to complete the operation as expected. ROP builds a lookup table for a logical operation with 2, 3 or 4 inputs (depending on ROP type). So for a ROP3, for example, the rop pattern will be 2^3=8 bits. ROP2_PATTERN [untested] bit 0 destination bit 1 pattern ROP2_SOURCE [untested] bit 0 destination bit 1 source ROP3 (uses ROP_FG only) bit 0 destination bit 1 source bit 2 pattern ROP4 (uses ROP_FG and ROP_BG) bit 0 destination bit 1 source bit 2 pattern bit "3" foreground/background (ROP_FG / ROP_BG) Used to choose between premultiplied and non-premultiplied alpha for the source color on PE10. PE20 hardware uses the COLOR_MULTIPLY_MODES register for this instead, which offers more flexibility. Normally this is enabled together with PE10_DST_COLOR_MULTIPLY. Used to choose between premultiplied and non-premultiplied alpha for the source color on PE10. PE20 hardware uses the COLOR_MULTIPLY_MODES register for this instead, which offers more flexibility. Normally this is enabled together with PE10_SRC_COLOR_MULTIPLY. 180/270 degree rotation configuration for the source surface. Height field specifies the height of the surface in pixels. 0/90/180/270 degree rotation and mirroring configuration for the source and destination surface. Height field specifies the height of the surface in pixels. Color modes to multiply source or destination pixel color by alpha channel. Alpha can be from global color source or current pixel. KEY transparency mode is reserved. MASK transparency mode is reserved. 2D drawing engine: conversion, scaling, filtering, rotation, blending of 2D images. In mono expansion this register defines the source color if the mono pixel is 0. The color must be set in A8R8G8B8 format. In color blits it defines the source transparency color and must be of the same format as the source format. In mono expansion this register defines the source color if the mono pixel is 1. The color must be set in A8R8G8B8 format. The value is calculated using the following formula: factor = ((srcWidth - 1) << 16) / (dstWidth - 1) Stretch blit uses only the integer part of the value while Filter blit uses all 31 bits. The value is calculated using the following formula: factor = ((srcWidth - 1) << 16) / (dstWidth - 1) Stretch blit uses only the integer part of the value while Filter blit uses all 31 bits. To calculate the stride multiply the surface width in pixels (8-pixel aligned) by the number of bytes per pixel. 90 degree rotation configuration for the destination surface. Width field specifies the width of the surface in pixels. Reserved field for future expansion. Draw solid filled rectangles. Draw lines. Lines can either be filled with a solid color or a pattern. Clipping is always on (except with filter blits) and everything beyond the clipping rectangle will be clipped out. Top left coordinates are inclusive. Clipping is always on (except with filter blits) and everything beyond the clipping rectangle will be clipped out. Bottom right coordinates are exclusive. Byte pattern mask used for clearing. PE1.0 uses a 8-byte pattern for clearing as specified in the CLEAR_PIXEL_VALUE_LOW and CLEAR_PIXEL_VALUE_HIGH registers. Each of 8 bits refers to a byte. A value of 1 clears the respective byte, and a value of 0 ignores it. This register and CLEAR_PIXEL_VALUE_HIGH specify a 8-byte pattern to be used for CLEAR operations. Together with values in SRC_ORIGIN these values form signed 16.16 fixed point origin for the source rectangle. Fractions are only used in filter blit in split frame mode. Bypass destination fetch when writing part of a cache block. Destination fetch can be disabled if the area around the target rectangle is not important. 180/270 degree rotation configuration for the destination surface. Height field specifies the height of the surface in pixels. Used as source color when blitting from A8 sources. If you don't want dither, set all fields to their reset values (0xFFFFFFFF). If you don't want dither, set all fields to their reset values (0xFFFFFFFF). The algorithm uses 5 bits of the pixel coordinate's fraction to index the kernel array, which makes it a 32-entry array. Each entry consists of 9 kernel values. In practice we store only a half of the table, because the other half is a mirror of the first, therefore: rows_to_store = 32 / 2 + 1 = 17 values_to_store = rows_to_store * 9 = 153 even_value_count = (values_to_store + 1) & ~1 = 154 dword_count = even_value_count / 2 = 77 256 color entries for the indexed color mode. Colors are assumed to be in the destination format and no color conversion is done on the values. This register is only used with chips with PE10 feature. 256 color entries for the indexed color mode. Colors are assumed to be in A8R8G8B8 format and no color conversion is done on the values. This register is only used with chips with PE20 feature. These registers are used for multi-source blit when the capability 2D_MULTI_SOURCE_BLIT is available. These registers are used for multi-source blit when the capability 2D_MULTI_SOURCE_BLIT_EX is available.