Host interface contains bits to identify the chip, control clock speed, and enable/acknowledge interrupts. If this bit is 1, debug registers are clock gated. Bits are 1 if the module is idle, 0 otherwise. Each bit represents a corresponding event being triggered. Reading this register clears the interrupt flags. Each bit enabled a corresponding event. Obsolete since GC500. Writing 1 will reset the counters and stop counting. Write 0 to start counting again. This register is a free running counter. It can be reset by writing 0 to it. It is reset when PROFILE_TOTAL_CYCLES register is written to. It looks at all the blocks but FE when determining the IP is idle. Features to control power usage. New MMU unit. Only exists on more recent hardware. A 64-byte range starting from this address that will act as a 'safe' zone. Any address that would cause an exception is routed to this safe zone. Reads will happen and writes will go to this address, but with a write-enable of 0. This register can only be programmed once after a reset. Any attempt to write to this register after the initial write-after-reset will be ignored. Each page can be 4kB or 64kB in size. Each page can be 4kB, 64kB, 1MB or 16MB in size. EXCEPTION_ADDR[0] will contain the exception address. EXCEPTION_ADDR[1] will contain the exception address. EXCEPTION_ADDR[2] will contain the exception address. EXCEPTION_ADDR[3] will contain the exception address. For security reasons, once the MMU is enabled it cannot be disabled anymore. The performance counter selected here can be read from one of the associated PROFILE_xx_READ registers. Selecting counter 15 resets all the counters of that unit. The performance counter selected here can be read from one of the associated PROFILE_xx_READ registers. Selecting counter 15 resets all the counters of that unit. The performance counter selected here can be read from one of the associated PROFILE_xx_READ registers. Selecting counter 15 resets all the counters of that unit.