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authorChristophe Leroy <christophe.leroy@c-s.fr>2020-05-21 16:56:03 +0000
committerMichael Ellerman <mpe@ellerman.id.au>2020-05-28 23:24:36 +1000
commit797f4016f6da4a90ac83e32b213b68ff7be3812b (patch)
tree56241ddf356705d5f9ef08f33b20bc60105d0660 /scripts/gdb/linux/proc.py
parent455531e9d88048c025ff9099796413df748d92b9 (diff)
powerpc/40x: Avoid using r12 in TLB miss handlers
Let's reduce the number of registers used in TLB miss handlers. We have both r9 and r12 available for any temporary use. r9 is enough, avoid using r12. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/7f330e971952abb2645fb9ca4310c0f527e84dcb.1590079969.git.christophe.leroy@csgroup.eu
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