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| author | Heiko Stuebner <heiko@sntech.de> | 2016-01-19 10:01:08 +0100 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2016-01-24 23:29:16 +0100 |
| commit | 535ebd428aeb07c3327947281306f2943f2c9faa (patch) | |
| tree | 91f83de7f76548c303d4098a5ef571aaf9e03292 /scripts/gdb/linux/utils.py | |
| parent | ee16bbd289a63e3036d31dcd809e411e9a5dbd5d (diff) | |
clk: rockchip: rk3368: fix cpuclk mux bit of big cpu-cluster
Both clusters have their mux bit in bit 7 of their respective register.
For whatever reason the big cluster currently lists bit 15 which is
definitly wrong.
Fixes: 3536c97a52db ("clk: rockchip: add rk3368 clock controller")
Reported-by: Zhang Qing <zhangqing@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: zhangqing <zhangqing@rock-chips.com>
Cc: stable@vger.kernel.org
Diffstat (limited to 'scripts/gdb/linux/utils.py')
0 files changed, 0 insertions, 0 deletions