diff options
| -rw-r--r-- | drivers/soc/renesas/Kconfig | 12 | ||||
| -rw-r--r-- | drivers/soc/renesas/pwc-rzv2m.c | 8 |
2 files changed, 17 insertions, 3 deletions
diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index fbc3b69d21a7..ba921f5c3aff 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -408,6 +408,18 @@ config ARCH_R9A09G057 help This enables support for the Renesas RZ/V2H(P) SoC variants. +config ARCH_R9A09G077 + bool "ARM64 Platform support for RZ/T2H" + default y if ARCH_RENESAS + help + This enables support for the Renesas RZ/T2H SoC variants. + +config ARCH_R9A09G087 + bool "ARM64 Platform support for RZ/N2H" + default y if ARCH_RENESAS + help + This enables support for the Renesas RZ/N2H SoC variants. + endif # ARM64 if RISCV diff --git a/drivers/soc/renesas/pwc-rzv2m.c b/drivers/soc/renesas/pwc-rzv2m.c index 452cee8d68be..4dbcb3d4a90c 100644 --- a/drivers/soc/renesas/pwc-rzv2m.c +++ b/drivers/soc/renesas/pwc-rzv2m.c @@ -24,8 +24,8 @@ struct rzv2m_pwc_priv { DECLARE_BITMAP(ch_en_bits, 2); }; -static void rzv2m_pwc_gpio_set(struct gpio_chip *chip, unsigned int offset, - int value) +static int rzv2m_pwc_gpio_set(struct gpio_chip *chip, unsigned int offset, + int value) { struct rzv2m_pwc_priv *priv = gpiochip_get_data(chip); u32 reg; @@ -38,6 +38,8 @@ static void rzv2m_pwc_gpio_set(struct gpio_chip *chip, unsigned int offset, writel(reg, priv->base + PWC_GPIO); assign_bit(offset, priv->ch_en_bits, value); + + return 0; } static int rzv2m_pwc_gpio_get(struct gpio_chip *chip, unsigned int offset) @@ -62,7 +64,7 @@ static const struct gpio_chip rzv2m_pwc_gc = { .label = "gpio_rzv2m_pwc", .owner = THIS_MODULE, .get = rzv2m_pwc_gpio_get, - .set = rzv2m_pwc_gpio_set, + .set_rv = rzv2m_pwc_gpio_set, .direction_output = rzv2m_pwc_gpio_direction_output, .can_sleep = false, .ngpio = 2, |