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into dt3-base
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This is a commit from the for-next branch of Linus Walleij's pin control tre
git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git
It is the oldest commit in that branch that provides the dependencies
needed for SoC changes to the usage of sh-pfc.
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When CONFIG_COMMON_CLOCK is enabled, call rcar_gen2_clocks_init() in the
timer init function to initialize the common clock framework before
initializing the clock sources. This will take care of clock
initialization when the r8a779[01] boards will be switched to
multiplatform kernels.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Add macros usable by device tree sources to reference r8a7791 clocks by
index.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Add macros usable by device tree sources to reference r8a7790 clocks by
index.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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This ensures that the PMIC RTC provides the system time, rather than
the on-SoC RTC, which is not battery-backed.
tegra124-venice2.dts isn't touched yet since we haven't added any off-
SoC RTC device to its device tree.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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According to board schematics, for HSMMC1 a GPIO line is used to detect
card presence, while currently it is being configured for internal card
detect line, which is multiplexed with card detect line of HSMMC0 and
thus breaking it.
This patch adds proper sdhci platform data setting card detect type to
external GPIO and fixing operation of HSMMC0.
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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Prepare the clock at probe time, as there is no other appropriate place
in the driver where we're allowed to sleep.
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
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The SPI controllers on Tegra124 are compatible with those found on the
Tegra114 SoC.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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This pin needs to be configured in pull-down, non-tristate mode in order
for the backlight to work correctly.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Other boards use PULL_NONE for their debug UART pins, and without this
change, the board doesn't accept any serial input.
Don't set the I2S port pins to tristate mode, or no audio signal will
be sent out.
Fixes: 605ae5804385 ("ARM: tegra: add default pinctrl nodes for Venice2")
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Add the default pinmux configuration for the Tegra124 based
Venice2 platform.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Set the parent of the regulators LDO2 to LDO9 according to the
schematic. Set the base voltage to 3.3V, there is only 3.3V on the
module itself.
Set the Core and CPU voltage to the specified voltages of 1.2V and
1.0V respectivly.
LDO6 should deliver 2.85V. The attached peripherals were not in
use so far.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Use Tegra pinconrol dt-binding macro to set the values of different pinmux
properties of Tegra30 platforms.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Use Tegra pinconrol dt-binding macro to set the values of different pinmux
properties of Tegra20 platforms.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Use Tegra pinconrol dt-binding macro to set the values of different pinmux
properties of Tegra114 platforms.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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This new header file defines pincontrol constants for Tegra to
use from Tegra's DTS file for pincontrol properties option.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Use key code macros for all key code refernced for keys.
For tegra20-seaboard.dts and tegra20-harmony.dts:
The key comment for key (16th row and 1st column) is KEY_KPSLASH but
code is 0x004e which is the key code for KEY_KPPLUS. As there other
key exist with KY_KPPLUS, I am assuming key code is wrong and comment
is fine. With this assumption, I am keeping the key code as KEY_KPSLASH.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Subsequent patches will need to reference a PWM channel for backlight
support, so enable the PWM device and assign a label to it.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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The PWM controller on Tegra124 is the same as the one on earlier SoC
generations.
Signed-off-by: Thierry Reding <treding@nvidia.com>
[swarren, added reset properties]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Venice2 uses the MAX98090 audio CODEC, and supports built-in speakers,
and a combo headphones/microphone jack. Add a top-level sound card node
to represent this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Tegra124 contains a similar set of audio devices to previous Tegra chips.
Specifically, there is an AHUB device which contains DMA FIFOs and audio
routing, and which hosts various audio-related components such as I2S
controllers.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Enable all the I2C controllers that are wired up on Venice2. I don't
know the correct I2C bus clock rates, so set them all to a conservative
100KHz for now.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Tegra124 has 6 I2C controllers. The first 5 have identical configuration
to Tegra114, but the sixth obviously has different interrupt/... IDs.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Tegra124 has 4 MMC controllers just like previous versions of the SoC.
Note that there are some non-backwards-compatible HW differences, and
hence a new DT compatible value must be used to describe the HW.
Also enable the relevant controllers in the Venice2 board DT.
power-gpios property suggested by Thierry Reding.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
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Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Acked by: Laxman Dewangan <ldewangan@nvidia.com>
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Instantiate the APB DMA controller in the Tegra124 DT, and add all
DMA-related properties to other DT nodes that rely on (reference) the
DMA controller's node.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
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The DT bindings now require module resets to be specified. The earlier
patches which added these nodes were originally written before that
requirement.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
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This patch adds clock properties for devices in the DT for basic support
of Tegra124 SoC.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
[swarren, added missing unit address to "clock" node]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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For Tegra DT files, I've been attempting to keep the nodes sorted in
the order:
1) Nodes with reg, in order of reg.
2) Nodes without reg, alphabetically.
This patch fixes a few escapees that I missed:-(
The diffs look larger than they really are, because sometimes when one
node was moved up or down, diff chose to represent this as many other
nodes being moved the other way!
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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DT node names should include a unit address iff the node has a reg
property. For Tegra DTs at least, we were previously applying a different
rule, namely that node names only needed to include a unit address if it
was required to make the node name unique. Consequently, many unit
addresses are missing. Add them.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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NVIDIA Tegra124 supports has the new GPIO port as GPIO_FF.
Add the macro for this port name.
Signed-off-by: Ashwini Ghuge <aghuge@nvidia.com>
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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Add the PRCM and CPU configuration units needed for SMP in the A31 DTSI.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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dma_request_slave_channel() returns NULL on error and not ERR_PTRs.
I've fixed this by using dma_request_slave_channel_reason() which does
return ERR_PTRs.
Fixes: a915d150f68d ('spi: tegra: convert to standard DMA DT bindings')
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
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The A13-OLinuXino-MICRO is a small dev-board with the Allwinner A13 SoC:
https://www.olimex.com/Products/OLinuXino/A13/A13-OLinuXino-MICRO/
Features:
A13 Cortex A8 processor at 1GHz, 3D Mali400 GPU
256 MB RAM (128Mbit x 16)
5VDC input power supply with own ICs, noise immune design
1 USB host
1 USB OTG which can power the board
SD-card connector for booting the Linux image
VGA video output
LCD signals available on connector so you still can use LCD if you disable VGA/HDMI
Audio output
Microphone input pads (no connector)
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
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Added a binding example for reference and updated the
node name. While at it also removed the name description
as it is not necessary.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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Fix the name as per DT node naming convention.
- rename the node to syscon which is a more generic name.
- append the register value to the node name.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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Added high speed I2C nodes to Exynos5420 DT file.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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The minimum recommended ARM voltage for Exynos5250 at 200MHz
on Arndale board is 0.9125V. Update accordingly.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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Exynos5420 is octa-core SoC from Samsung.
Hence populate all the CPU node entries.
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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Exynos5420 is octa-core SoC from Samsung. Hence extend exynos-mct clocksource
driver to support 8 local interrupts.
Also extend dts entries for 8 interrupts.
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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Adds G-Scaler device nodes to the DT device list
Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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This patch adds the mmc device tree node entries for exynos5420 SOC.
Exynos5420 has a different version of DWMMC controller,so a new
compatible string is used to distinguish it from the prior SOC's.
Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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This patch rename's the device tree mmc node's from "dwmmc" to "mmc".
According to ePAPR chapter 2.2.2 generic node name recommendation,
it has been opted change from dwmmc to mmc.Also this patch remove the
instance index from the node name.
Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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As fifo-depth property in dw_mmc device tree node is SOC
specific, move this property to exynos5250 SOC specific
file.
Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
[kgene.kim@samsung.com: squashed fifo-depth patch for cros5250-common]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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As per the timing information for supported panel, the value should
be between 47.2 MHz to 47.9 MHz for 60Hz refresh rate.
Total horizontal pixels = 1024 (x-res) + 80 (margin) + 48 (hsync) = 1152
Total vertical pixels = 600 (y-res) + 80 (margin) + 3 (vsync) = 683
Target pixel clock rate for refresh rate @60 Hz
= 1152 * 683 * 60 = 47208960 Hz ~ 47.5 MHz
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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As per the timing information for supported panel, the value should
be between 47.2 MHz to 47.9 MHz for 60Hz refresh rate.
Total horizontal pixels = 1024 (x-res) + 80 (margin) + 48 (hsync) = 1152
Total vertical pixels = 600 (y-res) + 80 (margin) + 3 (vsync) = 683
Target pixel clock rate for refresh rate @60 Hz
= 1152 * 683 * 60 = 47208960 Hz ~ 47.5 MHz
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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According to ePAPR, chapter 2.3.4, the status property has
defined that it should be set to "disabled" when "the device
is not presently operational, but it might become operational
in the future".
So this patch disable dwmmc node by "status = disabled" in SOC
dts file and enable dwmmc node by "status = okay" in board specific
dts file.
Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
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The PCI sub-system is not enabled by default on ARM and on certain
Renesas devices the build does not select it. This means that there
are configurations that do not allow the AHB-PCI bridge used for the
USB sub-systems to be built.
For the R8A7790, R8A7791 and EMEV-2 select MIGHT_HAVE_PCI to allow the
PCI drivers to be built. Also select MIGHT_HAVE_PCI for the multi-config
where there may be many Reneasas devices selected.
Reviewed-by: Ian Molton <ian.molton@codethink.co.uk>
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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