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Turn clk_enable() and clk_disable() calls into clk_prepare_enable() and
clk_disable_unprepare() to get ready for the migration to the common
clock framework.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Magnus Damm <damm@opensource.se>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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The break timer accesses hardware registers and thus requires the port
to be enabled. It currently ensures this by enabling the port at the
beginning of the timer handler, and disabling it at the end. However,
the enable/disable operations call the runtime PM sync functions, which
are not allowed in atomic context. The current situation is thus broken.
This change relies on non-atomic code to enable/disable the port. The
break timer will only be started from the IRQ handler, which already
runs with the port enabled. We just need to ensure that the port won't
be disabled with the timer running, and that's easily done by just
cancelling the timer in the port disable function.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Magnus Damm <damm@opensource.se>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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MSTP clocks are gate clocks controlled through a register that handles
up to 32 clocks. The register is often sparsely populated.
Those clocks are found on Renesas ARM SoCs.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
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DIV6 clocks are divider gate clocks controlled through a single
register. The divider is expressed on 6 bits, hence the name, and can
take values from 1/1 to 1/64.
Those clocks are found on Renesas ARM SoCs.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
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The R-Car Gen2 SoCs (R8A7790 and R8A7791) have several clocks that are
too custom to be supported in a generic driver. Those clocks can be
divided in two categories:
- Fixed rate clocks with multiplier and divisor set according to boot
mode configuration
- Custom divider clocks with SoC-specific divider values
This driver supports both.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
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Added device tree support for TI's Keystone USB driver and updated the
Documentation with device tree binding information.
Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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Added device tree support for TI's Keystone USB PHY driver and updated the
Documentation with device tree binding information.
Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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Update the Keystone gic device tree entry to add the maintenance
interrupt information.
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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Update the Keystone gic node to add the GICV and GIGH address space
needed by the KVM.
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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PA subsystem has a fixed factor clock at the input which is
input clock divided by 3. This patch adds this clock node to dts
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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Fix following typo
ddr3allclk -> ddr3apllclk
ddr3bllclk -> ddr3bpllclk
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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This patch adds K2 Kepler/Hawking evm (k2hk-evm) specific dts file.
To enable re-use of bindings across multiple evms of this family,
rename current keystone.dts to keystone.dtsi and include it in the
evm specific dts file.
K2 SoC has separate ref clock inputs for various clocks. So add
separate ref clock nodes for ARM, DDR3A, DDR3B and PA PLL input
clocks in k2hk-evm.dts. While at it, rename refclkmain to
refclksys based on device User Guide naming convention
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
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On non-DT platforms IRQ controllers associated with the GPIOs have a
fixed IRQ base value known at compile time. The sh-pfc driver translates
GPIO number to IRQ numbers using a hardcoded table. This mechanism
breaks on DT platforms, as the IRQ base values are dynamic in that case.
Fix this by specifying IRQs associated with GPIOs in IRQ resources,
populated automatically from the device tree. When IRQ resources are
specified the driver requires one IRQ resource per GPIO able to generate
an interrupt, and uses the translation table to compute the IRQ resource
offset instead of the IRQ number.
Cc: devicetree@vger.kernel.org
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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There's more than one window, name the field windows.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This makes catching duplicate entries easier. Merge the two IRQ9 entries
found after sorting.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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The external IRQ15 input multiplexed on GPIO 0 is missing. Add it.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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0 is a valid GPIO value, use -1 to terminate the gpios array in IRQ
lists.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Some indices take positive values only, make them unsigned.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Tegra124 adds a number of extra modules into the configlink bus, which
must be taken out of reset before the bus is used. Update the AHUB
driver to know about these extra modules (the AHUB HW module hosts the
configlink bus).
Based-on-work-by: Arun Shamanna Lakshmi <aruns@nvidia.com>
Based-on-work-by: Songhee Baek <sbaek@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Mark Brown <broonie@linaro.org>
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This patch depends on "ASoC: tegra: use reset framework" to compile,
which is ack'd and slated to go through a (large) topic branch in the
Tegra tree. So, we can either:
a) Merge that Tegra topic branch into the ASoC tree, then apply this.
Note that I haven't created the topic branch yet, since I'm still
waiting for DMA dependencies to be applied.
b) Apply this change to the Tegra tree too. This change isn't directly
related to the changes in the Tegra tree; it just makes use of the new
reset controller feature that's introduced there.
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ops->pin_config_get() is only used in one specific path that will only be taken
for generic pinconf drivers (ops->is_generic == true) when dumping the pinconf
by using debugfs.
By removing the check in pinconf_check_ops(), let's stop pressuring people to
write a pin_config_get() function that will never be used and so will probably
never be tested.
Removing the check in pinconf_pins_show() allows driver to not implement
pin_config_get() but still get a dump of the pinconf in debugfs by implementing
pin_config_dbg_show().
Finally, not implementing pin_config_get() now results in returning -ENOTSUPP
instead of -EINVAL. While this doesn't have any real impact for now, this feels
more right.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Prevent future unnecessary merge conflicts
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Prevent future unnecessary merge conflicts
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Prevent future (unnecessary) merge conflicts
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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This has caused merge conflicts in the past.
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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When passing a not initialized config parameter, at91_pinconf_get() would return
a bogus value. Fix that by initializing it to zero before using it.
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Marvell's Armada 370 Reference Design has a NAND flash, so enable it in
the devicetree and add the partitions as prepared in the factory images.
In order to skip the driver's custom device detection and use only ONFI
detection, the "marvell,keep-config" parameter is used. This is needed
because we have no support for setting the timings parameters yet.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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The board has 7 buttons connected to GPIOs, add a corresponding
gpio-keys device.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Use the %zu and %pad printk specifiers to print size_t and dma_addr_t
variables, and cast pointers to uintptr_t instead of unsigned int where
applicable. This fixes warnings on platforms where pointers and/or
dma_addr_t have a different size than int.
Cc: linux-serial@vger.kernel.org
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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HPB-DMAC has 2 channel for USB Func (= D0/D1)
D0 is used as Tx, D1 is used as Rx on this patch
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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If the system has been started in non-secure mode, then the ARM generic
timer is not configurable during the kernel initialisation. Currently
the only thing we can check for is if the timer has been correctly
configured during the boot process.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Reviewed-by: Ian Molton <ian.molton@codethink.co.uk>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Add support for R8A7791 Ether clock.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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<linux/platform_data/camera-rcar.h> is needed on BockW,
not setup-r8a7778.c
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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This patch support FSI-AK4648 with simple audio card
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Add a 'cpus' node to describe the CPU cores of Zynq.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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The bindings for the TTC changed in commit 'arm: zynq: Use standard
timer binding' (e932900a3279b5dbb6d8f43c7b369003620e137c). That change
removed possible subnodes from this driver rendering the 'clock-ranges'
property invalid for this node.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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The zynq includes a Cadence GEM IP core. This is compatible with the macb driver.
Add it to the zynq-7000 DT.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Josh Cartwright <josh.cartwright@ni.com>
[soren: rebased to current Linus tree, added zc706 + zed support, moved phy-mode property to board level dtses]
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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This patch adds PWM nodes for each of the four channels present on the
pxa270.
Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
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The "pcie_xclk" clock is not actually a clock at all, but rather a reset
domain. Now that the custom Tegra module reset API has been removed, we
can remove the definition of any "clocks" that existed solely to support
it.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
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Now that no code uses the custom Tegra module reset API, we can remove
its implementation.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
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Now that all Tegra drivers have been converted to use DMA APIs which
retrieve DMA channel information from standard DMA DT properties, we can
remove all the legacy DT DMA-related properties.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
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Now that all Tegra drivers have been converted to use the common reset
framework, we can remove all the legacy DT clocks/clock-names entries for
"clocks" that were only used with the old custom Tegra module reset API.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
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Tegra's clock driver now provides an implementation of the common
reset API (include/linux/reset.h). Use this instead of the old Tegra-
specific API; that will soon be removed.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Alan Stern <stern@rowland.harvard.edu>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Reviewed-by: Thierry Reding <treding@nvidia.com>
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Tegra's clock driver now provides an implementation of the common
reset API (include/linux/reset.h). Use this instead of the old Tegra-
specific API; that will soon be removed.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
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By using dma_request_slave_channel_or_err(), the DMA slave ID can be
looked up from standard DT properties, and squirrelled away during
channel allocation. Hence, there's no need to use a custom DT property
to store the slave ID.
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
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Tegra's clock driver now provides an implementation of the common
reset API (include/linux/reset.h). Use this instead of the old Tegra-
specific API; that will soon be removed.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Reviewed-by: Thierry Reding <treding@nvidia.com>
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By using dma_request_slave_channel_or_err(), the DMA slave ID can be
looked up from standard DT properties, and squirrelled away during
channel allocation. Hence, there's no need to use a custom DT property
to store the slave ID.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Mark Brown <broonie@linaro.org>
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