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This moves the Snowball LED pin config to the device tree.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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The SPI0 block is not at all connected to the AB8500 on the
Snowball: it is connected to the external header. These pins
on the header may also be used for GPIO, but let's assume
that SPI is a probable usecase on the Snowball and mux in the
SPI block and use these for SPI.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This transfers the muxing and biasing of the ethernet-related
pins on the snowball over to the device tree.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Move the few remaining HREFv60 pin configurations to the device
tree, reference these as hogs to the pin controller until there
are real devices that can make use of them.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Put two extra configs into the device tree to handle the default
configuration of the display reset signals on the HREFv60plus,
move this over from the board file to the device tree.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Move the control of muxing and enabling the IPGPIO (image
processor GPIO) from the static set-up to the device tree.
Use a hog as we have no device for the flash controller yet.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This moves some of the pin setup related to the CW1200 WLAN
module over to the device tree. As the driver is not yet
activated for the CW1200 WLAN we do not assign this pinctrl
state to any device node yet.
Get rid of the cmdline argument passing of a certain U9500
platform variant, as this is not supported by the kernel or
any device tree.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This moves over the configuration of the GPIO keys (used for
proximity sensor and Hall effect sensor) from the static pin
configuration file to the device tree. As part of the exercise,
implement the GPIO keys properly in a per-UIB file as this
setup actually differs with each UIB.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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The old HREFs (MOP500) were controlling an image-processor
GPIO (IPGPIO) by using hogs. Do the same thing with device tree
and get rid of the mop500_pins setting.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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The pin mappings for the STM (System Trace Macrocell) are not
really used by anything: we have no driver for is and the settings
are not connected to any device. We can recreate the different
mux outputs in the device tree the day we need them. Drop these
for now.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This moves the SKE keypad pin control table out of the board
file and into the device tree. This was previously set to be
active on all MOP500 and HREF boards but after reading the
schematic this seems incorrect: the HREFv60 and later uses
one of these for MC5 and no reference designs have the SKE
connected to any hardware so just leave the pins alone
in the power-on state.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This moves the MCDE pin control table out of the board file
and into the device tree. Some pins and configs have been
marked as used by sub-devices or slaves to the MCDE, such
as I2C device 0-070 which is the HDMI interface circuit
AV8100, but the pins rather belong to the MCDE SOC block
as they come out of the main ASIC. The touch screen GPIO
is not related to MCDE so this gets deleted and need to
be tied to the respective touch screen (I2C) device
once that device is added instead.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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As we need to connect resources such as pin mappings and clocks
when deleting board files, we create a MCDE node even though there
is no driver for it. As it is only using standard bindings right
now, this does not matter much. When a proper driver is written
for the MCDE, it can augment this node with custom properties.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This moves the SPI pin control table out of the board file
and into the device tree. Move the specific setting for
SSP0 on the HREFprev60 into the prev60-specific DTS file.
The SPI2 configuration is not really connected to any device,
as it will conflict with GPIO218 which is used on all HREFs.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This moves the MUSB pin control table out of the board file
and into the device tree. Tie the config to the on-chip MUSB
device rather than the ab8500-usb device which is off-chip.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This moves the input-pulled-up setting for GPIO217 as used
on the HREFs prior to v60 from the boardfile to the device
tree. GPIO218 is only used with the TVK UIB so move it to
that .dtsi file.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This moves the static, device-tied pin control configuration
out of the board file board-mop500-pins.c and into the device
tree. Add nodes for MSP0 and MSP2 on the HREF and Snowball
so we can reference the pins properly.
Cc: Lee Jones <lee.jones@linaro.org>
Cc: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This moves the static, device-tied pin control configuration
out of the board file board-mop500-pins.c and into the device
tree. Add entries for SDI1 and SDI2 on the Snowball so that the
WLAN pins on SDI1 can be used further on, and the unused pins
on SDI2 can be put to sleep.
Cc: Lee Jones <lee.jones@linaro.org>
Cc: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This moves the static, device-tied pin control configuration
out of the board file board-mop500-pins.c and into the device
tree. Define possible states also for I2C4 even if it's not
used by any board file at this time.
Cc: Lee Jones <lee.jones@linaro.org>
Cc: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This moves the static, device-tied pin control configuration
out of the board file board-mop500-pins.c and into the device
tree.
We create a new .dtsi-file to be shared between all the
MOP500-related boards, that include all HREF variants and
the Snowball board. Assign pin states for HREF and Snowball
boards alike.
Cc: Lee Jones <lee.jones@linaro.org>
Cc: Patrice Chotard <patrice.chotard@st.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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Move the platform data from all these files into one, delete empty
files and remove all references to them.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This hasn't been used since we converted the platform to DT only.
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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The TC3589x devices appearing in the ST Ericsson device trees
are adjusted to use the new binding so this is in a good shape,
and we add the keypad on the TVK1281618 UIB so this is working
again.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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With the commit d3f2950f2adeea3da0317e952914b59adaa4cdb3, the option
ARM_U8500_CPUIDLE was added to the Kconfig but not reflected in the
default config file, hence the cpuidle driver is no longer enabled
since this commit.
Enable it again by adding the missing option in the default config file.
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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This patch enables CONFIG_DETTMPFS and CONFIG_DEVTMPFS_MOUNT
flags for u8500 based devices.
In this way it's possible to create a tmpfs/ramfs already in the
early stages of the boot, allowing programs like udev/mdev to
populate the /dev directory.
Signed-off-by: Andi Shyti <andi@etezian.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
"Mostly bugfixes and a few small code removals. Worth pointing out is:
- A handful of more fixes to get DT enablement working properly on
OMAP, finding new breakage of things that don't work quite right
yet without the traditional board files. I expect a bit more of
this to come in this release as people test on their hardware.
- Implementation of power_down_finish() on vexpress, to make kexec
work and to stop the MCPM core to produce a warning (the warning
was new to 3.13-rc1).
- A handful of minor fixes for various platforms"
* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: bcm2835: add missing #xxx-cells to I2C nodes
ARM: dts: Add max77686 RTC interrupt to cros5250-common
ARM: vexpress/TC2: Implement MCPM power_down_finish()
ARM: tegra: Provide dummy powergate implementation
ARM: omap: fix warning with LPAE build
ARM: OMAP2+: Remove legacy omap4_twl6030_hsmmc_init
ARM: OMAP2+: Remove legacy mux code for display.c
ARM: OMAP2+: Fix undefined reference to set_cntfreq
gpio: twl4030: Fix passing of pdata in the device tree case
gpio: twl4030: Fix regression for twl gpio output
ARM: OMAP2+: More randconfig fixes for reconfigure_io_chain
ARM: dts: imx6qdl: disable spdif "rxtx5" clock option
ARM: dts: Fix omap2 specific dtsi files by adding the missing entries
ARM: OMAP2+: Fix GPMC and simplify bootloader timings for 8250 and smc91x
i2c: omap: Fix missing device tree flags for omap2
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git://git.kernel.org/pub/scm/linux/kernel/git/jmorris/linux-security
Pull IMA fixes from James Morris:
"These three patches fix regressions in the IMA code in your current
tree.
The first fixes a couple of bugs in template_desc_init_fields(), and
the other two ensure that changes in this kernel don't break
userspace"
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jmorris/linux-security:
ima: make a copy of template_fmt in template_desc_init_fields()
ima: do not send field length to userspace for digest of ima template
ima: do not include field length in template digest calc for ima template
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Pull non-transparent bridge updates from Jon Mason:
"NTB driver bug fixes to address a missed call to pci_enable_msix,
NTB-RP Link Up issue, Xeon Doorbell errata workaround, ntb_transport
link down race, and correct dmaengine_get/put usage.
Also, clean-ups to remove duplicate defines and document a hardware
errata. Finally, some changes to improve performance"
* tag 'ntb-3.13' of git://github.com/jonmason/ntb:
NTB: Disable interrupts and poll under high load
NTB: Enable Snoop on Primary Side
NTB: Document HW errata
NTB: remove duplicate defines
NTB: correct dmaengine_get/put usage
NTB: Fix ntb_transport link down race
ntb: Fix missed call to pci_enable_msix()
NTB: Fix NTB-RP Link Up
NTB: Xeon Doorbell errata workaround
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Commit f62805f1 introduced a bug where lazy MMU mode isn't exited if a
m2p_add/remove_override call fails.
Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Cc: Boris Ostrovsky <boris.ostrovsky@oracle.com>
Reviewed-by: David Vrabel <david.vrabel@citrix.com>
Reviewed-by: Anthony Liguori <aliguori@amazon.com>
Cc: xen-devel@lists.xenproject.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Matt Wilson <msw@amazon.com>
Signed-off-by: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
CC: stable@vger.kernel.org
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git://git.linaro.org/people/dlezcano/linux into timers/urgent
* Hide event stream Kconfig option for the arch_arm_timer for ARM=n
* Fix a missing a clk_put in case the registering of the sh_mtu[2] drivers fails.
* Reuse clockevents_config_and_register for the at91rm9200_time timer
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The low-power DSI clocks are used during host-driven transactions on the
DSI bus. Documentation recommends that they be children of PLLP and run
at a frequency of at least 52 MHz.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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This clock is needed to ensure the FUSE registers can be accessed
without freezing the system.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
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The clock for the PWM controller is slightly different from other
peripheral clocks on Tegra30. The clock source mux field start at
bit position 28 rather than 30.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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There are two GPUs on Tegra30 and each of them uses a separate clock, so
the secondary clock needs to be initialized in order for the gr3d module
to work properly.
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Add disp1 and disp2 clocks to the clock initialization table. These
clocks are required for display and HDMI support.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Adding suspend/resume function for tegra_cpu_car_ops. We only save and
restore the setting of the clock of CoreSight. Other clocks still need
to be taken care by clock driver.
Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
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Hook the functions for CPU hotplug support. After the CPU is hot
unplugged, the flow controller will handle to clock gate the CPU clock.
But still need to implement an empty function to avoid warning message.
Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
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Implement clock support for Tegra124.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
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Tegra124 introduces a number of new peripheral clocks. This patch adds those
to the common peripheral clock code.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
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Tegra124 introduces a number of a new clocks. Introduce the corresponding
the IDs for them.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
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Tegra124 has a clock which consists of a mux and a fractional divider.
Add support for this.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Tegra124 has periph clocks which share the hw register. Hence locking is
required.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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Tegra124 has an extra bank of peripheral clock registers. Add it to the
generic peripheral clock code.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
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Tegra124 introduces a new PLL type, PLLSS. Add support for it.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
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Move tegra20 to common tegra clock infrastructure.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
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Move tegra30 to common tegra clock infrastructure.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
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Introduce a common function which performs super clock initialization for
Tegra114 and beyond.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
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Introduce new files for fixed and PMC clocks common between several Tegra
SoCs and move Tegra114 to this new infrastructure.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
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