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2020-05-14clk: qcom: gcc: Add missing UFS clocks for SM8150Vinod Koul
Add the missing ufs card and ufs phy clocks for SM8150. They were missed in earlier addition of clock driver. Fixes: 2a1d7eb854bb ("clk: qcom: gcc: Add global clock controller driver for SM8150") Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lkml.kernel.org/r/20200513065420.32735-2-vkoul@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-14clk: qcom: gcc: Add GPU and NPU clocks for SM8150Vinod Koul
Add the GPU and NPU clocks for SM8150. They were missed in earlier addition of clock driver. Fixes: 2a1d7eb854bb ("clk: qcom: gcc: Add global clock controller driver for SM8150") Signed-off-by: Vinod Koul <vkoul@kernel.org> Link: https://lkml.kernel.org/r/20200513065420.32735-1-vkoul@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-14clk: qcom: mmcc-msm8996: Properly describe GPU_GX gdscBjorn Andersson
The GPU_GX GDSC depends on both GPU GDSC being enabled and that the VDD_GX rail is powered, so update the description of the node to cover these requirements. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lkml.kernel.org/r/20200417070044.1376212-3-bjorn.andersson@linaro.org Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-14clk: qcom: gdsc: Handle GDSC regulator suppliesBjorn Andersson
Certain GDSCs, such as the GPU_GX on MSM8996, requires that the upstream regulator supply is powered in order to be turned on. It's not guaranteed that the bootloader will leave these supplies on and the driver core will attempt to enable any GDSCs before allowing the individual drivers to probe defer on the PMIC regulator driver not yet being present. So the gdsc driver needs to be made aware of supplying regulators and probe defer on their absence, and it needs to enable and disable the regulator accordingly. Voltage adjustments of the supplying regulator are deferred to the client drivers themselves. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lkml.kernel.org/r/20200417070044.1376212-2-bjorn.andersson@linaro.org Reviewed-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-14Merge tag 'clk-meson-v5.8-1' of https://github.com/BayLibre/clk-meson into ↵Stephen Boyd
clk-amlogic Pull Amlogic clk driver updates from Jerome Brunet: - Meson8b: Updates and fixup HDMI and video clocks - Meson8b: Fixup reset polarity - Meson gx and g12: fix GPU glitch free mux switch * tag 'clk-meson-v5.8-1' of https://github.com/BayLibre/clk-meson: clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registers clk: meson: meson8b: Make the CCF use the glitch-free VPU mux clk: meson: meson8b: Fix the vclk_div{1, 2, 4, 6, 12}_en gate bits clk: meson: meson8b: Fix the polarity of the RESET_N lines clk: meson: meson8b: Fix the first parent of vid_pll_in_sel clk: meson: g12a: Prepare the GPU clock tree to change at runtime clk: meson: gxbb: Prepare the GPU clock tree to change at runtime clk: meson: meson8b: make the hdmi_sys clock tree mutable clk: meson8b: export the HDMI system clock
2020-05-14clk: ti: dra7xx: fix RNG clock parentTero Kristo
RNG is sourced from L4 clock. Add info for this for proper parenting of the clock. Signed-off-by: Tero Kristo <t-kristo@ti.com> Link: https://lkml.kernel.org/r/20200430083640.8621-4-t-kristo@ti.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-14clk: ti: dra7xx: mark MCAN clock as DRA76x onlyTero Kristo
This clock entry does not exist on any other devices except DRA76, so mark it as specific to that SoC only. Signed-off-by: Tero Kristo <t-kristo@ti.com> Link: https://lkml.kernel.org/r/20200430083640.8621-3-t-kristo@ti.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-14clk: ti: dra7xx: fix gpu clkctrl parentTero Kristo
gpu_cm:* parent clock name is wrong, replace this with correct gpu-clkctrl:* clock. Otherwise the clock ends up in the orphaned list. Signed-off-by: Tero Kristo <t-kristo@ti.com> Link: https://lkml.kernel.org/r/20200430083640.8621-2-t-kristo@ti.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-14clk: ti: omap5: Add proper parent clocks for l4-secure clocksTero Kristo
L4 secure clocks do not have their parents set currently, which ends them up to the orphan clock list. Fix this by adding either l3 or l4 clock as their parent. Signed-off-by: Tero Kristo <t-kristo@ti.com> Link: https://lkml.kernel.org/r/20200429131341.4697-4-t-kristo@ti.com Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-14clk: ti: omap4: Add proper parent clocks for l4-secure clocksTero Kristo
L4 secure clocks do not have their parents set currently, which ends them up to the orphan clock list. Fix this by adding either l3 or l4 clock as their parent. Signed-off-by: Tero Kristo <t-kristo@ti.com> Link: https://lkml.kernel.org/r/20200429131341.4697-3-t-kristo@ti.com Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-14clk: ti: composite: fix memory leakTero Kristo
The parent_names is never released for a component clock definition, causing some memory leak. Fix by releasing it once it is no longer needed. Reported-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Tero Kristo <t-kristo@ti.com> Link: https://lkml.kernel.org/r/20200429131341.4697-2-t-kristo@ti.com Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-13clk: samsung: Fix CLK_SMMU_FIMCL3 clock name on Exynos542xMarek Szyprowski
The proper name for CLK_SMMU_FIMCL3 is "smmu_fimcl3". Remove obvious typo. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2020-05-13clk: samsung: Mark top ISP and CAM clocks on Exynos542x as criticalMarek Szyprowski
The TOP 'aclk*_isp', 'aclk550_cam', 'gscl_wa' and 'gscl_wb' clocks must be kept enabled all the time to allow proper access to power management control for the ISP and CAM power domains. The last two clocks, although related to GScaler device and GSCL power domain, provides also the I_WRAP_CLK signal to MIPI CSIS0/1 devices, which are a part of CAM power domain and are needed for proper power on/off sequence. Currently there are no drivers for the devices, which are part of CAM and ISP power domains yet. This patch only fixes the race between disabling the unused power domains and disabling unused clocks, which randomly resulted in the following error during boot: Power domain CAM disable failed Power domain ISP disable failed Fixes: 318fa46cc60d ("clk/samsung: exynos542x: mark some clocks as critical") Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Acked-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2020-05-12clk: Move HAVE_CLK config out of architecture layerStephen Boyd
The implementation of 'struct clk' is not really an architectual detail anymore now that most architectures have migrated to the common clk framework. To sway new architecture ports away from trying to implement their own 'struct clk', move the config next to the common clk framework config. Cc: Russell King <linux@armlinux.org.uk> Cc: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20200409064416.83340-11-sboyd@kernel.org Reviewed-by: Arnd Bergmann <arnd@arndb.de>
2020-05-12MIPS: Loongson64: Drop asm/clock.h includeStephen Boyd
This include isn't used by this file, so just remove it. Acked-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Cc: Paul Burton <paulburton@kernel.org> Cc: <linux-mips@vger.kernel.org> Cc: <chenhc@lemote.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20200409064416.83340-10-sboyd@kernel.org Reviewed-by: Arnd Bergmann <arnd@arndb.de>
2020-05-12ARM: mmp: Remove legacy clk codeStephen Boyd
Remove all the legacy clk code that supports a non-common clk framework implementation of 'struct clk' in mach-mmp. This code doesn't look to be compiled anymore given that the MMP is fully supported in the multi-platform config via ARCH_MULTIPLATFORM as of commit 377524dc4d77 ("ARM: mmp: move into ARCH_MULTIPLATFORM"). The ARCH_MULTIPLATFORM config selects COMMON_CLK and therefore the Makefile rule can never actually compile the code in these files. Cc: Lubomir Rintel <lkundrak@v3.sk> Cc: Russell King <linux@armlinux.org.uk> Cc: <linux-arm-kernel@lists.infradead.org> Cc: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20200409064416.83340-9-sboyd@kernel.org Reviewed-by: Arnd Bergmann <arnd@arndb.de> [sboyd@kernel.org: Squash in a clock.h include removal found by Stephen Rothwell <sfr@canb.auug.org.au>]
2020-05-12clk: tegra: Add Tegra210 CSI TPG clock gateSowjanya Komatineni
Tegra210 CSI hardware internally uses PLLD for internal test pattern generator logic. PLLD_BASE register in CAR has a bit CSI_CLK_SOURCE to enable PLLD out to CSI during TPG mode. This patch adds this CSI TPG clock gate to Tegra210 clock driver to allow Tegra video driver to ungate CSI TPG clock during TPG mode and gate during non TPG mode. Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-05-12clk: tegra30: Use custom CCLK implementationDmitry Osipenko
We're going to use the generic cpufreq-dt driver on Tegra30 and thus CCLK intermediate re-parenting will be performed by the clock driver. There is now special CCLK implementation that supports all CCLK quirks, this patch makes Tegra30 SoCs to use that implementation. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Peter Geis <pgwipeout@gmail.com> Tested-by: Marcel Ziswiler <marcel@ziswiler.com> Tested-by: Jasper Korten <jja2000@gmail.com> Tested-by: David Heidelberg <david@ixit.cz> Tested-by: Nicolas Chauvet <kwizart@gmail.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-05-12clk: tegra20: Use custom CCLK implementationDmitry Osipenko
We're going to use the generic cpufreq-dt driver on Tegra20 and thus CCLK intermediate re-parenting will be performed by the clock driver. There is now special CCLK implementation that supports all CCLK quirks, this patch makes Tegra20 SoCs to use that implementation. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Peter Geis <pgwipeout@gmail.com> Tested-by: Marcel Ziswiler <marcel@ziswiler.com> Tested-by: Jasper Korten <jja2000@gmail.com> Tested-by: David Heidelberg <david@ixit.cz> Tested-by: Nicolas Chauvet <kwizart@gmail.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-05-12clk: tegra: cclk: Add helpers for handling PLLX rate changesDmitry Osipenko
CCLK should be re-parented away from PLLX if PLLX's rate is changing. The PLLP parent is a common safe CPU parent for all Tegra SoCs, thus CCLK will be re-parented to PLLP before PLLX rate-change begins and then switched back to PLLX after the rate-change completion. This patch adds helper functions which perform CCLK re-parenting, these helpers will be utilized by further patches. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Peter Geis <pgwipeout@gmail.com> Tested-by: Marcel Ziswiler <marcel@ziswiler.com> Tested-by: Jasper Korten <jja2000@gmail.com> Tested-by: David Heidelberg <david@ixit.cz> Tested-by: Nicolas Chauvet <kwizart@gmail.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-05-12clk: tegra: pll: Add pre/post rate-change hooksDmitry Osipenko
There is a need to temporarily re-parent CCLK away from PLLX if PLLX's rate is about to change. The newly introduced PLL pre/post rate-change hooks allow to handle such case. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Peter Geis <pgwipeout@gmail.com> Tested-by: Marcel Ziswiler <marcel@ziswiler.com> Tested-by: Jasper Korten <jja2000@gmail.com> Tested-by: David Heidelberg <david@ixit.cz> Tested-by: Nicolas Chauvet <kwizart@gmail.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-05-12clk: tegra: Add custom CCLK implementationDmitry Osipenko
CCLK stands for "CPU Clock", CPU core is running off CCLK. CCLK supports multiple parents, it has internal clock divider and a clock skipper. PLLX is the main CCLK parent that provides clock rates above 1GHz and it has special property such that the CCLK's internal divider is set into bypass mode when PLLX is selected as a parent for CCLK. This patch forks generic Super Clock into CCLK implementation which takes into account all CCLK specifics. The proper CCLK implementation is needed by the upcoming Tegra20 CPUFreq driver update that will allow to utilize the generic cpufreq-dt driver by moving intermediate clock selection into the clock driver. Note that technically this patch could be squashed into clk-super.c, but it is cleaner to have a separate source file. Also note that currently all CCLKLP bits are left in the clk-super.c and only CCLKG is supported by clk-tegra-super-cclk. It shouldn't be difficult to move the CCLKLP bits, but CCLKLP is not used by anything in kernel and thus better not to touch it for now. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Tested-by: Peter Geis <pgwipeout@gmail.com> Tested-by: Marcel Ziswiler <marcel@ziswiler.com> Tested-by: Jasper Korten <jja2000@gmail.com> Tested-by: David Heidelberg <david@ixit.cz> Tested-by: Nicolas Chauvet <kwizart@gmail.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-05-12clk: tegra: Remove the old emc_mux clock for Tegra210Joseph Lo
Remove the old emc_mux clock and don't use the common EMC clock definition. This will be replaced by a new clock defined in the EMC driver. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-05-12clk: tegra: Implement Tegra210 EMC clockJoseph Lo
The EMC clock needs to carefully coordinate with the EMC controller programming to make sure external memory can be properly clocked. Do so by hooking up the EMC clock with an EMC provider that will specify which rates are supported by the EMC and provide a callback to use for setting the clock rate at the EMC. Based on work by Peter De Schrijver <pdeschrijver@nvidia.com>. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-05-12clk: tegra: Export functions for EMC clock scalingJoseph Lo
Export functions to allow accessing the CAR register required by EMC clock scaling. These functions will be used to access the CAR register as part of the scaling sequence. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-05-12clk: tegra: Add PLLP_UD and PLLMB_UD for Tegra210Joseph Lo
Introduce the low jitter path of PLLP and PLLMB which can be used as EMC clock source. Signed-off-by: Joseph Lo <josephl@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-05-12clk: tegra: Rename Tegra124 EMC clock source fileThierry Reding
This code is only used on Tegra124, so rename it accordingly to make it more consistent with other file names. While at it, also get rid of the TEGRA_CLK_EMC Kconfig symbol that's really just an alias for TEGRA124_EMC. Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-05-12Merge branch 'for-5.8/dt-bindings' into for-5.8/clkThierry Reding
2020-05-12dt-bindings: clock: tegra: Add clock ID for CSI TPG clockSowjanya Komatineni
Tegra210 uses PLLD out internally for CSI TPG. This patch adds a clock ID for this CSI TPG clock from PLLD. Acked-by: Rob Herring <robh@kernel.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
2020-05-05clk: Allow the common clk framework to be selectableStephen Boyd
Enable build testing and configuration control of the common clk framework so that more code coverage and testing can be done on the common clk framework across various architectures. This also nicely removes the requirement that architectures must select the framework when they don't use it in architecture code. There's one snag with doing this, and that's making sure that randconfig builds don't select this option when some architecture or platform implements 'struct clk' outside of the common clk framework. Introduce a new config option 'HAVE_LEGACY_CLK' to indicate those platforms that haven't migrated to the common clk framework and therefore shouldn't be allowed to select this new config option. Also add a note that we hope one day to remove this config entirely. Based on a patch by Mark Brown <broonie@kernel.org>. Cc: Mark Brown <broonie@kernel.org> Cc: Geert Uytterhoeven <geert@linux-m68k.org> Cc: Mark Salter <msalter@redhat.com> Cc: Aurelien Jacquiot <jacquiot.aurelien@gmail.com> Cc: Jiaxun Yang <jiaxun.yang@flygoat.com> Cc: Guan Xuetao <gxt@pku.edu.cn> Cc: Russell King <linux@armlinux.org.uk> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Cc: Rich Felker <dalias@libc.org> Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: <linux-mips@vger.kernel.org> Cc: <linux-c6x-dev@linux-c6x.org> Cc: <linux-m68k@lists.linux-m68k.org> Cc: <linux-arm-kernel@lists.infradead.org> Cc: <linux-sh@vger.kernel.org> Link: https://lore.kernel.org/r/1470915049-15249-1-git-send-email-broonie@kernel.org Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20200409064416.83340-8-sboyd@kernel.org Reviewed-by: Mark Brown <broonie@kernel.org> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
2020-05-05mmc: meson-mx-sdio: Depend on OF_ADDRESS and not just OFStephen Boyd
Making COMMON_CLK a visible option causes the sparc allyesconfig to fail to build like so: sparc64-linux-ld: drivers/mmc/host/meson-mx-sdio.o: in function `meson_mx_mmc_remove': meson-mx-sdio.c:(.text+0x70): undefined reference to `of_platform_device_destroy' sparc64-linux-ld: drivers/mmc/host/meson-mx-sdio.o: in function `meson_mx_mmc_probe': meson-mx-sdio.c:(.text+0x9e4): undefined reference to `of_platform_device_create' sparc64-linux-ld: meson-mx-sdio.c:(.text+0xdd4): undefined reference to `of_platform_device_destroy' This is because the implementation of of_platform_device_destroy() is inside an #ifdef CONFIG_OF_ADDRESS section of drivers/of/platform.c. This driver already depends on OF being enabled, so let's tighten that constrain a little more so that it depends on OF_ADDRESS instead. This way we won't try to build this driver on platforms that don't have this function. Reported-by: kbuild test robot <lkp@intel.com> Cc: Neil Armstrong <narmstrong@baylibre.com> Cc: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Link: https://lkml.kernel.org/r/20200409064416.83340-7-sboyd@kernel.org Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
2020-05-05MIPS: Remove redundant CLKDEV_LOOKUP selectsStephen Boyd
The ATH79 config selects COMMON_CLK already, and the COMMON_CLK config option already selects CLKDEV_LOOKUP, and CLKDEV_LOOKUP already selects HAVE_CLK so it's redundant to have these selected again. Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de> Cc: <linux-mips@vger.kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Link: https://lkml.kernel.org/r/20200409064416.83340-6-sboyd@kernel.org
2020-05-05h8300: Remove redundant CLKDEV_LOOKUP selectsStephen Boyd
The h8300 architecture selects COMMON_CLK already, and the COMMON_CLK config option already selects CLKDEV_LOOKUP so it's redundant to have this selected again. Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Cc: uclinux-h8-devel@lists.sourceforge.jp Cc: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Link: https://lkml.kernel.org/r/20200409064416.83340-5-sboyd@kernel.org
2020-05-05arm64: tegra: Remove redundant CLKDEV_LOOKUP selectsStephen Boyd
The arm64 architecture selects COMMON_CLK at the toplevel ARM64 config. The COMMON_CLK config option already selects CLKDEV_LOOKUP so it's redundant to have this selected again for the Tegra specific config. Cc: Paul Walmsley <paul@pwsan.com> Acked-by: Thierry Reding <treding@nvidia.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> Cc: <linux-arm-kernel@lists.infradead.org> Cc: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Link: https://lkml.kernel.org/r/20200409064416.83340-4-sboyd@kernel.org
2020-05-05ARM: Remove redundant CLKDEV_LOOKUP selectsStephen Boyd
These platforms select COMMON_CLK indirectly through use of the ARCH_MULTIPLATFORM config option that they depend on implicitly via some V7/V6/V5 multi platform config option. The COMMON_CLK config option already selects CLKDEV_LOOKUP so it's redundant to have this selected again. Cc: Tony Prisk <linux@prisktech.co.nz> Cc: Russell King <linux@armlinux.org.uk> Cc: <linux-arm-kernel@lists.infradead.org> Cc: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Link: https://lkml.kernel.org/r/20200409064416.83340-3-sboyd@kernel.org
2020-05-05ARM: Remove redundant COMMON_CLK selectsStephen Boyd
The mulitplatform config already selects COMMON_CLK, so selecting it again is not useful. Remove these selects from ARM platforms that are part of the multiplatform build. Reviewed-by: "Andreas Färber" <afaerber@suse.de> # actions Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> # actions Cc: Russell King <linux@armlinux.org.uk> Cc: Alexander Shiyan <shc_work@mail.ru> Cc: Lubomir Rintel <lkundrak@v3.sk> Cc: <linux-arm-kernel@lists.infradead.org> Cc: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Link: https://lkml.kernel.org/r/20200409064416.83340-2-sboyd@kernel.org
2020-05-05Merge tag 'clk-renesas-for-v5.8-tag1' of ↵Stephen Boyd
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull Renesas clk driver updates from Geert Uytterhoeven: - Add support for the USB 2.0 clock selector on R-Car M3-W+ - Add support for the new RZ/G1H (R8A7742) SoC - Minor fixes and cleanups * tag 'clk-renesas-for-v5.8-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: clk: renesas: rcar-gen2: Remove superfluous CLK_RENESAS_DIV6 selects clk: renesas: cpg-mssr: Add R8A7742 support dt-bindings: clock: renesas: cpg-mssr: Document r8a7742 binding clk: renesas: Add r8a7742 CPG Core Clock Definitions dt-bindings: power: rcar-sysc: Add r8a7742 power domain index macros MAINTAINERS: Add DT Bindings for Renesas Clock Generators clk: renesas: r9a06g032: Fix some typo in comments dt-bindings: clock: renesas: rcar-usb2-clock-sel: Add r8a77961 support
2020-05-05clk: clk-xgene: Fix a typo in KconfigChristophe JAILLET
s/Sypport/Support Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Link: https://lkml.kernel.org/r/20200503190327.153249-1-christophe.jaillet@wanadoo.fr Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-05clk: Remove unused inline function clk_debug_reparentYueHaibing
There's no callers in-tree anymore. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Link: https://lkml.kernel.org/r/20200505083001.52564-1-yuehaibing@huawei.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2020-05-02clk: meson: meson8b: Don't rely on u-boot to init all GP_PLL registersMartin Blumenstingl
Not all u-boot versions initialize the HHI_GP_PLL_CNTL[2-5] registers. In that case all HHI_GPLL_PLL_CNTL[1-5] registers are 0x0 and when booting Linux the PLL fails to lock. The initialization sequence from u-boot is: - put the PLL into reset - write 0x59C88000 to HHI_GP_PLL_CNTL2 - write 0xCA463823 to HHI_GP_PLL_CNTL3 - write 0x0286A027 to HHI_GP_PLL_CNTL4 - write 0x00003000 to HHI_GP_PLL_CNTL5 - set M, N, OD and the enable bit - take the PLL out of reset - check if it has locked - disable the PLL In Linux we already initialize M, N, OD, the enable and the reset bits. Also the HHI_GP_PLL_CNTL[2-5] registers with these magic values (the exact meaning is unknown) so the PLL can lock when the vendor u-boot did not initialize these registers yet. Fixes: b882964b376f21 ("clk: meson: meson8b: add support for the GP_PLL clock on Meson8m2") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20200501215717.735393-1-martin.blumenstingl@googlemail.com
2020-04-30clk: renesas: rcar-gen2: Remove superfluous CLK_RENESAS_DIV6 selectsGeert Uytterhoeven
CLK_RENESAS_CPG_MSSR selects CLK_RENESAS_DIV6, and CLK_RCAR_GEN2_CPG selects CLK_RENESAS_CPG_MSSR, so there is no longer a need for the individual R-Car Gen2 clock driver options to select CLK_RENESAS_DIV6. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Link: https://lore.kernel.org/r/20200427193446.29738-1-geert+renesas@glider.be
2020-04-30clk: renesas: cpg-mssr: Add R8A7742 supportLad Prabhakar
Add RZ/G1H (R8A7742) Clock Pulse Generator / Module Standby and Software Reset support, using the CPG/MSSR driver core and the common R-Car Gen2 (and RZ/G) code. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Link: https://lore.kernel.org/r/1587998460-7804-1-git-send-email-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2020-04-29clk: meson: meson8b: Make the CCF use the glitch-free VPU muxMartin Blumenstingl
The "vpu_0" or "vpu_1" clock trees should not be updated while the clock is running. Enforce this by setting CLK_SET_RATE_GATE on the "vpu_0" and "vpu_1" gates. This makes the CCF switch to the "vpu_1" tree when "vpu_0" is currently active and vice versa, which is exactly what the vendor driver does when updating the frequency of the VPU clock. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20200417184127.1319871-5-martin.blumenstingl@googlemail.com
2020-04-29clk: meson: meson8b: Fix the vclk_div{1, 2, 4, 6, 12}_en gate bitsMartin Blumenstingl
The DIV{1,2,4,6,12}_EN bits are actually located in HHI_VID_CLK_CNTL register: - HHI_VID_CLK_CNTL[0] = DIV1_EN - HHI_VID_CLK_CNTL[1] = DIV2_EN - HHI_VID_CLK_CNTL[2] = DIV4_EN - HHI_VID_CLK_CNTL[3] = DIV6_EN - HHI_VID_CLK_CNTL[4] = DIV12_EN Update the bits accordingly so we will enable the bits in the correct register once we switch these clocks to be mutable. Fixes: 6cb57c678bb70e ("clk: meson: meson8b: add the read-only video clock trees") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20200417184127.1319871-4-martin.blumenstingl@googlemail.com
2020-04-29clk: meson: meson8b: Fix the polarity of the RESET_N linesMartin Blumenstingl
CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_POST and CLKC_RESET_VID_DIVIDER_CNTL_RESET_N_PRE are active low. This means: - asserting them requires setting the register value to 0 - de-asserting them requires setting the register value to 1 Set the register value accordingly for these two reset lines by setting the inverted the register value compared to all other reset lines. Fixes: 189621726bc2f6 ("clk: meson: meson8b: register the built-in reset controller") Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20200417184127.1319871-3-martin.blumenstingl@googlemail.com
2020-04-29clk: meson: meson8b: Fix the first parent of vid_pll_in_selMartin Blumenstingl
Use hdmi_pll_lvds_out as parent of the vid_pll_in_sel clock. It's not easy to see that the vendor kernel does the same, but it actually does. meson_clk_pll_ops in mainline still cannot fully recalculate all rates from the HDMI PLL registers because some register bits (at the time of writing it's unknown which bits are used for this) double the HDMI PLL output rate (compared to simply considering M, N and FRAC) for some (but not all) PLL settings. Update the vid_pll_in_sel parent so our clock calculation works for simple clock settings like the CVBS output (where no rate doubling is going on). The PLL ops need to be fixed later on for more complex clock settings (all HDMI rates). Fixes: 6cb57c678bb70 ("clk: meson: meson8b: add the read-only video clock trees") Suggested-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20200417184127.1319871-2-martin.blumenstingl@googlemail.com
2020-04-29dt-bindings: clocks: imx8mp: Add ids for audiomix clocksAbel Vesa
Add all the clock ids for the audiomix clocks. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-04-29clk: imx: Add helpers for passing the device as argumentAbel Vesa
All the imx clocks that need to be registered by the audiomix need to pass on the device so that the runtime PM support could work properly. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-04-29clk: imx: pll14xx: Add the device as argument when registeringAbel Vesa
In order to allow runtime PM, the device needs to be passed on to the register function. Audiomix clock controller, used on i.MX8MP and future platforms, registers a pll14xx and has runtime PM support. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2020-04-29clk: imx: gate2: Allow single bit gating clockAbel Vesa
Audiomix on i.MX8MP registers two gates that share the same enable count but use the same bit to control the gate instead of two bits. By adding the flag IMX_CLK_GATE2_SINGLE_BIT we allow the gate2 to use the generic gate ops for enable, disable and is_enabled. For the disable_unused, nothing happens if this flag is specified. Signed-off-by: Abel Vesa <abel.vesa@nxp.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
generated by cgit (git 2.34.1) at 2025-09-25 19:44:07 +0000