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2023-12-14drm/mediatek: Sort OVL adaptor componentsHsiao Chien Sung
Sort OVL adaptor components' names in alphabetical order. Reviewed-by: CK Hu <ck.hu@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com> Link: https://patchwork.kernel.org/project/dri-devel/patch/20231214055847.4936-17-shawn.sung@mediatek.com/ Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2023-12-14drm/mediatek: Start/Stop components with function pointersHsiao Chien Sung
By registering component related functions to the pointers, we can easily manage them within a for-loop and simplify the logic of component start/stop process. Reviewed-by: CK Hu <ck.hu@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com> Link: https://patchwork.kernel.org/project/dri-devel/patch/20231214055847.4936-16-shawn.sung@mediatek.com/ Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2023-12-14drm/mediatek: Power on/off devices with function pointersHsiao Chien Sung
Different from OVL, OVL adaptor is a pseudo device so we didn't define it in the device tree, consequently, pm_runtime_resume_and_get() called by .atomic_enable() powers on no device. For this reason, we implement a function to power on the RDMAs in OVL adaptor, and the system will make sure the IOMMUs are powered on as well because of the device link (iommus) in the RDMA nodes in DTS. This patch separates power and clock management process, it would be easier to maintain and add extensions. Reviewed-by: CK Hu <ck.hu@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com> Link: https://patchwork.kernel.org/project/dri-devel/patch/20231214055847.4936-15-shawn.sung@mediatek.com/ Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2023-12-14drm/mediatek: Manage component's clock with function pointersHsiao Chien Sung
By registering component related functions to the pointers, we can easily manage them within a for-loop and simplify the logic of clock control significantly. Reviewed-by: CK Hu <ck.hu@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com> Link: https://patchwork.kernel.org/project/dri-devel/patch/20231214055847.4936-14-shawn.sung@mediatek.com/ Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2023-12-14drm/mediatek: Add component ID to component match structureHsiao Chien Sung
Add component ID to component match structure so we can configure them with a for-loop. The main reason we do such code refactoring is that there is a new hardware component called "Padding" since MT8188, while MT8195 doesn't have this module, we can't use the original logic to manage the components. While MT8195 does not define Padding in the device tree, the corresponding components will be NULL and being skipped by the functions. Reviewed-by: CK Hu <ck.hu@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com> Link: https://patchwork.kernel.org/project/dri-devel/patch/20231214055847.4936-13-shawn.sung@mediatek.com/ Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2023-12-14drm/mediatek: Rename OVL_ADAPTOR_TYPE_RDMAHsiao Chien Sung
Rename OVL_ADAPTOR_TYPE_RDMA to OVL_ADAPTOR_TYPE_MDP_RDMA to align the naming rule of mtk_ovl_adaptor_comp_id. Reviewed-by: CK Hu <ck.hu@mediatek.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Hsiao Chien Sung <shawn.sung@mediatek.com> Link: https://patchwork.kernel.org/project/dri-devel/patch/20231214055847.4936-12-shawn.sung@mediatek.com/ Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
2023-12-14drm/i915/uapi: fix typos/spellos and punctuationRandy Dunlap
Use "its" for possessive form instead of "it's". Hyphenate multi-word adjectives. Correct some spelling. End one line of code with ';' instead of ','. The before and after object files are identical. Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: intel-gfx@lists.freedesktop.org Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231213044014.21410-1-rdunlap@infradead.org
2023-12-14drm/msm/dp: call dp_display_get_next_bridge() during probeDmitry Baryshkov
The funcion dp_display_get_next_bridge() can return -EPROBE_DEFER if the next bridge is not (yet) available. However returning -EPROBE_DEFER from msm_dp_modeset_init() is not ideal. This leads to -EPROBE return from component_bind, which can easily result in -EPROBE_DEFR loops. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Tested-by: Konrad Dybcio <konrad.dybcio@linaro.org> # sc8180x-primus Reviewed-by: Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by: Kuogee Hsieh <quic_khsieh@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/566208/ Link: https://lore.kernel.org/r/20231107004424.2112698-1-dmitry.baryshkov@linaro.org
2023-12-14drm/msm/dpu: Drop enable and frame_count parameters from dpu_hw_setup_misr()Jessica Zhang
Drop the enable and frame_count parameters from dpu_hw_setup_misr() as they are always set to the same values. In addition, replace MISR_FRAME_COUNT_MASK with MISR_FRAME_COUNT as frame_count is always set to the same value. Fixes: 7b37523fb1d1 ("drm/msm/dpu: Move MISR methods to dpu_hw_util") Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/572009/ Link: https://lore.kernel.org/r/20231213-encoder-fixup-v4-2-6da6cd1bf118@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-12-14drm/msm/dpu: Set input_sel bit for INTFJessica Zhang
Set the input_sel bit for encoders as it was missed in the initial implementation. Reported-by: Rob Clark <robdclark@gmail.com> Closes: https://gitlab.freedesktop.org/drm/msm/-/issues/39 Fixes: 91143873a05d ("drm/msm/dpu: Add MISR register support for interface") Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/572007/ Link: https://lore.kernel.org/r/20231213-encoder-fixup-v4-1-6da6cd1bf118@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-12-14drm/msm/dpu: move CSC tables to dpu_hw_util.cDmitry Baryshkov
Move CSC tables out of the header file to fix following kind of warnings: In file included from drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h:8, from drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c:5: drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h:54:33: warning: ‘dpu_csc10_rgb2yuv_601l’ defined but not used [-Wunused-const-variable=] 54 | static const struct dpu_csc_cfg dpu_csc10_rgb2yuv_601l = { | ^~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h:39:33: warning: ‘dpu_csc10_YUV2RGB_601L’ defined but not used [-Wunused-const-variable=] 39 | static const struct dpu_csc_cfg dpu_csc10_YUV2RGB_601L = { | ^~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h:24:33: warning: ‘dpu_csc_YUV2RGB_601L’ defined but not used [-Wunused-const-variable=] 24 | static const struct dpu_csc_cfg dpu_csc_YUV2RGB_601L = { | ^~~~~~~~~~~~~~~~~~~~ Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/571869/ Link: https://lore.kernel.org/r/20231213005728.53060-1-dmitry.baryshkov@linaro.org
2023-12-14drm/msm/dpu: Add mutex lock in control vblank irqPaloma Arellano
Add a mutex lock to control vblank irq to synchronize vblank enable/disable operations happening from different threads to prevent race conditions while registering/unregistering the vblank irq callback. v4: -Removed vblank_ctl_lock from dpu_encoder_virt, so it is only a parameter of dpu_encoder_phys. -Switch from atomic refcnt to a simple int counter as mutex has now been added v3: Mistakenly did not change wording in last version. It is done now. v2: Slightly changed wording of commit message Signed-off-by: Paloma Arellano <quic_parellan@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/571854/ Link: https://lore.kernel.org/r/20231212231101.9240-2-quic_parellan@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-12-14drm/msm/dpu: add cdm blocks to dpu snapshotAbhinav Kumar
Now that CDM block support has been added to DPU lets also add its entry to the DPU snapshot to help debugging. Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/571835/ Link: https://lore.kernel.org/r/20231212205254.12422-16-quic_abhinavk@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-12-14drm/msm/dpu: introduce separate wb2_format arrays for rgb and yuvAbhinav Kumar
Lets rename the existing wb2_formats array wb2_formats_rgb to indicate that it has only RGB formats and can be used on any chipset having a WB block. Introduce a new wb2_formats_rgb_yuv array to the catalog to indicate support for YUV formats to writeback in addition to RGB. Chipsets which have support for CDM block will use the newly added wb2_formats_rgb_yuv array. changes in v3: - change type of wb2_formats_rgb/wb2_formats_rgb_yuv to u32 to fix checkpatch warnings Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/571837/ Link: https://lore.kernel.org/r/20231212205254.12422-15-quic_abhinavk@quicinc.com [DB: fixed newer catalog entries] Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-12-14drm/msm/dpu: reserve cdm blocks for writeback in case of YUV outputAbhinav Kumar
Reserve CDM blocks for writeback if the format of the output fb is YUV. At the moment, the reservation is done only for writeback but can easily be extended by relaxing the checks once other interfaces are ready to output YUV. changes in v3: - squash CDM disable during encoder cleanup into this change changes in v2: - use needs_cdm from topology struct - drop fb related checks from atomic_mode_set() Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/571838/ Link: https://lore.kernel.org/r/20231212205254.12422-14-quic_abhinavk@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-12-14drm/msm/dpu: plug-in the cdm related bits to writeback setupAbhinav Kumar
To setup and enable CDM block for the writeback pipeline, lets add the pieces together to set the active bits and the flush bits for the CDM block. changes in v2: - passed the cdm idx to update_pending_flush_cdm() (have retained the R-b as its a minor change) Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/571831/ Link: https://lore.kernel.org/r/20231212205254.12422-13-quic_abhinavk@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-12-14drm/msm/dpu: add an API to setup the CDM block for writebackAbhinav Kumar
Add an API dpu_encoder_helper_phys_setup_cdm() which can be used by the writeback encoder to setup the CDM block. Currently, this is defined and used within the writeback's physical encoder layer however, the function can be modified to be used to setup the CDM block even for non-writeback interfaces. Until those modifications are planned and made, keep it local to writeback. changes in v3: - call bind_pingpong_blk() directly as disable() is dropped - add dpu_csc10_rgb2yuv_601l to dpu_hw_util.h and use it - fix kbot error on the function doc - document that dpu_encoder_helper_phys_setup_cdm() doesn't handle DPU_CHROMA_H1V2 changes in v2: - add the RGB2YUV CSC matrix to dpu util as needed by CDM - use dpu_hw_get_csc_cfg() to get and program CSC - drop usage of setup_csc_data() and setup_cdwn() cdm ops as they both have been merged into enable() - drop reduntant hw_cdm and hw_pp checks Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202312102149.qmbCdsg2-lkp@intel.com/ Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/571833/ Link: https://lore.kernel.org/r/20231212205254.12422-12-quic_abhinavk@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-12-14drm/msm/dpu: add CDM related logic to dpu_hw_ctl layerAbhinav Kumar
CDM block will need its own logic to program the flush and active bits in the dpu_hw_ctl layer. Make necessary changes in dpu_hw_ctl to support CDM programming. changes in v3: - drop unused cdm_active as reported by kbot - retained the R-b as its a trivial change changes in v2: - remove unused empty line - pass in cdm_num to update_pending_flush_cdm() Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202312102047.S0I69pCs-lkp@intel.com/ Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/571829/ Link: https://lore.kernel.org/r/20231212205254.12422-11-quic_abhinavk@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-12-14drm/msm/dpu: add support to allocate CDM from RMAbhinav Kumar
Even though there is usually only one CDM block, it can be used by either HDMI, DisplayPort OR Writeback interfaces. Hence its allocation needs to be tracked properly by the resource manager to ensure appropriate availability of the block. changes in v2: - move needs_cdm to topology struct Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/571827/ Link: https://lore.kernel.org/r/20231212205254.12422-10-quic_abhinavk@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-12-14drm/msm/dpu: add cdm blocks to RMAbhinav Kumar
Add the RM APIs necessary to initialize and allocate CDM blocks to be used by the rest of the DPU pipeline. changes in v2: - treat cdm_init() failure as fatal - fixed the commit text Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/571822/ Link: https://lore.kernel.org/r/20231212205254.12422-9-quic_abhinavk@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-12-14drm/msm/dpu: add dpu_hw_cdm abstraction for CDM blockAbhinav Kumar
CDM block comes with its own set of registers and operations which can be done. In-line with other hardware blocks, this change adds the dpu_hw_cdm abstraction for the CDM block. changes in v4: - used FIELD_PREP() for dpu_hw_cdm_setup_cdwn() operations - change to lowercase hex in dpu_hw_cdm_bind_pingpong_blk() - move disable assignment inside else in dpu_hw_cdm_bind_pingpong_blk() changes in v3: - fix commit text from sub-blk to blk for CDM - fix kbot issue for missing static for dpu_hw_cdm_enable() - fix kbot issue for incorrect documentation style - add more documentation for enums and struct in dpu_hw_cdm.h - drop "enable" parameter from bind_pingpong_blk() as we can just use PINGPONG_NONE for disable cases - drop unnecessary bit operation for zero value of cdm_cfg changes in v2: - replace bit magic with relevant defines - use drmm_kzalloc instead of kzalloc/free - some formatting fixes - inline _setup_cdm_ops() - protect bind_pingpong_blk with core_rev check - drop setup_csc_data() and setup_cdwn() ops as they are merged into enable() Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202312101815.B3ZH7Pfy-lkp@intel.com/ Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/571824/ Link: https://lore.kernel.org/r/20231212205254.12422-8-quic_abhinavk@quicinc.com [DB: Added linux/bitfield.h inclusion] Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-12-14drm/msm/dpu: add cdm blocks to sm8250 dpu_hw_catalogAbhinav Kumar
Add CDM blocks to the sm8250 dpu_hw_catalog to support YUV format output from writeback block. changes in v2: - re-use the cdm definition from sc7280 Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/571819/ Link: https://lore.kernel.org/r/20231212205254.12422-7-quic_abhinavk@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-12-14drm/msm/dpu: add cdm blocks to sc7280 dpu_hw_catalogAbhinav Kumar
Add CDM blocks to the sc7280 dpu_hw_catalog to support YUV format output from writeback block. changes in v3: - change the comment from sub-blk to clk for CDM changes in v2: - remove explicit zero assignment for features - move sc7280_cdm to dpu_hw_catalog from the sc7280 catalog file as its definition can be re-used Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/571818/ Link: https://lore.kernel.org/r/20231212205254.12422-6-quic_abhinavk@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-12-14drm/msm/dpu: move csc matrices to dpu_hw_utilAbhinav Kumar
Since the type and usage of CSC matrices is spanning across DPU lets introduce a helper to the dpu_hw_util to return the CSC corresponding to the request type. This will help to add more supported CSC types such as the RGB to YUV one which is used in the case of CDM. changes in v3: - drop the extra wrapper and export the matrices directly Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/571816/ Link: https://lore.kernel.org/r/20231212205254.12422-5-quic_abhinavk@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-12-14drm/msm/dpu: fix writeback programming for YUV casesAbhinav Kumar
For YUV cases, setting the required format bits was missed out in the register programming. Lets fix it now in preparation of adding YUV formats support for writeback. changes in v2: - dropped the fixes tag as its not a fix but adding new functionality Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/571814/ Link: https://lore.kernel.org/r/20231212205254.12422-4-quic_abhinavk@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-12-14drm/msm/dpu: rename dpu_encoder_phys_wb_setup_cdp to match its functionalityAbhinav Kumar
dpu_encoder_phys_wb_setup_cdp() is not programming the chroma down prefetch block. Its setting up the display ctl path for writeback. Hence rename it to dpu_encoder_phys_wb_setup_ctl() to match what its actually doing. Fixes: d7d0e73f7de3 ("drm/msm/dpu: introduce the dpu_encoder_phys_* for writeback") Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/571812/ Link: https://lore.kernel.org/r/20231212205254.12422-3-quic_abhinavk@quicinc.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-12-14drm/msm/dpu: add formats check for writeback encoderAbhinav Kumar
In preparation for adding more formats to dpu writeback add format validation to it to fail any unsupported formats. changes in v4: - change the failure message of the API drm_atomic_helper_check_wb_connector_state() to a generic one in case it checks more errors later and moreoever it already has debug message to indicate its failure - change the corresponding DPU_ERROR to DPU_DEBUG in-line with other atomic_check failure messages changes in v3: - rebase on top of msm-next - replace drm_atomic_helper_check_wb_encoder_state() with drm_atomic_helper_check_wb_connector_state() due to the rebase changes in v2: - correct some grammar in the commit text Fixes: d7d0e73f7de3 ("drm/msm/dpu: introduce the dpu_encoder_phys_* for writeback") Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/571811/ Link: https://lore.kernel.org/r/20231212205254.12422-2-quic_abhinavk@quicinc.com [DB: removed extra debug message] Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-12-14drm/msm/dpu: remove extra drm_encoder_cleanup from the error pathDmitry Baryshkov
The drmm handler will perform drm_encoder_cleanup() for us. Moreover if we call drm_encoder_cleanup() manually, the drmm_encoder_alloc_release() will spawn warnings at drivers/gpu/drm/drm_encoder.c:214. Drop these extra drm_encoder_cleanup() calls. Fixes: cd42c56d9c0b ("drm/msm/dpu: use drmm-managed allocation for dpu_encoder_virt") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reported-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Tested-by: Abhinav Kumar <quic_abhinavk@quicinc.com> #sm8250 CI Patchwork: https://patchwork.freedesktop.org/patch/571562/ Link: https://lore.kernel.org/r/20231211145440.3647001-1-dmitry.baryshkov@linaro.org
2023-12-14dt-bindings: display: msm: dp: declare compatible string for sm8150Dmitry Baryshkov
Add compatible string for the DisplayPort controller found on the Qualcomm SM8150 platform. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/571438/ Link: https://lore.kernel.org/r/20231209232132.3580045-2-dmitry.baryshkov@linaro.org
2023-12-14drm/msm/dpu: Ratelimit framedone timeout msgsRob Clark
When we start getting these, we get a *lot*. So ratelimit it to not flood dmesg. Signed-off-by: Rob Clark <robdclark@chromium.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org> Patchwork: https://patchwork.freedesktop.org/patch/571584/ Link: https://lore.kernel.org/r/20231211182000.218088-1-robdclark@gmail.com Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
2023-12-14drm/msm/dpu: enable writeback on SM8450Dmitry Baryshkov
Enable WB2 hardware block, enabling writeback support on this platform. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/570187/ Link: https://lore.kernel.org/r/20231203002743.1291956-4-dmitry.baryshkov@linaro.org
2023-12-14drm/msm/dpu: enable writeback on SM8350Dmitry Baryshkov
Enable WB2 hardware block, enabling writeback support on this platform. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> Patchwork: https://patchwork.freedesktop.org/patch/570188/ Link: https://lore.kernel.org/r/20231203002743.1291956-3-dmitry.baryshkov@linaro.org
2023-12-13drm/amdgpu: warn when there are still mappings when a BO is destroyed v2Christian König
This can only happen when there is a reference counting bug. v2: fix typo Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/radeon: Prevent multiple debug error lines on suspendWoody Suwalski
Fix to avoid multiple debug error lines printed on every suspend by Radeon driver's debugfs. radeon_debugfs_init() calls debugfs_create_file() for every ring. This results in printing multiple error lines to the screen and dmesg similar to this: [   92.378726] debugfs: File 'radeon_ring_gfx' in directory '0000:00:01.0' already present! [   92.378732] debugfs: File 'radeon_ring_cp1' in directory '0000:00:01.0' already present! [   92.378734] debugfs: File 'radeon_ring_cp2' in directory '0000:00:01.0' already present! [   92.378737] debugfs: File 'radeon_ring_dma1' in directory '0000:00:01.0' already present! [   92.378739] debugfs: File 'radeon_ring_dma2' in directory '0000:00:01.0' already present! [   92.380775] debugfs: File 'radeon_ring_uvd' in directory '0000:00:01.0' already present! [   92.406620] debugfs: File 'radeon_ring_vce1' in directory '0000:00:01.0' already present! [   92.406624] debugfs: File 'radeon_ring_vce2' in directory '0000:00:01.0' already present! Patch v1: The fix was to run lookup() for the file before trying to (re)create that debug file. Patch v2: Call the radeon_debugfs_init() only once when radeon ring is initialized (as suggested by Christian K. - thanks) Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Woody Suwalski <terraluna977@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/amd/display: add plane shaper TF supportMelissa Wen
Enable usage of predefined transfer func in addition to shaper 1D LUT. That means we can save some complexity by just setting a predefined curve, instead of programming a custom curve when preparing color space for applying 3D LUT. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Melissa Wen <mwen@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/amd/display: add plane shaper LUT supportMelissa Wen
Map DC shaper LUT to DM plane color management. Shaper LUT can be used to delinearize and/or normalize the color space for computational efficiency and achiving specific visual styles. If a plane degamma is apply to linearize the color space, a custom shaper 1D LUT can be used just before applying 3D LUT. v2: - use DPP color caps to verify plane 3D LUT support - add debug message if shaper LUT programming fails v4: - remove helper to check 3D LUT color caps (Harry) - update desc of lut3d-setup helper from MPC to DPP v5: - remove color_mgmt_changed check that prevents color updates (Joshua) Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Melissa Wen <mwen@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/amd/display: add HDR multiplier supportJoshua Ashton
With `dc_fixpt_from_s3132()` translation, we can just use it to set hdr_mult. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Joshua Ashton <joshua@froggi.es> Signed-off-by: Melissa Wen <mwen@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/amd/display: add dc_fixpt_from_s3132 helperJoshua Ashton
Detach value translation from CTM to reuse it for programming HDR multiplier property. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Joshua Ashton <joshua@froggi.es> Signed-off-by: Melissa Wen <mwen@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/amd/display: reject atomic commit if setting both plane and CRTC degammaMelissa Wen
DC only has pre-blending degamma caps (plane/DPP) that is currently in use for CRTC/post-blending degamma, so that we don't have HW caps to perform plane and CRTC degamma at the same time. Reject atomic updates when serspace sets both plane and CRTC degamma properties. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Melissa Wen <mwen@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/amd/display: add plane degamma TF and LUT supportJoshua Ashton
Set DC plane with user degamma LUT or predefined TF from driver-specific plane color properties. If plane and CRTC degamma are set in the same time, plane degamma has priority. That means, we only set CRTC degamma if we don't have plane degamma LUT or TF to configure. We return -EINVAL if we don't have plane degamma settings, so we can continue and check CRTC degamma. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Joshua Ashton <joshua@froggi.es> Signed-off-by: Melissa Wen <mwen@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/amdgpu: fix tear down order in amdgpu_vm_pt_freeChristian König
When freeing PD/PT with shadows it can happen that the shadow destruction races with detaching the PD/PT from the VM causing a NULL pointer dereference in the invalidation code. Fix this by detaching the the PD/PT from the VM first and then freeing the shadow instead. Signed-off-by: Christian König <christian.koenig@amd.com> Fixes: https://gitlab.freedesktop.org/drm/amd/-/issues/2867 Cc: <stable@vger.kernel.org> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/amd/display: decouple steps for mapping CRTC degamma to DC planeMelissa Wen
The next patch adds pre-blending degamma to AMD color mgmt pipeline, but pre-blending degamma caps (DPP) is currently in use to provide DRM CRTC atomic degamma or implict degamma on legacy gamma. Detach degamma usage regarging CRTC color properties to manage plane and CRTC color correction combinations. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Melissa Wen <mwen@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/amd/display: mark plane as needing reset if color props changeJoshua Ashton
We should reset a plane state if at least one of the color management properties differs from old and new state. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Joshua Ashton <joshua@froggi.es> Co-developed-by: Melissa Wen <mwen@igalia.com> Signed-off-by: Melissa Wen <mwen@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/amd/display: set sdr_ref_white_level to 80 for out_transfer_funcJoshua Ashton
Otherwise this is just initialized to 0. This needs to actually have a value so that compute_curve can work for PQ EOTF. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Joshua Ashton <joshua@froggi.es> Co-developed-by: Melissa Wen <mwen@igalia.com> Signed-off-by: Melissa Wen <mwen@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/amd: include drm/drm_edid.h only where neededJani Nikula
Including drm_edid.h from amdgpu_mode.h causes the rebuild of literally hundreds of files when drm_edid.h is modified, while there are only a handful of files that actually need to include drm_edid.h. Signed-off-by: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/amd/display: add CRTC gamma TF supportJoshua Ashton
Add predefined transfer function programming. There is no post-blending out gamma ROM for hardcoded curves, but we can use AMD color modules to program LUT parameters from pre-defined coefficients and an empty regamma LUT (or bump up LUT parameters with pre-defined TF values). v2: - update crtc color mgmt if regamma TF differs between states (Joshua) - map inverse EOTF to DC transfer function (Melissa) v3: - update AMDGPU TF list v4: - update comment regarding regamma behavior Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Joshua Ashton <joshua@froggi.es> Co-developed-by: Melissa Wen <mwen@igalia.com> Signed-off-by: Melissa Wen <mwen@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/amd/display: encapsulate atomic regamma operationMelissa Wen
We will wire up MPC 3D LUT to DM CRTC color pipeline in the next patch, but so far, only for atomic interface. By checking set_output_transfer_func in DC drivers with MPC 3D LUT support, we can verify that regamma is only programmed when 3D LUT programming fails. As a groundwork to introduce 3D LUT programming and better understand each step, detach atomic regamma programming from the crtc colocr updating code. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Melissa Wen <mwen@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/amd/display: add comments to describe DM crtc color mgmt behaviorMelissa Wen
Describe some expected behavior of the AMD DM color mgmt programming. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Melissa Wen <mwen@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/amd/display: add CRTC gamma TF driver-specific propertyMelissa Wen
Add AMD pre-defined transfer function property to default DRM CRTC gamma to convert to wire encoding with or without a user gamma LUT. There is no post-blending regamma ROM for pre-defined TF. When setting Gamma TF (!= Identity) and LUT at the same time, the color module will combine the pre-defined TF and the custom LUT values into the LUT that's actually programmed. v2: - enable CRTC prop in the end of driver-specific prop sequence - define inverse EOTFs as supported regamma TFs - reword driver-specific function doc to remove shaper/3D LUT v3: - spell out TF+LUT behavior in the commit and comments (Harry) Reviewed-by: Harry Wentland <harry.wentland@amd.com> Co-developed-by: Joshua Ashton <joshua@froggi.es> Signed-off-by: Joshua Ashton <joshua@froggi.es> Signed-off-by: Melissa Wen <mwen@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2023-12-13drm/amd/display: add plane blend LUT and TF driver-specific propertiesJoshua Ashton
Blend 1D LUT or a pre-defined transfer function (TF) can be set to linearize content before blending, so that it's positioned just before blending planes in the AMD color mgmt pipeline, and after 3D LUT (non-linear space). Shaper and Blend LUTs are 1D LUTs that sandwich 3D LUT. Drivers should advertize blend properties according to HW caps. There is no blend ROM for pre-defined TF. When setting blend TF (!= Identity) and LUT at the same time, the color module will combine the pre-defined TF and the custom LUT values into the LUT that's actually programmed. v3: - spell out TF+LUT behavior in the commit and comments (Harry) v5: - get blend blob correctly Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Joshua Ashton <joshua@froggi.es> Signed-off-by: Melissa Wen <mwen@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit (git 2.34.1) at 2025-10-03 12:30:30 +0000