| Age | Commit message (Collapse) | Author |
|---|
|
Now that the dt-binding has been extended to allow indicating the bit
position the following warning about a duplicate unit address with W=1
can be fixed:
arch/arm64/boot/dts/apple/t8103.dtsi:764.46-767.8: Warning (unique_unit_address_if_enabled): /soc/spmi@23d0d9300/pmic@f/nvmem-layout/boot-error-count@9f02: duplicate unit-address (also used in node /soc/spmi@23d0d9300/pmic@f/nvmem-layout/panic-count@9f02)
Fixes: d8bf82081c9e ("arm64: dts: apple: Add PMIC NVMEM")
Link: https://lore.kernel.org/r/20250610-nvmem-bit-pattern-v1-2-55ed5c1b369c@kernel.org
Signed-off-by: Sven Peter <sven@kernel.org>
|
|
Patches from Peter Chen <peter.chen@cixtech.com>:
Cixtech P1 (internal name sky1) is high performance generic Armv9 SoC.
Orion O6 is the Arm V9 Motherboard built by Radxa. You could find brief
introduction for SoC and related boards at:
https://radxa.com/products/orion/o6#overview
Currently, to run upstream kernel at Orion O6 board, you need to
use BIOS released by Radxa, and add "clk_ignore_unused=1" at bootargs.
https://docs.radxa.com/en/orion/o6/bios/install-bios
In this series, we add initial SoC and board support for Kernel building.
Since mailbox is used for SCMI clock communication, mailbox driver is added
in this series for the minimum SoC support.
Patch 1-2: add dt-binding doc for CIX and its sky1 SoC
Patch 3: add Arm64 build support
Patch 4-5: add CIX mailbox driver which needs to support SCMI clock protocol.
Patch 6: add Arm64 defconfig support
Patch 7-8: add initial dts support for SoC and Orion O6 board
Patch 9: add MAINTAINERS entry
* newsoc/cix-p1:
MAINTAINERS: Add CIX SoC maintainer entry
arm64: dts: cix: Add sky1 base dts initial support
dt-bindings: clock: cix: Add CIX sky1 scmi clock id
arm64: defconfig: Enable CIX SoC
mailbox: add CIX mailbox driver
dt-bindings: mailbox: add cix,sky1-mbox
arm64: Kconfig: add ARCH_CIX for cix silicons
dt-bindings: arm: add CIX P1 (SKY1) SoC
dt-bindings: vendor-prefixes: Add CIX Technology Group Co., Ltd.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
|
Using this entry as the maintainers information for CIX SoCs.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Fugang Duan <fugang.duan@cixtech.com>
Signed-off-by: Peter Chen <peter.chen@cixtech.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
|
CIX SKY1 SoC is high performance Armv9 SoC designed by Cixtech,
and Orion O6 is the motherboard launched by Radxa. See below for
detail:
https://docs.radxa.com/en/orion/o6/getting-started/introduction
In this commit, it only adds limited components for running initramfs
at Orion O6.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Tested-by: Enric Balletbo i Serra <eballetb@redhat.com>
Tested-by: Kajetan Puchalski <kajetan.puchalski@arm.com>
Signed-off-by: Peter Chen <peter.chen@cixtech.com>
Signed-off-by: Guomin Chen <Guomin.Chen@cixtech.com>
Signed-off-by: Gary Yang <gary.yang@cixtech.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
|
Add device tree bindings for the scmi clock id on
Cix sky1 platform.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Peter Chen <peter.chen@cixtech.com>
Signed-off-by: Gary Yang <gary.yang@cixtech.com>
Signed-off-by: Peter Chen <peter.chen@cixtech.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
|
- Enable CIX SoC support at ARM64 defconfig
- Enable CIX mailbox
At CIX SoC platforms, the clock handling uses Arm SCMI protocol,
the physical clock access is at sub processor, so it needs to enable
mailbox by default.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Peter Chen <peter.chen@cixtech.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
|
The CIX mailbox controller, used in the Cix SoCs, like sky1.
facilitates message transmission between multiple processors
within the SoC, such as the AP, PM, audio DSP, SensorHub MCU,
and others.
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
Reviewed-by: Peter Chen <peter.chen@cixtech.com>
Signed-off-by: Guomin Chen <Guomin.Chen@cixtech.com>
Signed-off-by: Gary Yang <gary.yang@cixtech.com>
Signed-off-by: Lihua Liu <Lihua.Liu@cixtech.com>
Signed-off-by: Peter Chen <peter.chen@cixtech.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
|
Add a dt-binding for the Cixtech Mailbox Controller.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Peter Chen <peter.chen@cixtech.com>
Signed-off-by: Guomin Chen <Guomin.Chen@cixtech.com>
Signed-off-by: Lihua Liu <Lihua.Liu@cixtech.com>
Signed-off-by: Peter Chen <peter.chen@cixtech.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
|
Add ARCH_CIX for CIX SoC series support.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Fugang Duan <fugang.duan@cixtech.com>
Signed-off-by: Peter Chen <peter.chen@cixtech.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
|
Add device tree bindings for CIX P1 (Internal name sky1) Arm SoC,
it consists several SoC models like CP8180, CD8180, etc.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Fugang Duan <fugang.duan@cixtech.com>
Signed-off-by: Peter Chen <peter.chen@cixtech.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
|
CIX Technology Group Co., Ltd. is a high performance Arm SoC design
company. Link: https://www.cixtech.com/.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Fugang Duan <fugang.duan@cixtech.com>
Signed-off-by: Peter Chen <peter.chen@cixtech.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
|
Patches from Ben Zong-You Xie <ben717@andestech.com>:
The Voyager is a 9.6” x 9.6” Micro ATX form factor development board
including Andes QiLai SoC. This patch series adds minimal device tree
files for the QiLai SoC and the Voyager board [1].
Now only support basic uart drivers to boot up into a basic console. Other
features will be added later.
[1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/
[2] https://lore.kernel.org/all/20250602060747.689824-1-ben717@andestech.com/
* newsoc/andes:
MAINTAINERS: Add entry for Andes SoC
riscv: defconfig: enable Andes SoC
riscv: dts: andes: add Voyager board device tree
riscv: dts: andes: add QiLai SoC device tree
dt-bindings: timer: add Andes machine timer
dt-bindings: interrupt-controller: add Andes machine-level software interrupt controller
dt-bindings: interrupt-controller: add Andes QiLai PLIC
dt-bindings: riscv: add Andes QiLai SoC and the Voyager board bindings
riscv: add Andes SoC family Kconfig support
|
|
https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt
MediaTek ARM64 DeviceTree updates for v6.17
This adds new machines and improves support for already supported
MediaTek SoCs.
In particular:
- New machine: MT8186 Steelix Squirtle Chromebook
- Steelix-Voltorb's two dts are merged in one
...and improvements for already supported SoCs and machines:
- Added reserved memory for AFE DMA for MT8173/83/86/92,
aligning audio related memory allocation between all of
the Chromebook SoCs
- Added second source components for Steelix, and marked the
multiple trackpads for Asurada as such
- MediaTek Genio 1200: Enabled support for the Audio DSP and sound
- MediaTek Genio 510/700/1200: Added support for the PMIC Keys
- MediaTek MT7988: Added Cache Coherent Interconnect for CPU DVFS
- MT7988A-BananaPi-R4: Enabled CCI, added GPIO LEDs
- Airoha EN7581: Added ethernet nodes to Evaluation Board
* tag 'mtk-dts64-for-v6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux:
arm64: dts: mediatek: mt8395-genio-1200-evk: Add MT6359 PMIC key support
arm64: dts: mediatek: mt8390-genio-common: Add Home MT6359 PMIC key support
arm64: dts: mediatek: mt7988a-bpi-r4: add gpio leds
arm64: dts: mediatek: mt7988a-bpi-r4: drop unused pins
arm64: dts: mediatek: mt7988a-bpi-r4: add proc-supply for cci
arm64: dts: mediatek: mt7988: add cci node
dt-bindings: interconnect: add mt7988-cci compatible
arm64: dts: airoha: en7581: Add ethernet nodes to EN7581 SoC evaluation board
arm64: dts: mediatek: mt8192-asurada-spherion: Mark trackpads as fail-needs-probe
arm64: dts: mediatek: mt8186: Add Squirtle Chromebooks
arm64: dts: mediatek: mt8186: Merge Voltorb device trees
arm64: dts: mediatek: mt8186-steelix: Mark second source components for probing
dt-bindings: arm: mediatek: Add MT8186 Squirtle Chromebooks
dt-bindings: arm: mediatek: Merge MT8186 Voltorb entries
arm64: dts: mediatek: mt8395-genio-1200-evk: Enable Audio DSP and sound card
arm64: dts: mediatek: mt8192-asurada: Reserve memory for audio frontend
arm64: dts: mediatek: mt8186-corsola: Reserve memory for audio frontend
arm64: dts: mediatek: mt8183-kukui: Reserve memory for audio frontend
arm64: dts: mediatek: mt8173: Reserve memory for audio frontend
Link: https://lore.kernel.org/r/20250711083656.33538-3-angelogioacchino.delregno@collabora.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
|
https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/dt
MediaTek mach ARM32 updates
This adds support for the MediaTek MT6572 SoC, found in various
old smartphones and tablets from various manufacturers.
In particular, this adds a board_dt_compat entry for this SoC
and its SMP bring up sequence to enable secondary cores.
* tag 'mtk-dts32-for-v6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux:
ARM: dts: mediatek: add basic support for Lenovo A369i board
ARM: dts: mediatek: add basic support for JTY D101 board
ARM: dts: mediatek: add basic support for MT6572 SoC
dt-bindings: arm: mediatek: add boards based on the MT6572 SoC
dt-bindings: vendor-prefixes: add JTY
dt-bindings: watchdog: mediatek,mtk-wdt: add MT6572
dt-bindings: interrupt-controller: mediatek,mt6577-sysirq: add MT6572
Link: https://lore.kernel.org/r/20250711083656.33538-2-angelogioacchino.delregno@collabora.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
|
https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap into soc/dt
arm: dts: OMAP updates for v6.17
- new board support: Seeed BeagleBone Green Eco
- misc. fixups / cleanups
* tag 'omap-for-v6.17/dt-signed' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap:
arm: dts: ti: omap: Fixup pinheader typo
ARM: dts: am335x-pdu001: Fix RS-485 transceiver switching
arm: dts: omap: Add support for BeagleBone Green Eco board
dt-bindings: omap: Add Seeed BeagleBone Green Eco
arm: dts: omap: am335x-bone-common: Rename tps to generic pmic node
Revert "ARM: dts: Update pcie ranges for dra7"
ARM: dts: omap: am335x: Use non-deprecated rts-gpios
Link: https://lore.kernel.org/r/7h7c0gxczy.fsf@baylibre.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
|
This patch removed the code where num_sources should be the same as cn_list.
For better resilience, it would be preferable to explicitly add the route
mapping the input pins to this MU entity.
Signed-off-by: Shuming Fan <shumingf@realtek.com>
Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Link: https://patch.msgid.link/20250721112346.388542-1-shumingf@realtek.com
Signed-off-by: Mark Brown <broonie@kernel.org>
|
|
One initial setting is 5 bytes, so num_init_writes should divide by 5.
Signed-off-by: Shuming Fan <shumingf@realtek.com>
Reviewed-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Link: https://patch.msgid.link/20250721112334.388506-1-shumingf@realtek.com
Signed-off-by: Mark Brown <broonie@kernel.org>
|
|
https://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into soc/dt
STM32 DT for v6.17, round 1
Highlights:
----------
- MPU:
- STM32MP13:
-Add Ethernet MAC adress efuse support.
- STMP32MP15:
- Add stm32mp157f-DK2 board support. This board embedds the same
conectivity devices, DDR ... than stm32mp157c-dk2.
However there are two differences: STM32MP157F SoC which allows
overdrive OPP and the SCMI support for system features like
clocks and regulators.
- STM32MP25:
- Fix tick timer for low power use cases.
- Add timer support.
* tag 'stm32-dt-for-v6.17-1' of https://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32:
arm64: dts: st: remove empty line in stm32mp251.dtsi
arm64: dts: st: fix timer used for ticks
arm64: defconfig: Enable STM32 Octo Memory Manager and OcstoSPI driver
ARM: dts: stm32: add stm32mp157f-dk2 board support
dt-bindings: arm: stm32: add STM32MP157F-DK2 board compatible
ARM: dts: stm32: optee async notif interrupt for MP15 scmi variants
ARM: dts: stm32: use internal regulators bindings for MP15 scmi variants
dt-bindings: regulator: Add STM32MP15 SCMI regulator identifiers
ARM: dts: stm32: use 'typec' generic name for stusb1600 on stm32mp15xx-dkx
ARM: dts: stm32: fullfill diversity with OPP for STM32M15xF SOCs
ARM: dts: stm32: add system-clock-direction-out on stm32mp15xx-dkx
arm64: defconfig: enable STM32 timers drivers
arm64: dts: st: add timer nodes on stm32mp257f-ev1
arm64: dts: st: add timer pins for stm32mp257f-ev1
arm64: dts: st: add timer nodes on stm32mp251
ARM: dts: stm32: Add nvmem-cells to ethernet nodes for constant mac-addresses
Link: https://lore.kernel.org/r/b3e3363b-1ea5-457c-b244-2cbe26f7d6e4@foss.st.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
|
https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
New boards: ROC-RK3588S-PC, Luckfox Omni3576, Radxa Rock 5T,
Sakura Pi RK3308B - all of them have the used soc in their name.
New overlays: RockPro64 screen, optional Sige5 Wifi/BT module,
ethernet-switch addon for Jaguar.
Added peripherals on rk3528 (spi, power-domain controller, gpu)
and sdio controller on rk3576.
DSI display support for the Gameforce-ACE handheld, a fix for the
cover-detection (closed/open) on the PineNote, camera support for
the Haikou Video Demo overlay on PX30 Ringneck as well as a number
of other newly enabled peripherals on a number of boards.
* tag 'v6.17-rockchip-dts64-1' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (40 commits)
arm64: dts: rockchip: Enable eMMC HS200 mode on Radxa E20C
arm64: dts: rockchip: Add bluetooth support to ArmSoM Sige7
arm64: dts: rockchip: enable PCIe on ROCK 4D
arm64: dts: rockchip: Enable HDMI receiver on CM3588
arm64: dts: rockchip: Add HDMI PHY PLL clock source to VOP2 on rk3576
arm64: dts: rockchip: Enable HDMI PHY clk provider on rk3576
arm64: dts: rockchip: add DTs for Firefly ROC-RK3588S-PC
dt-bindings: arm: rockchip: Add Firefly ROC-RK3588S-PC
arm64: dts: rockchip: Enable GPU on Radxa E20C
arm64: dts: rockchip: Add GPU node for RK3528
arm64: dts: rockchip: support camera module on Haikou Video Demo on PX30 Ringneck
arm64: dts: rockchip: add label to first port of ISP on px30
arm64: dts: rockchip: fix endpoint dtc warning for PX30 ISP
arm64: dts: rockchip: Add power controller for RK3528
arm64: dts: rockchip: enable USB on Sige5
arm64: dts: rockchip: add overlay for the WiFi/BT module on Sige5 v1.2
arm64: dts: rockchip: add version-independent WiFi/BT nodes on Sige5
arm64: dts: rockchip: add SDIO controller on RK3576
arm64: dts: rockchip: Enable gpu on rk3576-evb1-v10
arm64: dts: rockchip: Update the PinePhone Pro panel description
...
Link: https://lore.kernel.org/r/15465458.uLZWGnKmhe@phil
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
|
The Arm GIC "ppi-partitions" node is only relevant to GICv3 and makes no
sense for GICv2 implementations which the GIC-400 is. PPIs in GICv2 have
no CPU affinity.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20250609203721.2852879-1-robh@kernel.org
Signed-off-by: Andrew Jeffery <andrew@codeconstruct.com.au>
Link: https://lore.kernel.org/r/20250710-nuvoton-arm64-dt-v1-1-ec7db96ea507@codeconstruct.com.au
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
|
https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux into soc/dt
ASPEED devicetree updates for 6.17
Removed platforms:
- IBM's Swift BMC
New platforms:
- Meta's Santabarbara
Santabarbara is a compute node with an accelerator module
- NVIDIA's GB200NVL BMC
NVIDIA GB200 NVL72 connects 36 Grace CPUs and 72 Blackwell GPUs in an NVIDIA
NVLink-connected, liquid-cooled, rack-scale design.
Updated BMC platforms:
- Bletchley (Meta): GPIO hog names, remove ethernet-phy node, USB PD negotiation
- Catalina (Meta): Various sensors added, MCTP support for NIC management
- Harma (Meta): Various sensors added
- System1 (IBM): IPMB and various GPIO-related updates
- Yosemite4 (Meta): GPIO names for UART mux select lines
The System1 series includes a devicetree binding patch for IPMI IPMB devices.
* tag 'aspeed-6.17-devicetree-1' of https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux: (34 commits)
ARM: dts: aspeed: yosemite4: add gpio name for uart mux sel
ARM: dts: aspeed: santabarbara: Add Meta Santabarbara BMC
dt-bindings: arm: aspeed: add Meta Santabarbara board
ARM: dts: aspeed: bletchley: enable USB PD negotiation
ARM: dts: aspeed: lanyang: Fix 'lable' typo in LED nodes
ARM: dts: aspeed: harma: add mmc health
ARM: dts: aspeed: Harma: revise gpio bride pin for battery
ARM: dts: aspeed: harma: add ADC128D818 for voltage monitoring
ARM: dts: aspeed: harma: add fan board I/O expander
ARM: dts: aspeed: harma: add E1.S power monitor
ARM: dts: aspeed: catalina: Enable MCTP for frontend NIC management
ARM: dts: aspeed: Add device tree for Nvidia's GB200NVL BMC
dt-bindings: arm: aspeed: add Nvidia's GB200NVL BMC
ARM: dts: aspeed: catalina: Enable MCTP support for NIC management
ARM: dts: aspeed: catalina: Update CBC FRU EEPROM I2C bus and address
ARM: dts: aspeed: catalina: Enable multi-master on additional I2C buses
ARM: dts: aspeed: catalina: Remove INA238 and INA230 nodes
ARM: dts: aspeed: catalina: Add second source HSC node support
ARM: dts: aspeed: catalina: Add second source fan controller support
ARM: dts: aspeed: catalina: Add fan controller support
...
Link: https://lore.kernel.org/r/36d50489cac1fbae01ec699b742f6c6c459a01cb.camel@codeconstruct.com.au
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
|
https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
Renesas DTS updates for v6.17 (take two)
- Add support for the Renesas Gray Hawk Single board with R-Car
V4M-7 (R8A779H2),
- Add eMMC and microSD expansion board support for the RZ/V2H and
RZ/V2N EVK development boards,
- Add GPIO keys and Ethernet support for the RZ/G3E SoM and SMARC
Carrier-II EVK development board,
- Add QSPI FLASH support for the RZ/V2H and RZ/V2N SoCs and their EVK
development boards,
- Miscellaneous fixes and improvements.
* tag 'renesas-dts-for-v6.17-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Enable serial NOR FLASH
arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Enable serial NOR FLASH
arm64: dts: renesas: r9a09g057: Add XSPI node
arm64: dts: renesas: r9a09g056: Add XSPI node
arm64: dts: renesas: r9a09g056n48-rzv2n-evk: Fix pinctrl node name for GBETH1
arm64: dts: renesas: r9a09g057h44-rzv2h-evk: Fix pinctrl node name for GBETH1
arm64: dts: renesas: r8a779g3-sparrow-hawk-fan-pwm: Add missing install target
arm64: dts: renesas: rzg3e-smarc-som: Enable eth{0-1} (GBETH) interfaces
arm64: dts: renesas: r9a09g047e57-smarc: Add gpio keys
arm64: dts: renesas: Add CN15 eMMC and SD overlays for RZ/V2H and RZ/V2N EVKs
arm64: dts: renesas: r8a779h2: Add Gray Hawk Single support
arm64: dts: renesas: Add Renesas R8A779H2 SoC support
arm64: dts: renesas: Factor out Gray Hawk Single board support
dt-bindings: clock: renesas,r9a09g056/57-cpg: Add XSPI core clock
Link: https://lore.kernel.org/r/cover.1752090401.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
|
https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
Renesas DT binding updates for v6.17 (take two)
- Document support for the Renesas Gray Hawk Single board with R-Car
V4M-7 (R8A779H2).
* tag 'renesas-dt-bindings-for-v6.17-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
dt-bindings: soc: renesas: Document R-Car V4M-7 Gray Hawk Single
Link: https://lore.kernel.org/r/cover.1752090400.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
|
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
Samsung DTS ARM64 changes for v6.17
1. New SoC - Exynos2200 SoC - with basic nodes, pin controllers,
clock controllers and initial USB support. Add board using it:
Samsung Galaxy S22+ (SM-S906B), called G0S.
2. ExynosAutov920: Add CMU_HSI2 clock controller, remaining SPI nodes
3. Google GS101:
- Prepare to switching to architected timer, instead of Exynos MCT as
the primary one.
- Add secondary Maxim MAX77759 PMIC to Pixel boards, managing USB Type-C and
charger.
- Add incomplete description of the primary Samsung S2MPG10 PMIC.
Several bits, like regulators, are still missing, though.
- Add also secondary reboot-mode, via MAX77759 NVMEM.
- Switch the primary (SoC) reboot handler to Google specific
google,gs101-reboot which gives additional GS101 features (cold and
warm reboots).
This change will affect other users of this DTS, but to our
knowledge there is only Android, from which this change originates.
4. Exynos7870:
- Fix speed problems in USB gadget mode.
- Correct memory map to avoid crashes due to secure world.
* tag 'samsung-dt64-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: exynos7870-j6lte: reduce memory ranges to base amount
arm64: dts: exynos7870-on7xelte: reduce memory ranges to base amount
arm64: dts: exynos7870: add quirk to disable USB2 LPM in gadget mode
arm64: dts: exynos: gs101: switch to gs101 specific reboot
arm64: dts: exynos: gs101-pixel-common: add main PMIC node
arm64: dts: exynos: gs101: ufs: add dma-coherent property
arm64: dts: exynos: gs101: add dm-verity-device-corrupted syscon-reboot-mode
arm64: dts: exynos: gs101-pixel-common: add nvmem-reboot-mode
arm64: dts: exynos: gs101-pixel-common: add Maxim MAX77759 PMIC
arm64: dts: exynos5433: Align i2c-gpio node names with dtschema
arm64: dts: exynos: gs101: Add 'local-timer-stop' to cpuidle nodes
arm64: dts: exynosautov920: Add DT node for all SPI ports
arm64: dts: exynosautov920: add CMU_HSI2 clock DT nodes
MAINTAINERS: add entry for Samsung Exynos2200 SoC
arm64: dts: exynos: add initial support for Samsung Galaxy S22+
arm64: dts: exynos: add initial support for exynos2200 SoC
dt-bindings: arm: samsung: document g0s board binding
Link: https://lore.kernel.org/r/20250709191523.171359-6-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
|
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
Samsung DTS ARM changes for v6.17
Just few cleanups based on dtbs_check.
* tag 'samsung-dt-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
ARM: dts: s5pv210: Align i2c-gpio node names with dtschema
ARM: dts: exynos: Align i2c-gpio node names with dtschema
Link: https://lore.kernel.org/r/20250709191523.171359-5-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
|
https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt into soc/dt
VT8500 DTS ARM changes for v6.17
1. Several dtbs_check cleanups.
2. Add missing cache topology - L2 cache controller on WM8850/WM895.
* tag 'dt-vt8500-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt:
ARM: dts: vt8500: Add L2 cache controller on WM8850/WM8950
ARM: dts: vt8500: Fix the unit address of the VT8500 LCD controller
ARM: dts: vt8500: Use generic node name for the SD/MMC controller
ARM: dts: vt8500: Move memory nodes to board dts and fix addr/size
ARM: dts: vt8500: Add node address and reg in CPU nodes
Link: https://lore.kernel.org/r/20250709184800.168462-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
|
into soc/drivers
This pull request contains Broadcom SoCs drivers updates for 6.17,
please pull the following:
- Andrea adds the RP1 clock, pinctrl/pinconf/gpio and misc driver to
bind them all
* tag 'arm-soc/for-6.17/drivers' of https://github.com/Broadcom/stblinux:
pinctrl: rp1: Implement RaspberryPi RP1 pinmux/pinconf support
misc: rp1: RaspberryPi RP1 misc driver
pinctrl: rp1: Implement RaspberryPi RP1 gpio support
clk: rp1: Add support for clocks provided by RP1
dt-bindings: clock: Add RaspberryPi RP1 clock bindings
Link: https://lore.kernel.org/r/20250630190216.1518354-4-florian.fainelli@broadcom.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
|
https://github.com/Broadcom/stblinux into soc/drivers
This pull request contains MAINTAINERS file updates for 6.17, please
pull the following:
- Andrea adds the RP1 entry for all of the drivers pertaining to that
chip
* tag 'arm-soc/for-6.17/maintainers' of https://github.com/Broadcom/stblinux:
MAINTAINERS: add Raspberry Pi RP1 section
Link: https://lore.kernel.org/r/20250630190216.1518354-5-florian.fainelli@broadcom.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
|
We need the tty/serial fixes in here as well.
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
|
Add entry for Andes SoC maintainer and related files
Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
Link: https://lore.kernel.org/r/20250711133025.2192404-10-ben717@andestech.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
|
Enable Andes SoC config in defconfig to allow the default
upstream kernel to boot on Voyager board.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
Link: https://lore.kernel.org/r/20250711133025.2192404-9-ben717@andestech.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
|
Introduce the device tree support for Voyager development board.
Currently only support booting into console with only uart,
other features will be added later.
Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
Link: https://lore.kernel.org/r/20250711133025.2192404-8-ben717@andestech.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
|
Introduce the initial device tree support for the Andes QiLai SoC.
For further information, you can refer to [1].
[1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/
Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
Link: https://lore.kernel.org/r/20250711133025.2192404-7-ben717@andestech.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
|
Add the DT binding documentation for Andes machine timer.
The RISC-V architecture defines a machine timer that provides a real-time
counter and generates timer interrupts. Andes machiner timer (PLMT0) is
the implementation of the machine timer, and it contains memory-mapped
registers (mtime and mtimecmp). This device supports up to 32 cores.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
Link: https://lore.kernel.org/r/20250711133025.2192404-6-ben717@andestech.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
|
interrupt controller
Add the DT binding documentation for Andes machine-level software
interrupt controller.
In the Andes platform such as QiLai SoC, the PLIC module is instantiated a
second time with all interrupt sources tied to zero as the software
interrupt controller (PLICSW). PLICSW can generate machine-level software
interrupts through programming its registers.
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
Link: https://lore.kernel.org/r/20250711133025.2192404-5-ben717@andestech.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
|
Add a new compatible string for Andes QiLai PLIC.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
Link: https://lore.kernel.org/r/20250711133025.2192404-4-ben717@andestech.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
|
Add DT binding documentation for the Andes QiLai SoC and the
Voyager development board.
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
Link: https://lore.kernel.org/r/20250711133025.2192404-3-ben717@andestech.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
|
The first SoC in the Andes series is QiLai. It includes a high-performance
quad-core RISC-V AX45MP cluster and one NX27V vector processor.
For further information, refer to [1].
[1] https://www.andestech.com/en/products-solutions/andeshape-platforms/qilai-chip/
Signed-off-by: Ben Zong-You Xie <ben717@andestech.com>
Link: https://lore.kernel.org/r/20250711133025.2192404-2-ben717@andestech.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
|
https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux into soc/drivers
MediaTek soc driver updates for v6.17
This adds a single cleanup commit for the mtk-mutex driver,
clarifying the usage of the MUTEX_MOD1, MUTEX_MOD2 registers
for applying display controller sub-component mute settings
on all MediaTek SoCs.
* tag 'mtk-soc-for-v6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux:
soc: mediatek: mtk-mutex: Fix confusing usage of MUTEX_MOD2
Link: https://lore.kernel.org/r/20250711083656.33538-4-angelogioacchino.delregno@collabora.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
|
soc/drivers
Reset controller updates for v6.17
* Support reset controllers on Kendryte K230 and SOPHGO CV1800B.
* Add RZ/V2N USB2PHY reset controller bindings
* Use auxiliary device creation helpers in reset-mpfs.
* Convert nxp,lcp1850-rgu and snps,dw-reset binding docs to DT schema.
* Enable reset-brcmstb(-rescal) on BCM2712.
* Fix a typo in the T-HEAD TH1520 Kconfig option
* tag 'reset-for-v6.17' of https://git.pengutronix.de/git/pza/linux:
dt-bindings: reset: Convert snps,dw-reset to DT schema
reset: brcmstb: Enable reset drivers for ARCH_BCM2835
reset: simple: add support for Sophgo CV1800B
dt-bindings: reset: sophgo: Add CV1800B support
reset: mpfs: use the auxiliary device creation
dt-bindings: reset: renesas,rzv2h-usb2phy: Document RZ/V2N SoC support
dt-bindings: reset: convert nxp,lpc1850-rgu.txt to yaml format
reset: thead: Fix TH1520 typo
reset: canaan: add reset driver for Kendryte K230
dt-bindings: reset: add support for canaan,k230-rst
Link: https://lore.kernel.org/r/20250710152513.1346298-1-p.zabel@pengutronix.de
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
|
There is a extraneous space before a newline in a pr_warn message.
Remove it.
Signed-off-by: Colin Ian King <colin.i.king@gmail.com>
Link: https://patch.msgid.link/20250721135016.2500117-1-colin.i.king@gmail.com
[ rjw: Changelog edits ]
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
|
|
FSL SOC Changes for 6.17:
- Use dev_fwnode() instead of of_fwnode_handle()
- Use new GPIO line value setter callbacks
* tag 'soc_fsl-6.17-1' of https://github.com/chleroy/linux:
soc: Use dev_fwnode()
soc: fsl: qe: use new GPIO line value setter callbacks
Link: https://lore.kernel.org/r/c947d537-cae5-44f0-abd8-0c558bac46d2@csgroup.eu
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
|
https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux into soc/drivers
ASPEED SoC driver updates for 6.17
The ASPEED LPC snoop driver was recently the cause of some concern. In addition
to the initial fixes, the channel configuration paths are refactored to improve
robustness against errors.
* tag 'aspeed-6.17-drivers-1' of https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux:
soc: aspeed: lpc-snoop: Lift channel config to const structs
soc: aspeed: lpc-snoop: Consolidate channel initialisation
soc: aspeed: lpc-snoop: Use dev_err_probe() where possible
soc: aspeed: lpc-snoop: Switch to devm_clk_get_enabled()
soc: aspeed: lpc-snoop: Rearrange channel paths
soc: aspeed: lpc-snoop: Rename 'channel' to 'index' in channel paths
soc: aspeed: lpc-snoop: Constrain parameters in channel paths
soc: aspeed: lpc-snoop: Ensure model_data is valid
soc: aspeed: lpc-snoop: Don't disable channels that aren't enabled
soc: aspeed: lpc-snoop: Cleanup resources in stack-order
Link: https://lore.kernel.org/r/9123f151280e52c63dcb645cb07d4eee3462c067.camel@codeconstruct.com.au
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
|
https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/drivers
Renesas driver updates for v6.17 (take two)
- Sort Renesas Kconfig symbols.
* tag 'renesas-drivers-for-v6.17-tag2' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel:
soc: renesas: Sort Renesas Kconfig configs
Link: https://lore.kernel.org/r/cover.1752090398.git.geert+renesas@glider.be
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
|
https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into soc/drivers
Arm SCMI updates for v6.17
1. A fix is introduced to correct turbo frequency marking for 64-bit
devices with sustained frequencies over 4GHz, ensuring accurate turbo
frequency identification.
2. Debug capabilities are being improved by introducing in-flight transfer
tracking using debug counters, which help diagnose transfer congestion
and behavior. Additional tracepoints are added to log in-flight counts
at transfer begin and end, offering better runtime insight. The debug
counters now support decrement operations using a newly added
scmi_dec_count helper, making counter tracking symmetric and more robust.
3. A race condition in suspend-resume logic is being resolved by ensuring
SCMI_SYSPOWER_IDLE state is set early during resume, improving suspend
reliability under certain conditions. New suspend and resume operations
are added to the scmi_bus_type to enable finer power management control
for SCMI-based devices.
4. Finally enhancements are also made to avoid registering notifiers for
events that a platform does not support, reducing unnecessary overhead
by checking for unsupported event types during protocolinitialization.
* tag 'scmi-updates-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
firmware: arm_scmi: Convert to SYSTEM_SLEEP_PM_OPS
firmware: arm_scmi: Avoid notifier registration for unsupported events
firmware: arm_scmi: power_control: Ensure SCMI_SYSPOWER_IDLE is set early during resume
firmware: arm_scmi: Add power management operations to SCMI bus
include: trace: Add tracepoint support for inflight xfer count
firmware: arm_scmi: Track number of inflight SCMI transfers
firmware: arm_scmi: Add support for debug counter decrement
firmware: arm_scmi: Fix up turbo frequencies selection
Link: https://lore.kernel.org/r/20250709122907.1171913-1-sudeep.holla@arm.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
|
https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into soc/drivers
firmware: smccc: Update for v6.17
Just a single update extending arm_smccc_hypervisor_has_uuid() to
support both SMC and HVC conduits, enabling UUID retrieval when Linux
runs as the root partition under Microsoft Hypervisor (MSHV), where
SMC is used. It leverages arm_smccc_1_1_invoke() to dynamically select
the appropriate conduit, enhancing compatibility beyond just HVC.
* tag 'smccc-updates-6.17' of https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
firmware: smccc: Support both smc and hvc conduits for getting hyp UUID
Link: https://lore.kernel.org/r/20250709122615.1171419-1-sudeep.holla@arm.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
|
|
Merge series from Heiko Schocher <hs@denx.de>:
This series introduces the changes needed for trivial spi
based sensors from ABB, currently operated from userspace.
|
|
The second instance of TBSVC_MATCH_PROTOCOL_VERSION seems to have been
intended to be TBSVC_MATCH_PROTOCOL_REVISION.
Fixes: d1ff70241a27 ("thunderbolt: Add support for XDomain discovery protocol")
Cc: stable <stable@kernel.org>
Signed-off-by: Eric Biggers <ebiggers@kernel.org>
Link: https://lore.kernel.org/r/20250721050136.30004-1-ebiggers@kernel.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
|
The current power direction of an USB-C port also influences the
power_supply's online status, so a power role change should also update
the power_supply.
Fixes an issue on some systems where plugging in a normal USB device in
for the first time after a reboot will cause upower to erroneously
consider the system to be connected to AC power.
Cc: stable <stable@kernel.org>
Fixes: 0e6371fbfba3 ("usb: typec: ucsi: Report power supply changes")
Signed-off-by: Myrrh Periwinkle <myrrhperiwinkle@qtmlabs.xyz>
Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Link: https://lore.kernel.org/r/20250721-fix-ucsi-pwr-dir-notify-v1-1-e53d5340cb38@qtmlabs.xyz
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
|
ucsi_psy_get_current_max would return 0mA as the maximum current if
UCSI detected a BC or a Default USB Power sporce.
The comment in this function is true that we can't tell the difference
between DCP/CDP or SDP chargers, but we can guarantee that at least 1-unit
of USB 1.1/2.0 power is available, which is 100mA, which is a better
fallback value than 0, which causes some userspaces, including the ChromeOS
power manager, to regard this as a power source that is not providing
any power.
In reality, 100mA is guaranteed from all sources in these classes.
Signed-off-by: Benson Leung <bleung@chromium.org>
Reviewed-by: Jameson Thies <jthies@google.com>
Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Link: https://lore.kernel.org/r/20250717200805.3710473-1-bleung@chromium.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
|
