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2021-04-09clk: mvebu: armada-37xx-periph: Fix switching CPU freq from 250 Mhz to 1 GHzPali Rohár
It was observed that the workaround introduced by commit 61c40f35f5cd ("clk: mvebu: armada-37xx-periph: Fix switching CPU rate from 300Mhz to 1.2GHz") when base CPU frequency is 1.2 GHz is also required when base CPU frequency is 1 GHz. Otherwise switching CPU frequency directly from L2 (250 MHz) to L0 (1 GHz) causes a crash. When base CPU frequency is just 800 MHz no crashed were observed during switch from L2 to L0. Signed-off-by: Pali Rohár <pali@kernel.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Tested-by: Tomasz Maciej Nowak <tmn505@gmail.com> Tested-by: Anders Trier Olesen <anders.trier.olesen@gmail.com> Tested-by: Philip Soares <philips@netisense.com> Fixes: 2089dc33ea0e ("clk: mvebu: armada-37xx-periph: add DVFS support for cpu clocks") Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
2021-04-09cpufreq: armada-37xx: Fix the AVS value for load L1Pali Rohár
The original CPU voltage value for load L1 is too low for Armada 37xx SoC when base CPU frequency is 1000 or 1200 MHz. It leads to instabilities where CPU gets stuck soon after dynamic voltage scaling from load L1 to L0. Update the CPU voltage value for load L1 accordingly when base frequency is 1000 or 1200 MHz. The minimal L1 value for base CPU frequency 1000 MHz is updated from the original 1.05V to 1.108V and for 1200 MHz is updated to 1.155V. This minimal L1 value is used only in the case when it is lower than value for L0. This change fixes CPU instability issues on 1 GHz and 1.2 GHz variants of Espressobin and 1 GHz Turris Mox. Marvell previously for 1 GHz variant of Espressobin provided a patch [1] suitable only for their Marvell Linux kernel 4.4 fork which workarounded this issue. Patch forced CPU voltage value to 1.108V in all loads. But such change does not fix CPU instability issues on 1.2 GHz variants of Armada 3720 SoC. During testing we come to the conclusion that using 1.108V as minimal value for L1 load makes 1 GHz variants of Espressobin and Turris Mox boards stable. And similarly 1.155V for 1.2 GHz variant of Espressobin. These two values 1.108V and 1.155V are documented in Armada 3700 Hardware Specifications as typical initial CPU voltage values. Discussion about this issue is also at the Armbian forum [2]. [1] - https://github.com/MarvellEmbeddedProcessors/linux-marvell/commit/dc33b62c90696afb6adc7dbcc4ebbd48bedec269 [2] - https://forum.armbian.com/topic/10429-how-to-make-espressobin-v7-stable/ Signed-off-by: Pali Rohár <pali@kernel.org> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Tested-by: Tomasz Maciej Nowak <tmn505@gmail.com> Tested-by: Anders Trier Olesen <anders.trier.olesen@gmail.com> Tested-by: Philip Soares <philips@netisense.com> Fixes: 1c3528232f4b ("cpufreq: armada-37xx: Add AVS support") Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
2021-04-09clk: mvebu: armada-37xx-periph: remove .set_parent method for CPU PM clockMarek Behún
Remove the .set_parent method in clk_pm_cpu_ops. This method was supposed to be needed by the armada-37xx-cpufreq driver, but was never actually called due to wrong assumptions in the cpufreq driver. After this was fixed in the cpufreq driver, this method is not needed anymore. Signed-off-by: Marek Behún <kabel@kernel.org> Acked-by: Stephen Boyd <sboyd@kernel.org> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Tested-by: Pali Rohár <pali@kernel.org> Tested-by: Tomasz Maciej Nowak <tmn505@gmail.com> Tested-by: Anders Trier Olesen <anders.trier.olesen@gmail.com> Tested-by: Philip Soares <philips@netisense.com> Fixes: 2089dc33ea0e ("clk: mvebu: armada-37xx-periph: add DVFS support for cpu clocks") Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
2021-04-09cpufreq: armada-37xx: Fix setting TBG parent for load levelsMarek Behún
With CPU frequency determining software [1] we have discovered that after this driver does one CPU frequency change, the base frequency of the CPU is set to the frequency of TBG-A-P clock, instead of the TBG that is parent to the CPU. This can be reproduced on EspressoBIN and Turris MOX: cd /sys/devices/system/cpu/cpufreq/policy0 echo powersave >scaling_governor echo performance >scaling_governor Running the mhz tool before this driver is loaded reports 1000 MHz, and after loading the driver and executing commands above the tool reports 800 MHz. The change of TBG clock selector is supposed to happen in function armada37xx_cpufreq_dvfs_setup. Before the function returns, it does this: parent = clk_get_parent(clk); clk_set_parent(clk, parent); The armada-37xx-periph clock driver has the .set_parent method implemented correctly for this, so if the method was actually called, this would work. But since the introduction of the common clock framework in commit b2476490ef11 ("clk: introduce the common clock..."), the clk_set_parent function checks whether the parent is actually changing, and if the requested new parent is same as the old parent (which is obviously the case for the code above), the .set_parent method is not called at all. This patch fixes this issue by filling the correct TBG clock selector directly in the armada37xx_cpufreq_dvfs_setup during the filling of other registers at the same address. But the determination of CPU TBG index cannot be done via the common clock framework, therefore we need to access the North Bridge Peripheral Clock registers directly in this driver. [1] https://github.com/wtarreau/mhz Signed-off-by: Marek Behún <kabel@kernel.org> Acked-by: Gregory CLEMENT <gregory.clement@bootlin.com> Tested-by: Pali Rohár <pali@kernel.org> Tested-by: Tomasz Maciej Nowak <tmn505@gmail.com> Tested-by: Anders Trier Olesen <anders.trier.olesen@gmail.com> Tested-by: Philip Soares <philips@netisense.com> Fixes: 92ce45fb875d ("cpufreq: Add DVFS support for Armada 37xx") Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
2021-04-09MIPS: octeon: Add __raw_copy_[from|to|in]_user symbolsThomas Bogendoerfer
Cavium Octeon has its own memcpy implementation and also need the change done in commit 04324f44cb69 ("MIPS: Remove get_fs/set_fs"). Fixes: 04324f44cb69 ("MIPS: Remove get_fs/set_fs") Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
2021-04-09thunderbolt: Hide authorized attribute if router does not support PCIe tunnelsMika Westerberg
With USB4 devices PCIe tunneling is optional so for device routers without PCIe upstream adapter it does not make much sense to expose the authorized attribute. For this reason hide it if PCIe tunneling is not supported by the device router. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-04-09thunderbolt: Add details to router ueventMika Westerberg
Expose two environment variables for routers as part of the initial uevent: USB4_VERSION=1.0 USB4_TYPE=host|device|hub Userspace can use this information to expose more details about each connected device. Only USB4 devices have USB4_VERSION but all devices have USB4_TYPE. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2021-04-09crypto: qat - Fix a double free in adf_create_ringLv Yunlong
In adf_create_ring, if the callee adf_init_ring() failed, the callee will free the ring->base_addr by dma_free_coherent() and return -EFAULT. Then adf_create_ring will goto err and the ring->base_addr will be freed again in adf_cleanup_ring(). My patch sets ring->base_addr to NULL after the first freed to avoid the double free. Fixes: a672a9dc872ec ("crypto: qat - Intel(R) QAT transport code") Signed-off-by: Lv Yunlong <lyl2019@mail.ustc.edu.cn> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-04-09crypto: hisilicon/qm - delete redundant codeKai Ye
The "qdma" is a structure variable instead of actual data. This structure doesn't need to be zerod, The memset is useless and redundant. So delete it. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-04-09crypto: hisilicon/sec - fixup checking the 3DES weak keyKai Ye
skcipher: Add a verifying to check whether the triple DES key is weak. Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-04-09crypto: sa2ul - Fix memory leak of rxdColin Ian King
There are two error return paths that are not freeing rxd and causing memory leaks. Fix these. Addresses-Coverity: ("Resource leak") Fixes: 00c9211f60db ("crypto: sa2ul - Fix DMA mapping API usage") Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-04-09crypto: sun8i-ss - Fix memory leak of padColin Ian King
It appears there are several failure return paths that don't seem to be free'ing pad. Fix these. Addresses-Coverity: ("Resource leak") Fixes: d9b45418a917 ("crypto: sun8i-ss - support hash algorithms") Signed-off-by: Colin Ian King <colin.king@canonical.com> Acked-by: Corentin Labbe <clabbe.montjoie@gmail.com> Tested-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-04-09crypto: rockchip - delete unneeded variable initializationKai Ye
Delete unneeded variable initialization Signed-off-by: Kai Ye <yekai13@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-04-09crypto: ccp - Use DEFINE_SPINLOCK() for spinlockTang Yizhou
spinlock can be initialized automatically with DEFINE_SPINLOCK() rather than explicitly calling spin_lock_init(). Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Tang Yizhou <tangyizhou@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-04-09crypto: hisilicon/hpre - fix a typo in hpre_crypto.cRuiqi Gong
Do a trivial typo fix. s/discribed/described Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Ruiqi Gong <gongruiqi1@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-04-09crypto: ccp - A value assigned to a variable is never usedJiapeng Chong
Fix the following whitescan warning: Assigning value "64" to "dst.address" here, but that stored value is overwritten before it can be used. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Acked-by: John Allen <john.allen@amd.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-04-09crypto: hisilicon/sec - Fix a module parameter errorLongfang Liu
ctx_q_num is a module parameter set by the user to specify the number of qp queues required to create a ctx. When the number of qp queues allocated by PF or VF is less than the ctx_q_num, an error will be reported when ctx is initialized in kernel mode, which leads to the problem that the registered algorithms cannot be used. Therefore, when PF or VF is initialized, if the number of qp queues is not enough to create a ctx, the kernel mode cannot be used, and there is no need to register the kernel mode algorithms. Signed-off-by: Longfang Liu <liulongfang@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-04-09crypto: allwinner - add missing CRYPTO_ prefixCorentin Labbe
Some CONFIG select miss CRYPTO_. Reported-by: Chen-Yu Tsai <wens@csie.org> Fixes: 56f6d5aee88d1 ("crypto: sun8i-ce - support hash algorithms") Fixes: d9b45418a9177 ("crypto: sun8i-ss - support hash algorithms") Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2021-04-09ARM: dts: clps711x: fix missing interrupt parentArnd Bergmann
The kernelci.org bot reports a build time regression: arch/arm/boot/dts/ep7209.dtsi:187.17-192.4: Warning (interrupts_property): /keypad: Missing interrupt-parent There is only one interrupt controller in this SoC, so I assume this is the parent. Fixes: 2bd86203acf3 ("ARM: dts: clps711x: Add keypad node") Reported-by: kernelci.org bot <bot@kernelci.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-04-09ARM: dts: mvebu: fix SPI device nodeArnd Bergmann
dtc warns about a mismatched address: arch/arm/boot/dts/armada-385-atl-x530.dts:171.14-199.4: Warning (spi_bus_reg): /soc/spi@10680/spi-flash@0: SPI bus unit address format error, expected "1" I assume the "reg" property is correct here, so adjust the unit address accordingly. Fixes: c6dfc019c239 ("ARM: dts: mvebu: Add device tree for ATL-x530 Board") Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Reported-by: kernelci.org bot <bot@kernelci.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-04-09clk: socfpga: fix iomem pointer cast on 64-bitKrzysztof Kozlowski
Pointers should be cast with uintptr_t instead of integer. This fixes warning when compile testing on ARM64: drivers/clk/socfpga/clk-gate.c: In function ‘socfpga_clk_recalc_rate’: drivers/clk/socfpga/clk-gate.c:102:7: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] Fixes: b7cec13f082f ("clk: socfpga: Look for the GPIO_DB_CLK by its offset") Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> Acked-by: Dinh Nguyen <dinguyen@kernel.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-04-09Merge tag 'bmc-5.13-wpcm450' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc into arm/newsoc Nuvoton WPCM450 BMC SoC This adds basic support for the Nuvoton WPCM450 BMC SoC. It's an older SoC but still commonly found on eBay, mostly in Supermicro X9 server boards. Third-party documentation is available at: https://github.com/neuschaefer/wpcm450/wiki The code has been contributed by Jonathan Neuschäfer who has also stepped forward to maintain the soc. * tag 'bmc-5.13-wpcm450' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc: ARM: config: Add WPCM to multi v5 MAINTAINERS: Add entry for Nuvoton WPCM450 ARM: dts: Add devicetree for Supermicro X9SCi-LN4F based on WPCM450 ARM: dts: Add devicetree for Nuvoton WPCM450 BMC chip watchdog: npcm: Add support for WPCM450 ARM: npcm: Introduce Nuvoton WPCM450 SoC dt-bindings: watchdog: npcm: Add nuvoton,wpcm450-wdt dt-bindings: arm: npcm: Add nuvoton,wpcm450 compatible string dt-bindings: vendor-prefixes: Add Supermicro ARM: dts: Add board-specific compatible string to npcm750-evb devicetree dt-bindings: arm: Convert nuvoton,npcm750 binding to YAML Link: https://lore.kernel.org/r/CACPK8Xdj20TcJckH8fx757ACa4hT4j3bZEctT0Przjv8XJd7KA@mail.gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-04-09Merge tag 'aspeed-5.13-lpc' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc into arm/drivers ASPEED LPC updates for 5.13 These patches fix the ASPEED LPC bindings and LPC-related device drivers so in the future the KCS driver can properly use the hardware. * tag 'aspeed-5.13-lpc' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc: soc: aspeed: Adapt to new LPC device tree layout pinctrl: aspeed-g5: Adapt to new LPC device tree layout ipmi: kcs: aspeed: Adapt to new LPC DTS layout ARM: dts: Remove LPC BMC and Host partitions dt-bindings: aspeed-lpc: Remove LPC partitioning Link: https://lore.kernel.org/r/CACPK8Xcb12LsVr7CUaXXjQskKbVjb7x+jgueG1Hik-kBPWtDSg@mail.gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-04-09Merge tag 'bmc-5.13-devicetree' of ↵Arnd Bergmann
git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc into arm/dt BMC device tree updates for 5.13 The ASPEED and Nuvoton pull request now comes as a combined BMC pull request. - New machines * ASRock E3C246D4I, an AST2500 BMC for an Xeon E-2100/E-2200 mini-ITX system * Quanta GBS, an NPCM730 BMC for an x86 server - Power10 BMC updates for Everest and Rainier - GPIO line names for Mihawk * tag 'bmc-5.13-devicetree' of git://git.kernel.org/pub/scm/linux/kernel/git/joel/bmc: (21 commits) ARM: dts: nuvoton: Add Quanta GBS BMC Device Tree ARM: dts: aspeed: mihawk: Add GPIO line names ARM: dts: aspeed: Add Rainier 1S4U machine ARM: dts: aspeed: everest: Add size/address cells ARM: dts: aspeed: everest: Enable fan watchdog ARM: dts: aspeed: everest: Add RTC ARM: dts: aspeed: everest: GPIOs support ARM: dts: aspeed: everest: Add UCD90320 power sequencer ARM: dts: aspeed: everest: Add power supply i2c devices ARM: dts: aspeed: everest: Add pca9552 fan presence ARM: dts: aspeed: everest: Add FSI CFAMs and re-number engines ARM: dts: aspeed: everest: Add max31785 fan controller device ARM: dts: aspeed: everest: Add I2C components ARM: dts: aspeed: rainier 4U: Fix fan configuration ARM: dts: aspeed: rainier: Add missing fan nodes ARM: dts: aspeed: rainier: Enable fan watchdog ARM: dts: aspeed: rainier: Add presence GPIOs ARM: dts: aspeed: rainier: Add additional processor CFAMs ARM: dts: aspeed: rainier: Add gpio-keys-polled for fans ARM: dts: aspeed: rainier: Add directly controlled LEDs ... Link: https://lore.kernel.org/r/CACPK8Xe-KV5BeQwOH6NKC1++FCVqwwNCGBh7hEbBORfrmxfTtQ@mail.gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-04-08Merge branch 'bpf/selftests: page size fixes'Andrii Nakryiko
Yauheni Kaliuta says: ==================== A set of fixes for selftests to make them working on systems with PAGE_SIZE > 4K + cleanup (version) and ringbuf_multi extention. --- v3->v4: - zero initialize BPF programs' static variables; - add bpf_map__inner_map to libbpf.map in alphabetical order; - add bpf_map__set_inner_map_fd test to ringbuf_multi; v2->v3: - reorder: move version removing patch first to keep main patches in one group; - rename "selftests/bpf: pass page size from userspace in sockopt_sk" as suggested; - convert sockopt_sk test to use ASSERT macros; - set page size from userspace - split patches to pairs userspace/bpf. It's easier to check that every conversion works as expected; v1->v2: - add missed 'selftests/bpf: test_progs/sockopt_sk: Convert to use BPF skeleton' ==================== Signed-off-by: Andrii Nakryiko <andrii@kernel.org>
2021-04-08selftests/bpf: ringbuf_multi: Test bpf_map__set_inner_map_fdYauheni Kaliuta
Test map__set_inner_map_fd() interaction with map-in-map initialization. Use hashmap of maps just to make it different to existing array of maps. Signed-off-by: Yauheni Kaliuta <yauheni.kaliuta@redhat.com> Signed-off-by: Andrii Nakryiko <andrii@kernel.org> Link: https://lore.kernel.org/bpf/20210408061310.95877-9-yauheni.kaliuta@redhat.com
2021-04-08selftests/bpf: ringbuf_multi: Use runtime page sizeYauheni Kaliuta
Set bpf table sizes dynamically according to the runtime page size value. Do not switch to ASSERT macros, keep CHECK, for consistency with the rest of the test. Can be a separate cleanup patch. Signed-off-by: Yauheni Kaliuta <yauheni.kaliuta@redhat.com> Signed-off-by: Andrii Nakryiko <andrii@kernel.org> Link: https://lore.kernel.org/bpf/20210408061310.95877-8-yauheni.kaliuta@redhat.com
2021-04-08libbpf: Add bpf_map__inner_map APIAndrii Nakryiko
The API gives access to inner map for map in map types (array or hash of map). It will be used to dynamically set max_entries in it. Signed-off-by: Yauheni Kaliuta <yauheni.kaliuta@redhat.com> Signed-off-by: Andrii Nakryiko <andrii@kernel.org> Link: https://lore.kernel.org/bpf/20210408061310.95877-7-yauheni.kaliuta@redhat.com
2021-04-08selftests/bpf: ringbuf: Use runtime page sizeYauheni Kaliuta
Replace hardcoded 4096 with runtime value in the userspace part of the test and set bpf table sizes dynamically according to the value. Do not switch to ASSERT macros, keep CHECK, for consistency with the rest of the test. Can be a separate cleanup patch. Signed-off-by: Yauheni Kaliuta <yauheni.kaliuta@redhat.com> Signed-off-by: Andrii Nakryiko <andrii@kernel.org> Link: https://lore.kernel.org/bpf/20210408061310.95877-6-yauheni.kaliuta@redhat.com
2021-04-08selftests/bpf: mmap: Use runtime page sizeYauheni Kaliuta
Replace hardcoded 4096 with runtime value in the userspace part of the test and set bpf table sizes dynamically according to the value. Do not switch to ASSERT macros, keep CHECK, for consistency with the rest of the test. Can be a separate cleanup patch. Signed-off-by: Yauheni Kaliuta <yauheni.kaliuta@redhat.com> Signed-off-by: Andrii Nakryiko <andrii@kernel.org> Link: https://lore.kernel.org/bpf/20210408061310.95877-5-yauheni.kaliuta@redhat.com
2021-04-08selftests/bpf: Pass page size from userspace in map_ptrYauheni Kaliuta
Use ASSERT to check result but keep CHECK where format was used to report error. Use bpf_map__set_max_entries() to set map size dynamically from userspace according to page size. Zero-initialize the variable in bpf prog, otherwise it will cause problems on some versions of Clang. Signed-off-by: Yauheni Kaliuta <yauheni.kaliuta@redhat.com> Signed-off-by: Andrii Nakryiko <andrii@kernel.org> Link: https://lore.kernel.org/bpf/20210408061310.95877-4-yauheni.kaliuta@redhat.com
2021-04-08selftests/bpf: Pass page size from userspace in sockopt_skYauheni Kaliuta
Since there is no convenient way for bpf program to get PAGE_SIZE from inside of the kernel, pass the value from userspace. Zero-initialize the variable in bpf prog, otherwise it will cause problems on some versions of Clang. Signed-off-by: Yauheni Kaliuta <yauheni.kaliuta@redhat.com> Signed-off-by: Andrii Nakryiko <andrii@kernel.org> Link: https://lore.kernel.org/bpf/20210408061310.95877-3-yauheni.kaliuta@redhat.com
2021-04-08selftests/bpf: test_progs/sockopt_sk: Convert to use BPF skeletonYauheni Kaliuta
Switch the test to use BPF skeleton to save some boilerplate and make it easy to access bpf program bss segment. The latter will be used to pass PAGE_SIZE from userspace since there is no convenient way for bpf program to get it from inside of the kernel. Signed-off-by: Yauheni Kaliuta <yauheni.kaliuta@redhat.com> Signed-off-by: Andrii Nakryiko <andrii@kernel.org> Link: https://lore.kernel.org/bpf/20210408061310.95877-2-yauheni.kaliuta@redhat.com
2021-04-08selftests/bpf: test_progs/sockopt_sk: Remove versionYauheni Kaliuta
As pointed by Andrii Nakryiko, _version is useless now, remove it. Signed-off-by: Yauheni Kaliuta <yauheni.kaliuta@redhat.com> Signed-off-by: Andrii Nakryiko <andrii@kernel.org> Link: https://lore.kernel.org/bpf/20210408061310.95877-1-yauheni.kaliuta@redhat.com
2021-04-09asm-generic/io.h: Unbork ioremap_np() declarationHector Martin
It accidentally slipped into the #ifdef for ioremap_uc(). Signed-off-by: Hector Martin <marcan@marcan.st> Link: https://lore.kernel.org/r/20210409052038.58925-1-marcan@marcan.st' Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2021-04-09ARM: config: Add WPCM to multi v5Joel Stanley
This is a newly added ARM926 platform that is not covered by any other defconfigs. Signed-off-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20210409054511.1534181-1-joel@jms.id.au
2021-04-08libnvdimm: Notify disk drivers to revalidate region read-onlyDan Williams
Previous kernels allowed the BLKROSET to override the disk's read-only status. With that situation fixed the pmem driver needs to rely on notification events to reevaluate the disk read-only status after the host region has been marked read-write. Recall that when libnvdimm determines that the persistent memory has lost persistence (for example lack of energy to flush from DRAM to FLASH on an NVDIMM-N device) it marks the region read-only, but that state can be overridden by the user via: echo 0 > /sys/bus/nd/devices/regionX/read_only ...to date there is no notification that the region has restored persistence, so the user override is the only recovery. Fixes: 52f019d43c22 ("block: add a hard-readonly flag to struct gendisk") Reported-by: kernel test robot <lkp@intel.com> Reported-by: Vishal Verma <vishal.l.verma@intel.com> Tested-by: Vishal Verma <vishal.l.verma@intel.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Cc: Christoph Hellwig <hch@lst.de> Cc: Ming Lei <ming.lei@redhat.com> Cc: Martin K. Petersen <martin.petersen@oracle.com> Cc: Hannes Reinecke <hare@suse.de> Cc: Jens Axboe <axboe@kernel.dk> Link: https://lore.kernel.org/r/161534060720.528671.2341213328968989192.stgit@dwillia2-desk3.amr.corp.intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
2021-04-09MAINTAINERS: Add entry for Nuvoton WPCM450Jonathan Neuschäfer
I am adding myself as the maintainer of WPCM450-related code. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20210406120921.2484986-11-j.neuschaefer@gmx.net Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-04-09ARM: dts: Add devicetree for Supermicro X9SCi-LN4F based on WPCM450Jonathan Neuschäfer
The Supermicro X9SCi-LN4F is a server mainboard featuring the WPCM450 BMC. This patch adds a minimal devicetree for Linux running on the BMC. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20210406120921.2484986-10-j.neuschaefer@gmx.net Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-04-09ARM: dts: Add devicetree for Nuvoton WPCM450 BMC chipJonathan Neuschäfer
The WPCM450 is an older BMC SoC in the Nuvoton NPCM family, originally marketed as Winbond WPCM450. This patch adds a devicetree with basic functionality. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20210406120921.2484986-9-j.neuschaefer@gmx.net Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-04-09watchdog: npcm: Add support for WPCM450Jonathan Neuschäfer
Add a compatible string for WPCM450, which has essentially the same watchdog mechanism as NPCM750. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Acked-by: Guenter Roeck <linux@roeck-us.net> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20210406120921.2484986-8-j.neuschaefer@gmx.net Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-04-09ARM: npcm: Introduce Nuvoton WPCM450 SoCJonathan Neuschäfer
The WPCM450 is an older BMC SoC in the Nuvoton NPCM family, originally marketed as Winbond WPCM450. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20210406120921.2484986-6-j.neuschaefer@gmx.net Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-04-09dt-bindings: watchdog: npcm: Add nuvoton,wpcm450-wdtJonathan Neuschäfer
Add a compatible string for the WPCM450 SoC, which has the same watchdog timer. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20210406120921.2484986-5-j.neuschaefer@gmx.net Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-04-09dt-bindings: arm: npcm: Add nuvoton,wpcm450 compatible stringJonathan Neuschäfer
The WPCM450 is an older BMC SoC in the Nuvoton NPCM family, originally marketed as Winbond WPCM450. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20210406120921.2484986-3-j.neuschaefer@gmx.net Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-04-09dt-bindings: vendor-prefixes: Add SupermicroJonathan Neuschäfer
Super Micro Computer, Inc. (https://www.supermicro.com/en/), commonly known as Supermicro, is a manufacturer of server hardware. Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20210406120921.2484986-2-j.neuschaefer@gmx.net Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-04-09bus: mhi: core: Fix shadow declarationsManivannan Sadhasivam
This commit fixes below sparse warnings with W=2 about shadow declarations: drivers/bus/mhi/core/main.c: In function ‘parse_xfer_event’: drivers/bus/mhi/core/main.c:667:17: warning: declaration of ‘flags’ shadows a previous local [-Wshadow] 667 | unsigned long flags; | ^~~~~ drivers/bus/mhi/core/main.c:565:16: note: shadowed declaration is here 565 | unsigned long flags = 0; | ^~~~~ drivers/bus/mhi/core/main.c: In function ‘mhi_process_ctrl_ev_ring’: drivers/bus/mhi/core/main.c:856:23: warning: declaration of ‘new_state’ shadows a previous local [-Wshadow] 856 | enum mhi_pm_state new_state; | ^~~~~~~~~ drivers/bus/mhi/core/main.c:837:19: note: shadowed declaration is here 837 | enum mhi_state new_state; | ^~~~~~~~~ Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2021-04-09soc: aspeed: Adapt to new LPC device tree layoutChia-Wei, Wang
Add check against LPC device v2 compatible string to ensure that the fixed device tree layout is adopted. The LPC register offsets are also fixed accordingly. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20210319062752.145730-5-andrew@aj.id.au Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-04-09pinctrl: aspeed-g5: Adapt to new LPC device tree layoutChia-Wei, Wang
Add check against LPC device v2 compatible string to ensure that the fixed device tree layout is adopted. The LPC register offsets are also fixed accordingly. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20210319062752.145730-4-andrew@aj.id.au Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-04-09ipmi: kcs: aspeed: Adapt to new LPC DTS layoutChia-Wei, Wang
Add check against LPC device v2 compatible string to ensure that the fixed device tree layout is adopted. The LPC register offsets are also fixed accordingly. Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Haiyue Wang <haiyue.wang@linux.intel.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20210319062752.145730-3-andrew@aj.id.au Signed-off-by: Joel Stanley <joel@jms.id.au>
2021-04-09ARM: dts: Remove LPC BMC and Host partitionsChia-Wei, Wang
The LPC controller has no concept of the BMC and the Host partitions. A concrete instance is that the HICRB[5:4] are for the I/O port address configurtaion of KCS channel 1/2. However, the KCS driver cannot access HICRB for channel 1/2 initialization via syscon regmap interface due to the parition boundary. (i.e. offset 80h) In addition, for the HW design backward compatibility, a newly added HW control bit could be located at any reserved one over the LPC addressing space. Thereby, this patch removes the lpc-bmc and lpc-host child node and thus the LPC partitioning. Note that this change requires the synchronization between device tree change and the driver change. To prevent the misuse of old devicetrees with new drivers, or vice versa, the v2 compatible strings are adopted for the LPC device as listed: "aspeed,ast2400-lpc-v2" "aspeed,ast2500-lpc-v2" "aspeed,ast2600-lpc-v2" Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20210319062752.145730-2-andrew@aj.id.au Signed-off-by: Joel Stanley <joel@jms.id.au>
generated by cgit (git 2.34.1) at 2025-10-01 09:49:01 +0000