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2017-04-24gpio: arizona: Correct check whether the pin is an inputCharles Keepax
The logic to check if the pin is an input or output whilst testing if we need to read the register value from the hardware or not is currently inverted. Remove the erroneous not from the if statement. Fixes: 11598d174050 ("gpio: arizona: Correct handling for reading input GPIOs") Signed-off-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-24gpio: Add XRA1403 DTS binding documentationNandor Han
Add the XRA1403 DTS binding documentation. Signed-off-by: Nandor Han <nandor.han@ge.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-24hwmon: (tmp103) Use SIMPLE_DEV_PM_OPS helper macroRahul Bedarkar
Replace ifdefs with SIMPLE_DEV_PM_OPS helper macro. Signed-off-by: Rahul Bedarkar <rahulbedarkar89@gmail.com> Acked-by: Heiko Schocher <hs@denx.de> Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2017-04-24dt-bindings: add exar to vendor prefixes listNandor Han
Add Exar Corporation to vendors list. Signed-off-by: Nandor Han <nandor.han@ge.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-24gpio: gpio-wcove: fix irq pending status bit widthKuppuswamy Sathyanarayanan
Whiskey cove PMIC has three GPIO banks with total number of 13 GPIO pins. But when checking for the pending status, for_each_set_bit() uses bit width of 7 and hence it only checks the status for first 7 GPIO pins missing to check/clear the status of rest of the GPIO pins. This patch fixes this issue. Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-24dma-debug: use offset_in_page() macroGeliang Tang
Use offset_in_page() macro instead of open-coding. Signed-off-by: Geliang Tang <geliangtang@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-04-24dmaengine: mv_xor: use offset_in_page() macroGeliang Tang
Use offset_in_page() macro instead of open-coding. Signed-off-by: Geliang Tang <geliangtang@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-04-24dmaengine: dmatest: use offset_in_page() macroGeliang Tang
Use offset_in_page() macro instead of open-coding. Signed-off-by: Geliang Tang <geliangtang@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
2017-04-24gpio: dwapb: use dwapb_read instead of readl_relaxedJisheng Zhang
Commit 67809b974a07 ("GPIO: gpio-dwapb: Change readl&writel to dwapb_read&dwapb_write") missed this readl_relaxed() usage, I'm not sure the reason, maybe for performance reason? But if we do care the performance, we could use the relaxed io in dwapb_read and dwapb_write. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-24pinctrl: aspeed: g5: Add pinconf supportAndrew Jeffery
Testing for pinctrl-aspeed-g5 was performed on an AST2500EVB system, using the strategy outlined in the commit message for the change to the Aspeed pinctrl core. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-24pinctrl: aspeed: g4: Add pinconf supportAndrew Jeffery
Testing for pinctrl-aspeed-g4 was performed on an OpenPOWER Palmetto system, using the strategy outlined in the commit message for the change to the Aspeed pinctrl core. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-24pinctrl: aspeed: Add core pinconf supportAndrew Jeffery
Several pinconf parameters have a fairly straight-forward mapping onto the Aspeed pin controller. These include management of pull-down bias, drive-strength, and some debounce configuration. Pin biasing largely is managed on a per-GPIO-bank basis, aside from the ADC and RMII/RGMII pins. As the bias configuration for each pin in a bank maps onto a single per-bank bit, configuration tables will be introduced to describe the ranges of pins and the supported pinconf parameter. The use of tables also helps with the sparse support of pinconf properties, and the fact that not all GPIO banks support biasing or drive-strength configuration. Further, as the pin controller uses a consistent approach for bias and drive strength configuration at the register level, a second table is defined for looking up the the bit-state required to enable or query the provided configuration. Testing for pinctrl-aspeed-g4 was performed on an OpenPOWER Palmetto system, and pinctrl-aspeed-g5 on an AST2500EVB as well as under QEMU. The test method was to set the appropriate bits via devmem and verify the result through the controller's pinconf-pins debugfs file. This simultaneously validates the get() path and half of the set() path. The remainder of the set() path was validated by configuring a handful of pins via the devicetree with the supported pinconf properties and verifying the appropriate registers were touched. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-24gpio: aspeed: Add open-source and open-drain supportAndrew Jeffery
As per the datasheet, manage the IO and value states to implement open-source/open-drain, but do this by falling back to gpiolib's emulation. This commit simply makes the behaviour explicit for clarity, rather than relying on the implicit return of -ENOTSUPP to trigger the emulation. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-24gpio: aspeed: Add debounce supportAndrew Jeffery
Each GPIO in the Aspeed GPIO controller can choose one of four input debounce states: to disable debouncing for an input, or select from one of three programmable debounce timer values. Each GPIO in a four-bank-set is assigned one bit in each of two debounce configuration registers dedicated to the set, and selects a debounce state by configuring the two bits to select one of the four options. The limitation on debounce timer values is managed by mapping offsets onto a configured timer value and keeping count of the number of users a timer has. Timer values are configured on a first-come-first-served basis. A small twist in the hardware design is that the debounce configuration register numbering is reversed with respect to the binary representation of the debounce timer of interest (i.e. debounce register 1 represents bit 1, and debounce register 2 represents bit 0 of the timer numbering). Tested on an AST2500EVB with additional inspection under QEMU's romulus-bmc machine. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-24gpio: aspeed: dt: Add optional clocks propertyAndrew Jeffery
We need a reference to the HPLL to calculate debounce cycles. If the clocks property is not supplied in the GPIO node then the consumer should deny any debounce requests. Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-24gpio: aspeed: dt: Fix description alignment in bindings documentAndrew Jeffery
Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-24pinctrl: aspeed: Document pinconf in devicetree bindingsAndrew Jeffery
Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Joel Stanley <joel@jms.id.au> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-24pinctrl: Add st,stm32f469-pinctrl compatible to stm32-pinctrlAlexandre TORGUE
Add new compatible for stm32f469 MCU. Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-24drm: mali-dp: Check the mclk rate and allow up/down scalingMihail Atanassov
When downscaling, mclk needs to be sufficiently higher than pxlclk in order to be able to fetch the higher-resolution data and produce output pixels. When not scaling, or when upscaling, mclk can be equal to pxlclk. Since the driver doesn't control mclk, just ensure that the requirement is satisfied with the current clock rate. Signed-off-by: Mihail Atanassov <mihail.atanassov@arm.com> Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
2017-04-24drm: mali-dp: Enable image enhancement when scalingMihail Atanassov
Apply image enhacement when we are upscaling by a factor of 2 or more in either direction. Signed-off-by: Mihail Atanassov <mihail.atanassov@arm.com> Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
2017-04-24drm: mali-dp: Add plane upscaling supportMihail Atanassov
Enable the scaling engine for upscaling a single plane using the polyphase scaler. No image enhancement support or downscaling yet*, and composition result scaling is not implemented. * Downscaling a plane requires mclk > pxlclk. Signed-off-by: Mihail Atanassov <mihail.atanassov@arm.com> Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
2017-04-24pinctrl: stm32: Add STM32F469 MCU supportAlexandre TORGUE
This patch which adds STM32F469 pinctrl and GPIO support, relies on the generic STM32 pinctrl driver. Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-24Documentation: dt: Remove ngpios from stm32-pinctrl bindingAlexandre TORGUE
Remove "ngpios" bindings definition as it is no more used in stm32 pinctrl driver. Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-24pinctrl: stm32: replace device_initcall() with arch_initcall()Alexandre TORGUE
Pinctrl has to be registered earlier. Mainly to register bank irqdomain earlier as other devices could use interrupts from those irqdomain. Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-24pinctrl: stm32: add possibility to use gpio-ranges to declare bank rangeAlexandre TORGUE
Use device tree entries to declare gpio range. It will allow to use no contiguous gpio bank and holes inside a bank. Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-24pinctrl: armada-37xx: Add gpio supportGregory CLEMENT
GPIO management is pretty simple and is part of the same IP than the pin controller for the Armada 37xx SoCs. This patch adds the GPIO support to the pinctrl-armada-37xx.c file, it also allows sharing common functions between the gpiolib and the pinctrl drivers. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-24arm64: Add CNTFRQ_EL0 trap handlerMarc Zyngier
We now trap accesses to CNTVCT_EL0 when the counter is broken enough to require the kernel to mediate the access. But it turns out that some existing userspace (such as OpenMPI) do probe for the counter frequency, leading to an UNDEF exception as CNTVCT_EL0 and CNTFRQ_EL0 share the same control bit. The fix is to handle the exception the same way we do for CNTVCT_EL0. Fixes: a86bd139f2ae ("arm64: arch_timer: Enable CNTVCT_EL0 trap if workaround is enabled") Reported-by: Hanjun Guo <guohanjun@huawei.com> Tested-by: Hanjun Guo <guohanjun@huawei.com> Reviewed-by: Hanjun Guo <guohanjun@huawei.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2017-04-24tty: fix comment for __tty_alloc_driver()Thadeu Lima de Souza Cascardo
Signed-off-by: Thadeu Lima de Souza Cascardo <cascardo@cascardo.eti.br> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
2017-04-24init/main: properly align the multi-line commentViresh Kumar
Add a tab before it to follow standard practices. Also add the missing full stop '.'. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
2017-04-24init/main: Fix double "the" in commentViresh Kumar
s/the\ the/the Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
2017-04-24iommu/amd: Fix incorrect error handling in amd_iommu_bind_pasid()Pan Bian
In function amd_iommu_bind_pasid(), the control flow jumps to label out_free when pasid_state->mm and mm is NULL. And mmput(mm) is called. In function mmput(mm), mm is referenced without validation. This will result in a NULL dereference bug. This patch fixes the bug. Signed-off-by: Pan Bian <bianpan2016@163.com> Fixes: f0aac63b873b ('iommu/amd: Don't hold a reference to mm_struct') Signed-off-by: Joerg Roedel <jroedel@suse.de>
2017-04-24crypto: algif_aead - Require setkey before accept(2)Stephan Mueller
Some cipher implementations will crash if you try to use them without calling setkey first. This patch adds a check so that the accept(2) call will fail with -ENOKEY if setkey hasn't been done on the socket yet. Fixes: 400c40cf78da ("crypto: algif - add AEAD support") Cc: <stable@vger.kernel.org> Signed-off-by: Stephan Mueller <smueller@chronox.de> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-04-24crypto: scomp - add support for deflate rfc1950 (zlib)Giovanni Cabiddu
Add scomp backend for zlib-deflate compression algorithm. This backend outputs data using the format defined in rfc1950 (raw deflate surrounded by zlib header and footer). Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-04-24crypto: scomp - allow registration of multiple scompsGiovanni Cabiddu
Add crypto_register_scomps and crypto_unregister_scomps to allow the registration of multiple implementations with one call. Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-04-24crypto: ccp - Change ISR handler method for a v5 CCPGary R Hook
The CCP has the ability to perform several operations simultaneously, but only one interrupt. When implemented as a PCI device and using MSI-X/MSI interrupts, use a tasklet model to service interrupts. By disabling and enabling interrupts from the CCP, coupled with the queuing that tasklets provide, we can ensure that all events (occurring on the device) are recognized and serviced. This change fixes a problem wherein 2 or more busy queues can cause notification bits to change state while a (CCP) interrupt is being serviced, but after the queue state has been evaluated. This results in the event being 'lost' and the queue hanging, waiting to be serviced. Since the status bits are never fully de-asserted, the CCP never generates another interrupt (all bits zero -> one or more bits one), and no further CCP operations will be executed. Cc: <stable@vger.kernel.org> # 4.9.x+ Signed-off-by: Gary R Hook <gary.hook@amd.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-04-24crypto: ccp - Change ISR handler method for a v3 CCPGary R Hook
The CCP has the ability to perform several operations simultaneously, but only one interrupt. When implemented as a PCI device and using MSI-X/MSI interrupts, use a tasklet model to service interrupts. By disabling and enabling interrupts from the CCP, coupled with the queuing that tasklets provide, we can ensure that all events (occurring on the device) are recognized and serviced. This change fixes a problem wherein 2 or more busy queues can cause notification bits to change state while a (CCP) interrupt is being serviced, but after the queue state has been evaluated. This results in the event being 'lost' and the queue hanging, waiting to be serviced. Since the status bits are never fully de-asserted, the CCP never generates another interrupt (all bits zero -> one or more bits one), and no further CCP operations will be executed. Cc: <stable@vger.kernel.org> # 4.9.x+ Signed-off-by: Gary R Hook <gary.hook@amd.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-04-24crypto: crypto4xx - rename ce_ring_contol to ce_ring_controlColin Ian King
trivial spelling mistake, missing r, rename to ce_ring_control Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-04-24crypto: testmgr - Allow ecb(cipher_null) in FIPS modeMilan Broz
The cipher_null is not a real cipher, FIPS mode should not restrict its use. It is used for several tests (for example in cryptsetup testsuite) and also temporarily for reencryption of not yet encrypted device in cryptsetup-reencrypt tool. Problem is easily reproducible with cryptsetup benchmark -c null Signed-off-by: Milan Broz <gmazyland@gmail.com> Acked-by: Stephan Müller <smueller@chronox.de> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-04-24drm/mali-dp: Add core_id file to the sysfs interfaceLiviu Dudau
Add a core_id file in the driver's sysfs directory, exposing the hardware CORE ID. This is useful to allow userspace to discover the hardware version used. Signed-off-by: Mihail Atanassov <mihail.atanassov@arm.com> Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
2017-04-24drm: mali-dp: Add CTM supportMihail Atanassov
All DPs have a COLORADJ matrix which is applied prior to output gamma. Attach that to the CTM property. Also, ensure the input CTM's coefficients can fit in the DP registers' Q3.12 format. Signed-off-by: Mihail Atanassov <mihail.atanassov@arm.com> Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
2017-04-24drm: mali-dp: enable gamma supportMihail Atanassov
Add gamma via the DRM GAMMA_LUT/GAMMA_LUT_SIZE CRTC properties. The expected LUT size is 4096 in order to produce as accurate a set of segments as possible. This version uses only the green channel's gamma curve to set the hardware curve on DP550/650. For the sake of simplicity, it uses the same table of coefficients for all 3 curves on DP500. Signed-off-by: Mihail Atanassov <mihail.atanassov@arm.com> Signed-off-by: Liviu Dudau <liviu.dudau@arm.com>
2017-04-24drm: mali-dp: add malidp_crtc_state structMihail Atanassov
Add a custom CRTC state struct to enable storing driver's private state. This patch only adds the base drm_crtc_state struct and the atomic functions that handle it. Signed-off-by: Mihail Atanassov <mihail.atanassov@arm.com> Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
2017-04-24drm: mali-dp: add custom reset hook for planesMihail Atanassov
Now that we are using a custom plane state in mali-dp, we need a bespoke reset that takes into account the larger structure. Signed-off-by: Mihail Atanassov <mihail.atanassov@arm.com> [Updated commit message] Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
2017-04-24drm: mali-dp: remove unused variableArnd Bergmann
The newly introduced function causes a harmless build warning: drivers/gpu/drm/arm/malidp_planes.c: In function 'malidp_plane_atomic_print_state': drivers/gpu/drm/arm/malidp_planes.c:98:23: error: unused variable 'mp' [-Werror=unused-variable] The variable serves no purpose here and can be removed. Fixes: 242f43b69c61 ("drm: mali-dp: add atomic_print_state for planes") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Liviu Dudau <Liviu.Dudau@arm.com> Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
2017-04-24drm: mali-dp: add atomic_print_state for planesMihail Atanassov
Add function to dump the state of the plane. Signed-off-by: Mihail Atanassov <mihail.atanassov@arm.com> Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
2017-04-24drm: mali-dp: Enable power management for the device.Liviu Dudau
Enable runtime and system Power Management. Clocks are now managed from malidp_crtc_{enable,disable} functions. Suspend-to-RAM tested as working on Juno. Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
2017-04-24drm: mali-dp: Update the state of all planes before re-enabling active CRTCs.Liviu Dudau
Mali DP needs to have all the planes that are becoming inactive in the new state disabled before re-enabling the active CRTC, otherwise we start streaming out data from old pointers in memory. Signed-off-by: Liviu Dudau <Liviu.Dudau@arm.com>
2017-04-24pinctrl: armada-37xx: Add pin controller support for Armada 37xxGregory CLEMENT
The Armada 37xx SoC come with 2 pin controllers: one on the south bridge (managing 28 pins) and one on the north bridge (managing 36 pins). At the hardware level the controller configure the pins by group and not pin by pin. This constraint is reflected in the design of the driver: only the group related functions are implemented. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-24pinctrl: dt-bindings: Add documentation for Armada 37xx pin controllersGregory CLEMENT
Document the device tree binding for the pin controllers found on the Armada 37xx SoCs. Update the binding documention of the xtal clk which is a subnode of this syscon node. Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org> [Fixed gpios node] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2017-04-24Merge tag 'vfio-ccw-20170413' of ↵Martin Schwidefsky
git://git.kernel.org/pub/scm/linux/kernel/git/kvms390/vfio-ccw into features Pull vfio-ccw fixes from Cornelia Huck: Two fixes for the new vfio-ccw support.
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