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2025-01-07dt-bindings: clock: Add Qualcomm SM6115 LPASS clock controllerKonrad Dybcio
SM6115 (and its derivatives or similar SoCs) has an LPASS clock controller block which provides audio-related resets. Add bindings for it. Cc: Konrad Dybcio <konradybcio@kernel.org> Cc: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Cc: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> [alexey.klimov slightly changed the commit message] Signed-off-by: Alexey Klimov <alexey.klimov@linaro.org> Link: https://lore.kernel.org/r/20241212002551.2902954-2-alexey.klimov@linaro.org [bjorn: Adjusted Konrad's address] Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-07clk: qcom: gcc-sdm845: Do not use shared clk_ops for QUPsAmit Pundir
Similar to the earlier fixes meant for sm8x50 and x1e platforms, we have to stop using the shared clk ops for sdm845 QUPs as well. As Stephen Boyd pointed out in earlier fixes, there wasn't a problem to mark QUP clks shared until we started parking shared RCGs at clk registration time in commit 01a0a6cc8cfd ("clk: qcom: Park shared RCGs upon registration"). Parking at init is actually harmful to the UART when earlycon is used. If the device is pumping out data while the frequency changes and we see garbage on the serial console until the driver can probe and actually set a proper frequency. This patch reverts the QUP clk sharing ops part of commit 06391eddb60a ("clk: qcom: Add Global Clock controller (GCC) driver for SDM845"), so that the QUPs on sdm845 don't get parked during clk registration and break UART operations. Fixes: 01a0a6cc8cfd ("clk: qcom: Park shared RCGs upon registration") Signed-off-by: Amit Pundir <amit.pundir@linaro.org> Link: https://lore.kernel.org/r/20241209174912.2526928-1-amit.pundir@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-07clk: clocking-wizard: calculate dividers fractional partsShubhrajyoti Datta
Calculate dividers fractional parts to optimally modulate output frequency. Clocking wizard supports having multiplier m and divisors d and o. Currently the fractional parts of m and o are not utilised. For the pixel clock usecases a higher accuracy is needed.. Adding support for m and o to have fractional values. Co-developed-by: Anatoliy Klymenko <anatoliy.klymenko@amd.com> Signed-off-by: Anatoliy Klymenko <anatoliy.klymenko@amd.com> Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> Tested-by: Anatoliy Klymenko <anatoliy.klymenko@amd.com> Link: https://lore.kernel.org/r/20250106082937.29555-1-shubhrajyoti.datta@amd.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-01-07dt-bindings: clock: xilinx: Add reset GPIO for VCURohit Visavalia
It is marked as optional as some of the ZynqMP designs are having vcu_reset (reset pin of VCU IP) driven by proc_sys_reset, proc_sys_reset is another PL IP driven by the PS pl_reset. So, here the VCU reset is not driven by axi_gpio or PS GPIO so there will be no GPIO entry. Signed-off-by: Rohit Visavalia <rohit.visavalia@amd.com> Link: https://lore.kernel.org/r/20250107044038.100945-3-rohit.visavalia@amd.com Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-01-07dt-bindings: clock: xilinx: Convert VCU bindings to dtschemaRohit Visavalia
Convert AMD (Xilinx) VCU bindings to yaml format. Additional changes: - move xlnx_vcu DT binding to clock from soc following commit a2fe7baa27a4 ("clk: xilinx: move xlnx_vcu clock driver from soc") - corrected clock sequence as per xilinx device-tree generator Signed-off-by: Rohit Visavalia <rohit.visavalia@xilinx.com> Link: https://lore.kernel.org/r/20250107044038.100945-2-rohit.visavalia@amd.com Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-01-07Merge tag 'renesas-clk-for-v6.14-tag2' of ↵Stephen Boyd
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-renesas Pull Renesas clk driver updates from Geert Uytterhoeven: - Add support for the RZ/G3E (R9A09G047) SoC - Add Module Stop (MSTOP) support on RZ/V2H - Add Image Signal Processor helper block (FCPVX and VSPX) clocks on R-Car V4H SoC - Add System Controller (SYS) reset and Generic Interrupt Controller (GIC) clock and reset entries on RZ/V2H * tag 'renesas-clk-for-v6.14-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers: dt-bindings: clock: renesas,r9a08g045-vbattb: Fix include guard clk: renesas: r9a09g057: Add clock and reset entries for GIC clk: renesas: r9a09g057: Add reset entry for SYS clk: renesas: r8a779g0: Add VSPX clocks clk: renesas: r8a779g0: Add FCPVX clocks clk: renesas: r9a09g047: Add I2C clocks/resets clk: renesas: r9a09g047: Add CA55 core clocks clk: renesas: rzv2h: Add support for RZ/G3E SoC clk: renesas: rzv2h: Add MSTOP support dt-bindings: clock: renesas: Document RZ/G3E SoC CPG dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK dt-bindings: soc: renesas: Document Renesas RZ/G3E SoC variants
2025-01-07Merge tag 'clk-microchip-6.14' of ↵Stephen Boyd
https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into clk-microchip Pull Microchip clk driver updates from Claudiu Beznea: - Support for the SAMA7D65 SoC - Clock IDs for for the slow clock controller * tag 'clk-microchip-6.14' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: clk: at91: sama7d65: add sama7d65 pmc driver dt-bindings: clock: Add SAMA7D65 PMC compatible string dt-bindings: clocks: atmel,at91sam9x5-sckc: add sama7d65 clk: at91: sckc: Use SCKC_{TD, MD}_SLCK IDs for clk32k clocks dt-bindings: clk: at91: Add clock IDs for the slow clock controller
2025-01-07clk: qcom: gcc-sdm845: Add general purpose clock opsDzmitry Sankouski
SDM845 has "General Purpose" clocks that can be muxed to SoC pins to clock various external devices. Those clocks may be used as e.g. PWM sources for external peripherals. GPCLK can in theory have arbitrary value depending on the use case, so the concept of frequency tables, used in rcg2 clock driver, is not efficient, because it allows only defined frequencies. Introduce clk_rcg2_gp_ops, which automatically calculate clock mnd values for arbitrary clock rate. The calculation done as follows: - upon determine rate request, we calculate m/n/pre_div as follows: - find parent(from our client's assigned-clock-parent) rate - find scaled rates by dividing rates on its greatest common divisor - assign requested scaled rate to m - factorize scaled parent rate, put multipliers to n till max value (determined by mnd_width) - validate calculated values with *_width: - if doesn't fit, delete divisor and multiplier by 2 until fit - return determined rate Limitations: - The driver doesn't select a parent clock (it may be selected by client in device tree with assigned-clocks, assigned-clock-parents properties) Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com> Link: https://lore.kernel.org/r/20241118-starqltechn_integration_upstream-v8-3-ac8e36a3aa65@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-07clk: qcom: clk-rcg2: split __clk_rcg2_configure functionDzmitry Sankouski
__clk_rcg2_configure function does 2 things - configures parent and mnd values. In order to be able to add new clock options, we should split. Move __clk_rcg2_configure logic on 2 functions: - __clk_rcg2_configure_parent which configures clock parent - __clk_rcg2_configure_mnd which configures mnd values __clk_rcg2_configure delegates to mentioned functions. Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com> Link: https://lore.kernel.org/r/20241118-starqltechn_integration_upstream-v8-2-ac8e36a3aa65@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-07clk: qcom: clk-rcg2: document calc_rate functionDzmitry Sankouski
Update calc_rate docs to reflect, that pre_div is not pure divisor, but a register value, and requires conversion. Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com> Link: https://lore.kernel.org/r/20241118-starqltechn_integration_upstream-v8-1-ac8e36a3aa65@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-07clk: qcom: gcc-x1e80100: Do not turn off usb_2 controller GDSCAbel Vesa
Allowing the usb_2 controller GDSC to be turned off during system suspend renders the controller unable to resume. So use PWRSTS_RET_ON instead in order to make sure this the GDSC doesn't go down. Fixes: 161b7c401f4b ("clk: qcom: Add Global Clock controller (GCC) driver for X1E80100") Cc: stable@vger.kernel.org # 6.8 Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Tested-by: Johan Hovold <johan+linaro@kernel.org> Link: https://lore.kernel.org/r/20250107-x1e80100-clk-gcc-fix-usb2-gdsc-pwrsts-v1-1-e15d1a5e7d80@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-07dt-bindings: clock: renesas,r9a08g045-vbattb: Fix include guardGeert Uytterhoeven
Add the missing "RENESAS" part to the include guard. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/34953d1e9f472e4f29533ed06cf092dd3c0d1178.1736238939.git.geert+renesas@glider.be
2025-01-07clk: renesas: r9a09g057: Add clock and reset entries for GICLad Prabhakar
Add clock and reset entries for GIC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250102181839.352599-7-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-01-07clk: renesas: r9a09g057: Add reset entry for SYSLad Prabhakar
Add the missing reset entry for the `SYS` module in the clock driver. The corresponding core clock entry for `SYS` is already present. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250102181839.352599-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-01-07clk: renesas: r8a779g0: Add VSPX clocksJacopo Mondi
Add the VSPX modules clock for Renesas R-Car V4H (R8A779G0) SoC. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Jacopo Mondi <jacopo.mondi+renesas@ideasonboard.com> Link: https://lore.kernel.org/20241220-rcar-v4h-vspx-v4-3-7dc1812585ad@ideasonboard.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-01-07clk: renesas: r8a779g0: Add FCPVX clocksJacopo Mondi
Add the FCPVX modules clock for Renesas R-Car V4H (R8A779G0) SoC. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by: Jacopo Mondi <jacopo.mondi+renesas@ideasonboard.com> Link: https://lore.kernel.org/20241220-rcar-v4h-vspx-v4-1-7dc1812585ad@ideasonboard.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-01-07clk: renesas: r9a09g047: Add I2C clocks/resetsBiju Das
Add I2C{0..8} clock and reset entries. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241216120029.143944-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-01-07clk: renesas: r9a09g047: Add CA55 core clocksBiju Das
Add CA55 core clocks which are derived from PLLCA55. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/20241213123550.289193-4-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-01-07clk: renesas: rzv2h: Add support for RZ/G3E SoCBiju Das
The clock structure for RZ/G3E is almost identical to RZ/V2H SoC with more IP blocks compared to RZ/V2H. For eg: VSPI, LVDS, DPI and LCDC1 are present only on the RZ/G3E SoC. Add minimal clock and reset entries required to boot the Renesas RZ/G3E SMARC EVK and binds it with the RZ/V2H CPG core driver. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://lore.kernel.org/20241213123550.289193-3-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-01-07Merge tag 'renesas-r9a09g047-dt-binding-defs-tag1' into renesas-clk-for-v6.14Geert Uytterhoeven
Renesas RZ/G3E DT Binding Definitions DT bindings and binding definitions for the Renesas RZ/G3E (R9A09G047) SoC, shared by driver and DT source files.
2025-01-07clk: renesas: rzv2h: Add MSTOP supportBiju Das
Add MSTOP support to control buses for the individual units on RZ/V2H. Use per-bit (instead of group-based) configuration and atomic counters, to ensure precise control over individual MSTOP bits, and to prevent issues with shared dependencies between module clocks. Co-developed-by: Biju Das <biju.das.jz@bp.renesas.com> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Co-developed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20241213123550.289193-2-biju.das.jz@bp.renesas.com Link: https://lore.kernel.org/20250102181839.352599-2-prabhakar.mahadev-lad.rj@bp.renesas.com Link: https://lore.kernel.org/20250102181839.352599-3-prabhakar.mahadev-lad.rj@bp.renesas.com Link: https://lore.kernel.org/20250102181839.352599-4-prabhakar.mahadev-lad.rj@bp.renesas.com Link: https://lore.kernel.org/20250102181839.352599-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-01-06clk: qcom: ipq5424: add gcc_xo_clkManikanta Mylavarapu
The gcc_xo_clk is required for the functionality of the WiFi copy engine block. Therefore, add the gcc_xo_clk in gcc driver. Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com> Link: https://lore.kernel.org/r/20241210064110.130466-3-quic_mmanikan@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06dt-bindings: clock: qcom: gcc-ipq5424: add gcc_xo_clk macroManikanta Mylavarapu
The GCC_XO_CLK is required for the functionality of the WiFi copy engine block. Therefore, add the GCC_XO_CLK macro. Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20241210064110.130466-2-quic_mmanikan@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06dt-bindings: clock: qcom: gcc-ipq5424: remove apss_dbg clock macroManikanta Mylavarapu
The gcc_apss_dbg clk is access protected by trust zone, and accessing it results in a kernel crash. Therefore remove the gcc_apss_dbg_clk macro. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com> Link: https://lore.kernel.org/r/20241217113909.3522305-3-quic_mmanikan@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06clk: qcom: ipq5424: remove apss_dbg clockManikanta Mylavarapu
The gcc_apss_dbg clk is access protected by trust zone, and accessing it results in a kernel crash. Therefore remove the gcc_apss_dbg_clk from the gcc driver. Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com> Link: https://lore.kernel.org/r/20241217113909.3522305-2-quic_mmanikan@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06dt-bindings: clock: qcom,sdm845-camcc: add sdm670 compatibleRichard Acayan
The camera clocks on SDM670 and SDM845 have no significant differences that would require a change in the clock controller driver. The only difference is the clock frequency at each level of the power domains, which is not specified in the clock driver. There should still be a compatible specific to the SoC, so add the compatible for SDM670 with the SDM845 compatible as fallback. Link: https://android.googlesource.com/kernel/msm/+/d4dc50c0a9291bd99895d4844f973421c047d267/drivers/clk/qcom/camcc-sdm845.c#2048 Suggested-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Suggested-by: Konrad Dybcio <konradybcio@kernel.org> Link: https://lore.kernel.org/linux-arm-msm/7d26a62b-b898-4737-bd53-f49821e3b471@linaro.org Signed-off-by: Richard Acayan <mailingradian@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20241218231729.270137-8-mailingradian@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06Merge tag 'socfpga_clk_update_for_v6.14' of ↵Stephen Boyd
git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into clk-socfpga Pull a SoCFPGA clk driver update from Dinh Nguyen: - Optimize local variables in clk_pll_recalc_rate() for Arria10 * tag 'socfpga_clk_update_for_v6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux: clk: socfpga: arria10: Optimize local variables in clk_pll_recalc_rate()
2025-01-06clk: qcom: mmcc-msm8960: handle LVDS clockDmitry Baryshkov
On APQ8064 the DSI2_PIXEL_SRC clock can be used either to drive the second DSI host or to drive the LCDC controller. Add LVDS PLL as possible source to the clock and LVDS output clock. The DSI2_PIXEL_SRC clock has separate path to be used for the LVDS clock. To represent both DSI and LVDS clocks properly, add intermediate clock which toggles the enable bit and make DSI2_PIXEL_CLK clock just check for the HALT bit. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-apq8064-fix-mmcc-v1-4-c95d2e2bf143@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06clk: qcom: rcg: add 1/1 pixel clock ratioDmitry Baryshkov
LVDS clocks require 1:1 ration support in the table used by clk_rcg_pixel_ops. Add corresponding divider to the table. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241224-apq8064-fix-mmcc-v1-3-c95d2e2bf143@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06dt-bindings: clock: qcom,mmcc-msm8960: add LCDC-related clocksDmitry Baryshkov
APQ8064 / MSM8960 have separate LVDS / LCDC clock, driving the MDP4 LCD controller. Add corresponding indices to clock controller bindings. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20241224-apq8064-fix-mmcc-v1-2-c95d2e2bf143@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06dt-bindings: clock: qcom,mmcc: support LVDS PLL input for apq8064Dmitry Baryshkov
APQ8064 / MSM8960 have separate LVDS PLL driving the LVDS / LCDC clock. Add corresponding input to clock controller bindings. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20241224-apq8064-fix-mmcc-v1-1-c95d2e2bf143@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06clk: ti: use kcalloc() instead of kzalloc()Ethan Carter Edwards
Use 2-factor multiplication argument form kcalloc() instead of kzalloc(). Link: https://github.com/KSPP/linux/issues/162 Signed-off-by: Ethan Carter Edwards <ethan@ethancedwards.com> Link: https://lore.kernel.org/r/xfjn4wqrhukvi45dkgkbulamq3242eijn7567vxwaxznh4ebdr@waat7u3l2mhi Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-01-06dt-bindings: clock: st,stm32mp1-rcc: complete the reference pathDario Binacchi
All other paths referenced in the file follow a scheme starting from the Linux root. The patch adjusts the single file that deviated from this scheme, making it consistent with the others. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Link: https://lore.kernel.org/r/20241231150144.4035938-2-dario.binacchi@amarulasolutions.com Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-01-06dt-bindings: clock: st,stm32mp1-rcc: fix reference pathsDario Binacchi
The path of the two files was wrong even at the time they were added. Let's fix them so they can be correctly referenced. Fixes: 722dc8a1d5c8 ("dt-bindings: rcc: stm32: add new compatible for STM32MP13 SoC") Fixes: 20107d7328cc ("dt-bindings: rcc: Convert stm32mp1 rcc bindings to json-schema") Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Link: https://lore.kernel.org/r/20241231150144.4035938-1-dario.binacchi@amarulasolutions.com Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-01-06dt-bindings: clock: ti: Convert composite.txt to json-schemaAndreas Kemnade
Convert the OMAP gate clock device tree binding to json-schema. Specify the creator of the original binding as a maintainer. Choose GPL-only license because original binding was also GPL. Signed-off-by: Andreas Kemnade <andreas@kemnade.info> Link: https://lore.kernel.org/r/20250105170854.408875-3-andreas@kemnade.info Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-01-06dt-bindings: clock: ti: Convert gate.txt to json-schemaAndreas Kemnade
Convert the OMAP gate clock device tree binding to json-schema. Specify the creator of the original binding as a maintainer. Choose GPL-only license because original binding was also GPL. Clean up the examples during conversion to meet modern standards and remove examples with no additional value. Due to usage in code and existing devicetree binding, add the ti,set-rate-parent property. Signed-off-by: Andreas Kemnade <andreas@kemnade.info> Link: https://lore.kernel.org/r/20250105170854.408875-2-andreas@kemnade.info Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2025-01-06clk: qcom: Add CMN PLL clock controller driver for IPQ SoCLuo Jie
The CMN PLL clock controller supplies clocks to the hardware blocks that together make up the Ethernet function on Qualcomm IPQ SoCs and to GCC. The driver is initially supported for IPQ9574 SoC. The CMN PLL clock controller expects a reference input clock from the on-board Wi-Fi block acting as clock source. The input reference clock needs to be configured to one of the supported clock rates. The controller supplies a number of fixed-rate output clocks. For the IPQ9574, there is one output clock of 353 MHZ to PPE (Packet Process Engine) hardware block, three 50 MHZ output clocks and an additional 25 MHZ output clock supplied to the connected Ethernet devices. The PLL also supplies a 24 MHZ clock as XO and a 32 KHZ sleep clock to GCC, and one 31.25 MHZ clock to PCS. Signed-off-by: Luo Jie <quic_luoj@quicinc.com> Acked-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250103-qcom_ipq_cmnpll-v8-2-c89fb4d4849d@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06Merge branch '20250103-qcom_ipq_cmnpll-v8-1-c89fb4d4849d@quicinc.com' into ↵Bjorn Andersson
clk-for-6.14 Merge the IPQ CMN PLL clock binding through a topic branch to make it available to DeviceTree source branches as well.
2025-01-06dt-bindings: clock: qcom: Add CMN PLL clock controller for IPQ SoCLuo Jie
The CMN PLL controller provides clocks to networking hardware blocks and to GCC on Qualcomm IPQ9574 SoC. It receives input clock from the on-chip Wi-Fi, and produces output clocks at fixed rates. These output rates are predetermined, and are unrelated to the input clock rate. The primary purpose of CMN PLL is to supply clocks to the networking hardware such as PPE (packet process engine), PCS and the externally connected switch or PHY device. The CMN PLL block also outputs fixed rate clocks to GCC, such as 24 MHZ as XO clock and 32 KHZ as sleep clock supplied to GCC. Signed-off-by: Luo Jie <quic_luoj@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250103-qcom_ipq_cmnpll-v8-1-c89fb4d4849d@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06clk: qcom: dispcc-sm8750: Add SM8750 Display clock controllerKrzysztof Kozlowski
Add driver for Display clock controller (DISPCC) in Qualcomm SM8750. The device has several differences against SM8650, including new Pongo PLLs and different clock parents, thus no compatibility or driver re-usage. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250106-sm8750-dispcc-v2-3-6f42beda6317@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06clk: qcom: clk-alpha-pll: Add Pongo PLLKrzysztof Kozlowski
Add support for Pongo type of PLL clocks, used in Qualcomm SM8750 SoC. Notable difference comparing to other PLLs is the need for calibration for internally generated clock followed by wait_for_pll(). This is done in configure call and at this time clocks are not yet registered, thus wait_for_pll() cannot use clk_hw_get_name. Locking during this calibration requires much more time, thus increase the timeout in wait_for_pll(). Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250106-sm8750-dispcc-v2-2-6f42beda6317@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06Merge branch '20250106-sm8750-dispcc-v2-1-6f42beda6317@linaro.org' into ↵Bjorn Andersson
clk-for-6.14 Merge SM8750 display clock controller bindings through topic branch, to make available to DeviceTree source branch as well.
2025-01-06dt-bindings: clock: qcom,sm8550-dispcc: Add SM8750 DISPCCKrzysztof Kozlowski
Add bindings for the Qualcomm SM8750 Display Clock Controller (DISPCC). Bindings are similar to existing SM8550 and SM8650 (same clock inputs), but the clock hierarchy is quite different and these are not compatible devices. The binding header was copied from downstream sources, so I retained original copyrights. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250106-sm8750-dispcc-v2-1-6f42beda6317@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06clk: qcom: Add TCSR clock driver for SM8750Taniya Das
The TCSR clock controller found on SM8750 provides refclks for PCIE, USB and UFS. Add clock driver for it. Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20241204-sm8750_master_clks-v3-8-1a8f31a53a86@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06clk: qcom: Add support for GCC on SM8750Taniya Das
Add support for GCC for SM8750 platform. Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241204-sm8750_master_clks-v3-6-1a8f31a53a86@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06clk: qcom: clk-alpha-pll: Add support for controlling Taycan PLLsTaniya Das
Add clock ops for Taycan PLL, add the register offsets for supporting the PLL. Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20241204-sm8750_master_clks-v3-4-1a8f31a53a86@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06clk: qcom: rpmh: Add support for SM8750 rpmh clocksTaniya Das
Add the RPMH clocks present in SM8750 SoC. Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241204-sm8750_master_clks-v3-3-1a8f31a53a86@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06clk: qcom: rpmh: Sort the match table alphabeticallyTaniya Das
Update the match table for SC7280 to sort it in alphabetical order. Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20241204-sm8750_master_clks-v3-2-1a8f31a53a86@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06dt-bindings: clock: qcom-rpmhcc: Add RPMHCC for SM8750Taniya Das
Update the documentation for clock rpmh driver on SM8750 SoCs. Signed-off-by: Melody Olvera <quic_molvera@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20241204-sm8750_master_clks-v3-1-1a8f31a53a86@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2025-01-06Merge branch '20241204-sm8750_master_clks-v3-0-1a8f31a53a86@quicinc.com' ↵Bjorn Andersson
into clk-for-6.14 Merge the SM8750 GCC and TCSR clock bindings through topic branch, to allow merging into DeviceTree source branch as well.
generated by cgit (git 2.34.1) at 2025-09-21 23:24:58 +0000