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2025-07-02clk: renesas: r9a09g057: Add support for xspi mux and dividerLad Prabhakar
The mux smux2_xspi_clk{0,1} used for selecting spi and spix2 clocks and pllcm33_xspi divider to select different clock rates. Add support for both. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250627204237.214635-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-07-02clk: renesas: r9a09g056: Add support for xspi mux and dividerLad Prabhakar
The mux smux2_xspi_clk{0,1} used for selecting spi and spix2 clocks and pllcm33_xspi divider to select different clock rates. Add support for both. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250627204237.214635-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-07-02Merge tag 'renesas-r9a09g057-dt-binding-defs-tag4' into renesas-clk-for-v6.17Geert Uytterhoeven
Renesas RZ/V2N and RZ/V2H XSPI Clock DT Binding Definitions Expanded Serial Peripheral Interface (XSPI) clock DT binding definitions for the Renesas RZ/V2N (R9A09G056) and RZ/V2H (R9A09G057) SoCs, shared by driver and DT source files.
2025-07-02clk: renesas: r9a09g077: Add RIIC module clocksLad Prabhakar
Add RIIC module clocks for: iic0, iic1, and iic2. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250625141705.151383-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-07-02clk: renesas: r9a09g077: Add PLL2 and SDHI clock supportLad Prabhakar
Add support for PLL2 to the R9A09G077 (RZ/T2H) clock definitions and register it as the source for the high-speed SDHI clock (SDHI_CLKHS) operating at 800MHz. Also add fixed-factor clock PCLKAM derived from CLK_PLL4D1, and define module clocks for SDHI0 and SDHI1, both of which use PCLKAM as their clock source. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250625141705.151383-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-07-02Merge tag 'renesas-r9a09g087-dt-binding-defs-tag2' into renesas-clk-for-v6.17Geert Uytterhoeven
Renesas RZ/T2H and RZ/N2H SDHI Clock DT Binding Definitions SDHI clock DT binding definitions for the Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs, shared by driver and DT source files.
2025-07-02clk: renesas: rzv2h: Drop redundant base pointer from pll_clkLad Prabhakar
The base address can be accessed via the priv pointer already present in struct pll_clk, making the separate base field redundant. Remove the base member and its assignment. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250624153049.462535-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-07-02clk: renesas: r9a09g057: Add entries for the RSPIsFabrizio Castro
Add clock and reset entries for the Renesas RZ/V2H(P) RSPI IPs. Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250624192304.338979-2-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-07-02dt-bindings: clock: renesas,r9a09g077/87: Add SDHI_CLKHS clock IDLad Prabhakar
Add the SDHI high-speed clock (SDHI_CLKHS) definition for the Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs. SDHI_CLKHS is used as a core clock for the SDHI IP and operates at 800MHz. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250625141705.151383-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-07-02dt-bindings: clock: renesas,r9a09g056/57-cpg: Add XSPI core clockLad Prabhakar
Add XSPI core clock definitions to the clock bindings for the Renesas R9A09G056 and R9A09G057 SoCs. These clocks IDs are used to support XSPI interface. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250627204237.214635-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-26clk: renesas: rzv2h: Add missing include fileFabrizio Castro
File `rzv2h-cpg.h' makes use of data types defined in `linux/types.h', but it does not include the latter, which could lead to build errors. Include `linux/types.h' to fix this problem. Signed-off-by: Fabrizio Castro <fabrizio.castro.jz@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250624192748.340196-1-fabrizio.castro.jz@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-24clk: renesas: rzv2h: Use devm_kmemdup_array()Raag Jadav
Convert to use devm_kmemdup_array() which is more robust. Signed-off-by: Raag Jadav <raag.jadav@intel.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250610072809.1808464-1-raag.jadav@intel.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-19clk: renesas: Add CPG/MSSR support to RZ/N2H SoCLad Prabhakar
Add clock driver support for the Renesas RZ/N2H (R9A09G087) SoC by reusing the existing RZ/T2H (R9A09G077) CPG/MSSR implementation, as both SoCs share the same clock and reset architecture. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250617155757.149597-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-19Merge tag 'renesas-r9a09g087-dt-binding-defs-tag1' into renesas-clk-for-v6.17Geert Uytterhoeven
Renesas RZ/N2H DT Binding Definitions DT bindings and binding definitions for the Renesas RZ/N2H (R9A09G087) SoC, shared by driver and DT source files.
2025-06-19clk: renesas: r9a09g077: Add PCLKL core clockLad Prabhakar
Add the Peripheral Module Clock L (PCLKL) for the RZ/T2H (R9A09G077) SoC. PCLKL is sourced from PLL1 and runs at 62.5MHz. It is used by various low-speed peripherals such as IIC and WDT. Also update LAST_DT_CORE_CLK to reflect the addition of PCLKL, ensuring correct enumeration of core clocks exposed to DT. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250617155757.149597-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-19Merge tag 'renesas-r9a09g077-dt-binding-defs-tag2' into renesas-clk-for-v6.17Geert Uytterhoeven
Renesas RZ/T2H PCLKL Clock DT Binding Definition Peripheral Module Clock L (PCLKL) DT binding definition for the Renesas RZ/T2H (R9A09G077) SoC, shared by driver and DT source files.
2025-06-19dt-bindings: clock: renesas,cpg-mssr: Document RZ/N2H supportLad Prabhakar
Document support for Module Standby and Software Reset found on the Renesas RZ/N2H (R9A09G087) SoC. The Module Standby and Software Reset IP is similar to that found on the RZ/T2H SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250609203656.333138-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-19dt-bindings: soc: renesas: Document RZ/N2H (R9A09G087) SoCPaul Barker
Add RZ/N2H (R9A09G087), its variants, and the rzn2h-evk evaluation board in documentation. Signed-off-by: Paul Barker <paul.barker.ct@bp.renesas.com> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250609203656.333138-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-19dt-bindings: clock: renesas,r9a09g077: Add PCLKL core clock IDLad Prabhakar
Add the Peripheral Module Clock L (PCLKL) core clock ID for the RZ/T2H (R9A09G077) SoC. This clock is used by peripherals such as IIC, WDT, and others. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250617155757.149597-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-19clk: renesas: r9a09g047: Add I3C0 clocks and resetsTommaso Merciai
Add I3C0 clock and reset support to the Renesas RZ/G3E R9A09G047 CPG driver. Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250611093934.4208-3-wsa+renesas@sang-engineering.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-13clk: renesas: rzv2h: Fix missing CLK_SET_RATE_PARENT flag for ddiv clocksLad Prabhakar
Commit bc4d25fdfadf ("clk: renesas: rzv2h: Add support for dynamic switching divider clocks") missed setting the `CLK_SET_RATE_PARENT` flag when registering ddiv clocks. Without this flag, rate changes to the divider clock do not propagate to its parent, potentially resulting in incorrect clock configurations. Fix this by setting `CLK_SET_RATE_PARENT` in the clock init data. Fixes: bc4d25fdfadfa ("clk: renesas: rzv2h: Add support for dynamic switching divider clocks") Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250609140341.235919-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-10clk: renesas: rzg2l: Rename mstp_clock to mod_clockGeert Uytterhoeven
The mstp_clock structure really represents a module clock (cfr. the various rzg2l_mod_clock_*() functions and the to_mod_clock() helper), and is not directly related to the "Module stop state". Rename it to "mod_clock", and replace "mstp_clock" by "mod_clock". to avoid confusion with the mstop registers. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://lore.kernel.org/53b3a730a784650762cdb27fdbde7a45b0c20db8.1749119264.git.geert+renesas@glider.be
2025-06-10clk: renesas: r9a09g056: Add clock and reset entries for USB2.0Lad Prabhakar
Add clock and reset entries for USB2.0. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250528132558.167178-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-10Revert "dt-bindings: clock: renesas,rzg2l-cpg: Update #power-domain-cells = ↵Claudiu Beznea
<1> for RZ/G3S" This reverts commit f33dca9ed6f41c8acf2c17c402738deddb7d7c28. Since the configuration order between the individual MSTOP and CLKON bits cannot be preserved with the power domain abstraction, drop the power domain IDs. Currently, there are no device tree users for #power-domain-cell = <1>. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: "Rob Herring (Arm)" <robh@kernel.org> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://lore.kernel.org/20250527112403.1254122-9-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-10dt-bindings: clock: rzg2l: Drop power domain IDsClaudiu Beznea
Since the configuration order between the individual MSTOP and CLKON bits cannot be preserved with the power domain abstraction, drop the power domain IDs. The corresponding code has also been removed. Currently, there are no device tree users for these IDs. Acked-by: "Rob Herring (Arm)" <robh@kernel.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://lore.kernel.org/20250527112403.1254122-8-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-10clk: renesas: rzg2l: Drop MSTOP based power domain supportClaudiu Beznea
Since the configuration order between the individual MSTOP and CLKON bits cannot be preserved with the power domain abstraction, drop the power domain core code. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://lore.kernel.org/20250527112403.1254122-7-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-10clk: renesas: r9a08g045: Drop power domain instantiationClaudiu Beznea
Since the configuration order between the individual MSTOP and CLKON bits cannot be preserved with the power domain abstraction, drop the power domain instantiations. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://lore.kernel.org/20250527112403.1254122-6-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-10clk: renesas: rzg2l: Add support for MSTOP in clock enable/disable APIClaudiu Beznea
The RZ/{G2L,V2L,G3S} CPG versions support a feature called MSTOP. Each module has one or more MSTOP bits associated with it, and these bits need to be configured along with the module clocks. Setting the MSTOP bits switches the module between normal and standby states. Previously, MSTOP support was abstracted through power domains (struct generic_pm_domain::{power_on, power_off} APIs). With this abstraction, the order of setting the MSTOP and CLKON bits was as follows: Previous Order: A/ Switching to Normal State (e.g., during probe): 1/ Clear module MSTOP bit 2/ Set module CLKON bit B/ Switching to Standby State (e.g., during remove): 1/ Clear CLKON bit 2/ Set MSTOP bit However, in some cases (when the clock is disabled through devres), the order may have been (due to the issue described in link section): 1/ Set MSTOP bit 2/ Clear CLKON bit Recently, the hardware team has suggested that the correct order to set the MSTOP and CLKON bits is: Updated Order: A/ Switching to Normal State (e.g., during probe): 1/ Set CLKON bit 2/ Clear MSTOP bit B/ Switching to Standby State (e.g., during remove): 1/ Set MSTOP bit 2/ Clear CLKON bit To prevent future issues due to incorrect ordering, the MSTOP setup has now been implemented in rzg2l_mod_clock_endisable(), ensuring compliance with the sequence suggested in Figure 41.5: Module Standby Mode Procedure from the RZ/G3S HW manual, Rev1.10. Additionally, since multiple clocks of a single module may be mapped to a single MSTOP bit, MSTOP setup is reference-counted. Furthermore, as all modules start in the normal state after reset, if the module clocks are disabled, the module state is switched to standby. This prevents keeping the module in an invalid state, as recommended by the hardware team. Link: https://lore.kernel.org/all/20250215130849.227812-1-claudiu.beznea.uj@bp.renesas.com/ Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250527112403.1254122-5-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-10clk: renesas: rzg2l: Add macro to loop through module clocksClaudiu Beznea
Add a macro to iterate over the module clocks array. This will be useful in the upcoming commits that move MSTOP support into the clock enable/disable APIs. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://lore.kernel.org/20250527112403.1254122-4-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-10clk: renesas: Add support for R9A09G077 SoCThierry Bultel
RZ/T2H has 2 register blocks at different addresses. The clock tree has configurable dividers and mux selectors. Add these new clock types, new register layout type, and registration code for mux and div in registration callback. Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250515141828.43444-6-thierry.bultel.yh@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-10Merge tag 'renesas-r9a09g077-dt-binding-defs-tag' into renesas-clk-for-v6.17Geert Uytterhoeven
Renesas RZ/T2H DT Binding Definitions DT bindings and binding definitions for the Renesas RZ/T2H (R9A09G077) SoC, shared by driver and DT source files.
2025-06-10clk: renesas: Pass sub struct of cpg_mssr_priv to cpg_clk_registerThierry Bultel
In a subsequent patch, the registration callback will need more parameters from cpg_mssr_priv (like another base address with clock controllers with double register block, and also, notifiers and rmw_lock). Instead of adding more parameters, move the needed parameters to a public sub-struct. Instead moving clks to this structure, which would have implied to add an allocation (and cleanup) for it, keep the way the allocation is done and just have a copy of the pointer in the public structure. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Thierry Bultel <thierry.bultel.yh@bp.renesas.com> Link: https://lore.kernel.org/20250515141828.43444-5-thierry.bultel.yh@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-10clk: renesas: rzg2l: Move pointers after hw memberClaudiu Beznea
Reorder the pointer members in struct mstp_clock so they appear immediately after the hw member. This helps avoid potential padding and eliminates the need for any calculations in the to_mod_clock() macro. As struct clk_hw currently contains only pointers, placing it first also avoids padding. Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Link: https://lore.kernel.org/20250514090415.4098534-3-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-10clk: renesas: rzg2l: Postpone updating priv->clks[]Claudiu Beznea
Since the sibling data is filled after the priv->clks[] array entry is populated, the first clock that is probed and has a sibling will temporarily behave as its own sibling until its actual sibling is populated. To avoid any issues, postpone updating priv->clks[] until after the sibling is populated. Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250514090415.4098534-2-claudiu.beznea.uj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-10clk: renesas: r9a09g056: Add clocks and resets for Mali-G31 GPULad Prabhakar
Add clock and reset support for the Mali-G31 GPU on the Renesas RZ/V2N (R9A09G056) SoC. This includes adding clock sources required for the module clocks. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250513154635.273664-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-10clk: renesas: r9a09g056: Add clock and reset entries for WDT controllersLad Prabhakar
Add module clock and reset definitions for WDT0-3, which are available on the RZ/V2N (R9A09G056) SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250513154635.273664-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-10clk: renesas: r9a09g056: Add clock and reset entries for RIIC controllersLad Prabhakar
Add module clock and reset definitions for RIIC controllers 0-8, which are available on the RZ/V2N (R9A09G056) SoC. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250513154635.273664-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-10clk: renesas: r9a09g056-cpg: Add clock and reset entries for OSTM instancesLad Prabhakar
Introduce a new fixed divider .pllcln_div16 which is sourced from PLLCLN and add PCLK module clocks gtm_0_pclk through gtm_7_pclk for OSTM0-7. Add corresponding reset lines GTM_0_PRESETZ through GTM_7_PRESETZ to control the OSTM instances. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250513154635.273664-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-10clk: renesas: r9a09g056-cpg: Add clock and reset entries for GBETH0/1Lad Prabhakar
Add clock and reset entries for GBETH instances. Include core clocks for PTP, sourced from PLLETH, and add PLLs, dividers, and static mux clocks used as clock sources for the GBETH IP. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250513154635.273664-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-10clk: renesas: r9a09g057: Add clock and reset entries for GBETH0/1Lad Prabhakar
Add clock and reset entries for GBETH instances. Include core clocks for PTP, sourced from PLLETH, and add PLLs, dividers, and static mux clocks used as clock sources for the GBETH IP. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250509160121.331073-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-10clk: renesas: rzv2h: Skip monitor checks for external clocksLad Prabhakar
For module clocks whose parent mux may select an external source, bypass the normal monitor (CLK_MON) register check when the external clock is active. Introduce a new `ext_clk_mux_index` in `struct rzv2h_mod_clk` and `struct mod_clock`, and detect the current mux index in `rzv2h_mod_clock_is_enabled()` to disable monitoring if it matches the external source index. Provide the `DEF_MOD_MUX_EXTERNAL()` macro for declaring external-source module clocks, and populate the `ext_clk_mux_index` field in `rzv2h_cpg_register_mod_clk()`. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250509160121.331073-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2025-06-08Linux 6.16-rc1Linus Torvalds
2025-06-08Merge tag 'turbostat-2025.06.08' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux Pull turbostat updates from Len Brown: - Add initial DMR support, which required smarter RAPL probe - Fix AMD MSR RAPL energy reporting - Add RAPL power limit configuration output - Minor fixes * tag 'turbostat-2025.06.08' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux: tools/power turbostat: version 2025.06.08 tools/power turbostat: Add initial support for BartlettLake tools/power turbostat: Add initial support for DMR tools/power turbostat: Dump RAPL sysfs info tools/power turbostat: Avoid probing the same perf counters tools/power turbostat: Allow probing RAPL with platform_features->rapl_msrs cleared tools/power turbostat: Clean up add perf/msr counter logic tools/power turbostat: Introduce add_msr_counter() tools/power turbostat: Remove add_msr_perf_counter_() tools/power turbostat: Remove add_cstate_perf_counter_() tools/power turbostat: Remove add_rapl_perf_counter_() tools/power turbostat: Quit early for unsupported RAPL counters tools/power turbostat: Always check rapl_joules flag tools/power turbostat: Fix AMD package-energy reporting tools/power turbostat: Fix RAPL_GFX_ALL typo tools/power turbostat: Add Android support for MSR device handling tools/power turbostat.8: pm_domain wording fix tools/power turbostat.8: fix typo: idle_pct should be pct_idle
2025-06-08Merge tag 'timers-cleanups-2025-06-08' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull timer cleanup from Thomas Gleixner: "The delayed from_timer() API cleanup: The renaming to the timer_*() namespace was delayed due massive conflicts against Linux-next. Now that everything is upstream finish the conversion" * tag 'timers-cleanups-2025-06-08' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: treewide, timers: Rename from_timer() to timer_container_of()
2025-06-08Merge tag 'x86-urgent-2025-06-08' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 fixes from Thomas Gleixner: "A small set of x86 fixes: - Cure IO bitmap inconsistencies A failed fork cleans up all resources of the newly created thread via exit_thread(). exit_thread() invokes io_bitmap_exit() which does the IO bitmap cleanups, which unfortunately assume that the cleanup is related to the current task, which is obviously bogus. Make it work correctly - A lockdep fix in the resctrl code removed the clearing of the command buffer in two places, which keeps stale error messages around. Bring them back. - Remove unused trace events" * tag 'x86-urgent-2025-06-08' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: fs/resctrl: Restore the rdt_last_cmd_clear() calls after acquiring rdtgroup_mutex x86/iopl: Cure TIF_IO_BITMAP inconsistencies x86/fpu: Remove unused trace events
2025-06-08Merge tag 'timers-urgent-2025-06-08' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull timer fix from Thomas Gleixner: "Add the missing seq_file forward declaration in the timer namespace header" * tag 'timers-urgent-2025-06-08' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: timens: Add struct seq_file forward declaration
2025-06-08tools/power turbostat: version 2025.06.08Len Brown
Add initial DMR support, which required smarter RAPL probe Fix AMD MSR RAPL energy reporting Add RAPL power limit configuration output Minor fixes Signed-off-by: Len Brown <len.brown@intel.com>
2025-06-08tools/power turbostat: Add initial support for BartlettLakeZhang Rui
Add initial support for BartlettLake. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
2025-06-08tools/power turbostat: Add initial support for DMRZhang Rui
Add initial support for DMR. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
2025-06-08tools/power turbostat: Dump RAPL sysfs infoZhang Rui
for example: intel-rapl:1: psys 28.0s:100W 976.0us:100W intel-rapl:0: package-0 28.0s:57W,max:15W 2.4ms:57W intel-rapl:0/intel-rapl:0:0: core disabled intel-rapl:0/intel-rapl:0:1: uncore disabled intel-rapl-mmio:0: package-0 28.0s:28W,max:15W 2.4ms:57W [lenb: simplified format] Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Len Brown <len.brown@intel.com> squish me Signed-off-by: Len Brown <len.brown@intel.com>
generated by cgit (git 2.34.1) at 2025-09-23 21:28:54 +0000