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2025-07-10arm64: dts: ti: k3-am68-sk-base-board: Add bootph-all property to enable ↵Chintan Vankar
Ethernet boot Ethernet boot requires CPSW nodes to be present starting from R5 SPL stage. Add bootph-all property to required nodes to enable Ethernet boot on SK-AM68. Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com> Signed-off-by: Chintan Vankar <c-vankar@ti.com> Link: https://lore.kernel.org/r/20250709105326.232608-2-c-vankar@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-07-10arm64: dts: ti: Add support for AM62D2-EVMParesh Bhagat
AM62D-EVM evaluation module (EVM) is a low-cost expandable platform board designed for AM62D2 SoC from TI. It supports the following interfaces: * 4 GB LPDDR4 RAM * x2 Gigabit Ethernet expansion connectors * x4 3.5mm TRS Audio Jack Line In * x4 3.5mm TRS Audio Jack Line Out * x2 Audio expansion connectors * x1 Type-A USB 2.0, x1 Type-C dual-role device (DRD) USB 2.0 * x1 UHS-1 capable micro SD card slot * 32 GB eMMC Flash * 512 Mb OSPI NOR flash * x4 UARTs via USB 2.0-B * XDS110 for onboard JTAG debug using USB * Temperature sensors, user push buttons and LEDs Although AM62D2 and AM62A7 differ in peripheral capabilities example multimedia, VPAC, and display subsystems, the core architecture remains same. To reduce duplication, AM62D support reuses the AM62A dtsi and the necessary overrides will be handled in SOC specific dtsi file and a board specific dts. Add basic support for AM62D2-EVM. Schematics Link - https://www.ti.com/lit/zip/sprcal5 Signed-off-by: Paresh Bhagat <p-bhagat@ti.com> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Andrew Davis <afd@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20250708085839.1498505-5-p-bhagat@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-07-10arm64: dts: ti: Add pinctrl entries for AM62D2 family of SoCsParesh Bhagat
Update k3-pinctrl file to include pin definitions for AM62D2 family of SoCs. Signed-off-by: Paresh Bhagat <p-bhagat@ti.com> Reviewed-by: Devarsh Thakkar <devarsht@ti.com> Link: https://lore.kernel.org/r/20250708085839.1498505-4-p-bhagat@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-07-10dt-bindings: arm: ti: Add AM62D2 SoC and BoardsParesh Bhagat
The AM62D2 SoC, part of the K3 architecture, is built for high-performance DSP tasks in automotive audio, pro audio, radar, sonar, and medical imaging. It features up to four Cortex-A53 cores (1.4GHz), two Cortex-R5F cores, and a C7x DSP with 2 TOPS MMA. Key interfaces include multi-channel McASP audio, TSN-capable Gigabit Ethernet, and a range of peripherals (UART, SPI, I2C, CAN, USB, eMMC/SD, OSPI, CSI). It supports LPDDR4/DDR4, secure boot with hardware security, and low-power modes with CAN/GPIO/UART wakeup. This SoC is of part K3 AM62x family, which includes the AM62A and AM62P variants. A key distinction is that the AM62D does not include multimedia components such as the video encoder/decoder, MJPEG encoder, Vision Processing Accelerator (VPAC) for image signal processing, or the display subsystem. Additionally, the AM62D has a different pin configuration compared to the AM62A, which impacts embedded software development. This adds dt bindings for TI's AM62D2 family of devices. More details about the SoCs can be found in the Technical Reference Manual: https://www.ti.com/lit/pdf/sprujd4 Signed-off-by: Paresh Bhagat <p-bhagat@ti.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20250708085839.1498505-3-p-bhagat@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-07-10arm64: dts: ti: Add bootph property to nodes at source for am62aParesh Bhagat
Add bootph property directly into the original definitions of relevant nodes (e.g., power domains, USB controllers, and other peripherals) within their respective DTSI files (ex. main, mcu, and wakeup) for am62a. By defining bootph in the nodes source definitions instead of appending it later in final DTS files, this change ensures that the property is inherently present wherever the nodes are reused across derived device trees. Signed-off-by: Paresh Bhagat <p-bhagat@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20250708085839.1498505-2-p-bhagat@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-07-09arm64: dts: ti: k3-am62p-verdin: Adjust temperature trip pointsJoão Paulo Gonçalves
While the TI AM62P supports a junction temperature (Tj) of up to 125°C for industrial and automotive parts, Toradex Verdin-AM62P hardware lifetime guarantees consider a 105°C Tj. Change the passive trip points to 95°C and the critical trip points to 105°C to be compliant with the hardware specifications. Signed-off-by: João Paulo Gonçalves <joao.goncalves@toradex.com> Link: https://lore.kernel.org/r/20250623-b4-verdin-am62p-cooling-device-v1-2-cc185ba5843d@toradex.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-07-09arm64: dts: ti: k3-am62p-j722s: Enable freq throttling on thermal alertJoão Paulo Gonçalves
Enable throttling down the CPU frequency when an alert temperature threshold is reached before the critical temperature for shutdown. Signed-off-by: João Paulo Gonçalves <joao.goncalves@toradex.com> Link: https://lore.kernel.org/r/20250623-b4-verdin-am62p-cooling-device-v1-1-cc185ba5843d@toradex.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-07-09arm64: dts: ti: k3-j784s4-j742s2-main-common: Add PBIST_14 nodeNeha Malcom Francis
Add DT node for PBIST_14 that is responsible for triggering the PBIST self-tests for the MAIN_R5_2_x cores. Reviewed-by: Udit Kumar <u-kumar1@ti.com> Signed-off-by: Neha Malcom Francis <n-francis@ti.com> Link: https://lore.kernel.org/r/20250605063506.2005637-3-n-francis@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-07-09dt-bindings: soc: ti: bist: Add BIST for K3 devicesNeha Malcom Francis
Document the binding for TI K3 BIST (Built-In Self Test) block. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Neha Malcom Francis <n-francis@ti.com> Link: https://lore.kernel.org/r/20250605063506.2005637-2-n-francis@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-07-09arm64: dts: ti: k3-am62-main: Remove eMMC High Speed DDR supportJudith Mendez
For eMMC, High Speed DDR mode is not supported [0], so remove mmc-ddr-1_8v flag which adds the capability. [0] https://www.ti.com/lit/gpn/am625 Fixes: c37c58fdeb8a ("arm64: dts: ti: k3-am62: Add more peripheral nodes") Cc: stable@vger.kernel.org Signed-off-by: Judith Mendez <jm@ti.com> Link: https://lore.kernel.org/r/20250707191250.3953990-1-jm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-07-09arm64: dts: ti: k3-am62*: Move eMMC pinmux to top level board fileJudith Mendez
This moves pinmux child nodes for sdhci0 node from k3-am62x-sk-common to each top level board file. This is needed since we require internal pullups for AM62x SK and not for AM62 LP SK since it has external pullups on DATA 1-7. Internal pulls are required for AM62 SK as per JESD84 spec recommendation to prevent unconnected lines floating. Fixes: d19a66ae488a ("arm64: dts: ti: k3-am625-sk: Enable on board peripherals") Cc: stable@vger.kernel.org Signed-off-by: Judith Mendez <jm@ti.com> Link: https://lore.kernel.org/r/20250707190830.3951619-1-jm@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-07-09arm64: dts: ti: k3-am62a7-sk: fix pinmux for main_uart1Hong Guan
main_uart1 reserved for TIFS firmware traces is routed to the onboard FT4232 via a FET switch which is connected to pin A21 and B21 of the SoC and not E17 and C17. Fix it. Fixes: cf39ff15cc01a ("arm64: dts: ti: k3-am62a7-sk: Describe main_uart1 and wkup_uart") Cc: stable@vger.kernel.org Signed-off-by: Hong Guan <hguan@ti.com> [bb@ti.com: expanded commit message] Signed-off-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20250707-uart-fixes-v1-1-8164147218b0@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-07-09arm64: dts: ti: Enable overlays for all DTB filesAndrew Davis
Allow overlays to be applied to any DTB without manually enabling it for each file. This adds around ~10% to the total size of the DTB files on average. Signed-off-by: Andrew Davis <afd@ti.com> Acked-by: Bryan Brattlof <bb@ti.com> Link: https://lore.kernel.org/r/20250702145314.71996-1-afd@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-07-09arm64: dts: ti: k3-am62p-verdin: fix PWM_3_DSI GPIO directionParth Pancholi
PWM_3_DSI is used as the HDMI Hot-Plug Detect (HPD) GPIO for the Verdin DSI-to-HDMI adapter. After the commit 33bab9d84e52 ("arm64: dts: ti: k3-am62p: fix pinctrl settings"), the pin was incorrectly set as output without RXACTIVE, breaking HPD detection and display functionality. The issue was previously hidden and worked by chance before the mentioned pinctrl fix. Fix the pinmux configuration to correctly set PWM_3_DSI GPIO as an input. Fixes: 87f95ea316ac ("arm64: dts: ti: Add Toradex Verdin AM62P") Signed-off-by: Parth Pancholi <parth.pancholi@toradex.com> Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com> Link: https://lore.kernel.org/r/20250703084534.1649594-1-parth105105@gmail.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-07-09arm64: dts: ti: k3-pinctrl: Enable Schmitt Trigger by defaultAlexander Sverdlin
Switch Schmitt Trigger functions for PIN_INPUT* macros by default. This is HW PoR configuration, the slew rate requirements without ST enabled are pretty tough for these devices. We've noticed spurious GPIO interrupts even with noise-free edges but not meeting slew rate requirements (3.3E+6 V/s for 3.3v LVCMOS). It's not obvious why one might want to disable the PoR-enabled ST on any pin. Just enable it by default. As it's not possible to provide OR-able macros to disable the ST, shall anyone require it, provide a set of new macros with _NOST suffix. Fixes: fe49f2d776f7 ("arm64: dts: ti: Use local header for pinctrl register values") Cc: stable@vger.kernel.org Signed-off-by: Alexander Sverdlin <alexander.sverdlin@siemens.com> Link: https://lore.kernel.org/r/20250701105437.3539924-1-alexander.sverdlin@siemens.com [vigneshr@ti.com: Add Fixes tag] Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-07-04arm64: dts: ti: k3-am62p-verdin: add SD_1 CD pull-upFrancesco Dolcini
Add internal pull-up to the SD_1 card detect signal, without this the CD signal is floating and spurious detects events can happen. Fixes: 87f95ea316ac ("arm64: dts: ti: Add Toradex Verdin AM62P") Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Link: https://lore.kernel.org/r/20250701081643.71406-1-francesco@dolcini.it Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-06-26arm64: dts: ti: k3-j784s4-j742s2-main-common: Add ACSPCIE1 nodeParth Pancholi
The ACSPCIE1 module on TI's J784S4 SoC is capable of driving the reference clock required by the PCIe Endpoint device. It is an alternative to on- board and external reference clock generators. Add the device-tree node for the same. Signed-off-by: Parth Pancholi <parth.pancholi@toradex.com> Link: https://lore.kernel.org/r/20250513152155.1590689-1-parth105105@gmail.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-06-26arm64: dts: ti: k3-j722s-evm: Fix USB gpio-hog level for Type-CSiddharth Vadapalli
According to the "GPIO Expander Map / Table" section of the J722S EVM Schematic within the Evaluation Module Design Files package [0], the GPIO Pin P05 located on the GPIO Expander 1 (I2C0/0x23) has to be pulled down to select the Type-C interface. Since commit under Fixes claims to enable the Type-C interface, update the property within "p05-hog" from "output-high" to "output-low", thereby switching from the Type-A interface to the Type-C interface. [0]: https://www.ti.com/lit/zip/sprr495 Cc: stable@vger.kernel.org Fixes: 485705df5d5f ("arm64: dts: ti: k3-j722s: Enable PCIe and USB support on J722S-EVM") Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Link: https://lore.kernel.org/r/20250623100657.4082031-1-s-vadapalli@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-06-21arm64: dts: ti: k3-am642-evm-pcie0-ep: Add boot phase tag to "pcie0_ep"Hrushikesh Salunke
AM64X SoC has one instance of PCIe which is PCIe0. To support PCIe boot on AM64X SoC, PCIe0 needs to be in endpoint mode and it needs to be functional at all stages of PCIe boot process. Thus add the "bootph-all" boot phase tag to "pcie0_ep" device tree node. Signed-off-by: Hrushikesh Salunke <h-salunke@ti.com> Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com> Link: https://lore.kernel.org/r/20250610054920.2395509-1-h-salunke@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-06-21arm64: dts: ti: k3-j722s-main: Add audio-refclk0 nodeMichael Walle
Add the node for the AUDIO_EXT_REFCLK0 clock output. Signed-off-by: Michael Walle <mwalle@kernel.org> Link: https://lore.kernel.org/r/20250618090724.1917731-1-mwalle@kernel.org Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-06-21arm64: dts: ti: k3-am62p-j722s: fix pinctrl-single sizeMichael Walle
Pinmux registers ends at 0x000f42ac (including). Thus, the size argument of the pinctrl-single node has to be 0x2b0. Fix it. This will fix the following error: pinctrl-single f4000.pinctrl: mux offset out of range: 0x2ac (0x2ac) Fixes: 29075cc09f43 ("arm64: dts: ti: Introduce AM62P5 family of SoCs") Signed-off-by: Michael Walle <mwalle@kernel.org> Link: https://lore.kernel.org/r/20250618065239.1904953-1-mwalle@kernel.org Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-06-21arm64: dts: ti: k3-am62a7-sk: Describe the SPI NANDMiquel Raynal
Describe the octal SPI NAND available on the low-power starter kit. The pinctrl configuration comes from TI fork. With the current mainline tree, we currently get the following performances: eraseblock write speed is 7507 KiB/s eraseblock read speed is 15802 KiB/s page write speed is 7551 KiB/s page read speed is 15609 KiB/s 2 page write speed is 7551 KiB/s 2 page read speed is 15609 KiB/s erase speed is 284444 KiB/s 2x multi-block erase speed is 512000 KiB/s Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Link: https://lore.kernel.org/r/20250613182356.1272642-1-miquel.raynal@bootlin.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-06-21arm64: dts: ti: k3-j721s2-main: Add McASP nodesJayesh Choudhary
Add McASP 0-4 instances and keep them disabled because several required properties are missing as they are board specific. Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Link: https://lore.kernel.org/r/20250604104656.38752-2-j-choudhary@ti.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-06-21arm64: dts: ti: k3-am62p-verdin: Enable pull-ups on I2C_3_HDMIEmanuele Ghidoli
Enable internal bias pull-ups on the SoC-side I2C_3_HDMI that do not have external pull resistors populated on the SoM. This ensures proper default line levels. Fixes: 87f95ea316ac ("arm64: dts: ti: Add Toradex Verdin AM62P") Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com> Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com> Link: https://lore.kernel.org/r/20250529102601.452859-1-ghidoliemanuele@gmail.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-06-21arm64: dts: ti: k3-am62-verdin: Enable pull-ups on I2C busesEmanuele Ghidoli
Enable internal bias pull-ups on the SoC-side I2C buses that do not have external pull resistors populated on the SoM. This ensures proper default line levels. Cc: stable@vger.kernel.org Fixes: 316b80246b16 ("arm64: dts: ti: add verdin am62") Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com> Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com> Link: https://lore.kernel.org/r/20250528110741.262336-1-ghidoliemanuele@gmail.com Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-06-21arm64: dts: ti: k3-am642-phyboard-electra: Fix PRU-ICSSG Ethernet portsWadim Egorov
For the ICSSG PHYs to operate correctly, a 25 MHz reference clock must be supplied on CLKOUT0. Previously, our bootloader configured this clock, which is why the PRU Ethernet ports appeared to work, but the change never made it into the device tree. Add clock properties to make EXT_REFCLK1.CLKOUT0 output a 25MHz clock. Signed-off-by: Wadim Egorov <w.egorov@phytec.de> Fixes: 87adfd1ab03a ("arm64: dts: ti: am642-phyboard-electra: Add PRU-ICSSG nodes") Link: https://lore.kernel.org/r/20250521053339.1751844-1-w.egorov@phytec.de Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
2025-06-08Linux 6.16-rc1Linus Torvalds
2025-06-08Merge tag 'turbostat-2025.06.08' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux Pull turbostat updates from Len Brown: - Add initial DMR support, which required smarter RAPL probe - Fix AMD MSR RAPL energy reporting - Add RAPL power limit configuration output - Minor fixes * tag 'turbostat-2025.06.08' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux: tools/power turbostat: version 2025.06.08 tools/power turbostat: Add initial support for BartlettLake tools/power turbostat: Add initial support for DMR tools/power turbostat: Dump RAPL sysfs info tools/power turbostat: Avoid probing the same perf counters tools/power turbostat: Allow probing RAPL with platform_features->rapl_msrs cleared tools/power turbostat: Clean up add perf/msr counter logic tools/power turbostat: Introduce add_msr_counter() tools/power turbostat: Remove add_msr_perf_counter_() tools/power turbostat: Remove add_cstate_perf_counter_() tools/power turbostat: Remove add_rapl_perf_counter_() tools/power turbostat: Quit early for unsupported RAPL counters tools/power turbostat: Always check rapl_joules flag tools/power turbostat: Fix AMD package-energy reporting tools/power turbostat: Fix RAPL_GFX_ALL typo tools/power turbostat: Add Android support for MSR device handling tools/power turbostat.8: pm_domain wording fix tools/power turbostat.8: fix typo: idle_pct should be pct_idle
2025-06-08Merge tag 'timers-cleanups-2025-06-08' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull timer cleanup from Thomas Gleixner: "The delayed from_timer() API cleanup: The renaming to the timer_*() namespace was delayed due massive conflicts against Linux-next. Now that everything is upstream finish the conversion" * tag 'timers-cleanups-2025-06-08' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: treewide, timers: Rename from_timer() to timer_container_of()
2025-06-08Merge tag 'x86-urgent-2025-06-08' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 fixes from Thomas Gleixner: "A small set of x86 fixes: - Cure IO bitmap inconsistencies A failed fork cleans up all resources of the newly created thread via exit_thread(). exit_thread() invokes io_bitmap_exit() which does the IO bitmap cleanups, which unfortunately assume that the cleanup is related to the current task, which is obviously bogus. Make it work correctly - A lockdep fix in the resctrl code removed the clearing of the command buffer in two places, which keeps stale error messages around. Bring them back. - Remove unused trace events" * tag 'x86-urgent-2025-06-08' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: fs/resctrl: Restore the rdt_last_cmd_clear() calls after acquiring rdtgroup_mutex x86/iopl: Cure TIF_IO_BITMAP inconsistencies x86/fpu: Remove unused trace events
2025-06-08Merge tag 'timers-urgent-2025-06-08' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull timer fix from Thomas Gleixner: "Add the missing seq_file forward declaration in the timer namespace header" * tag 'timers-urgent-2025-06-08' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: timens: Add struct seq_file forward declaration
2025-06-08tools/power turbostat: version 2025.06.08Len Brown
Add initial DMR support, which required smarter RAPL probe Fix AMD MSR RAPL energy reporting Add RAPL power limit configuration output Minor fixes Signed-off-by: Len Brown <len.brown@intel.com>
2025-06-08tools/power turbostat: Add initial support for BartlettLakeZhang Rui
Add initial support for BartlettLake. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
2025-06-08tools/power turbostat: Add initial support for DMRZhang Rui
Add initial support for DMR. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
2025-06-08tools/power turbostat: Dump RAPL sysfs infoZhang Rui
for example: intel-rapl:1: psys 28.0s:100W 976.0us:100W intel-rapl:0: package-0 28.0s:57W,max:15W 2.4ms:57W intel-rapl:0/intel-rapl:0:0: core disabled intel-rapl:0/intel-rapl:0:1: uncore disabled intel-rapl-mmio:0: package-0 28.0s:28W,max:15W 2.4ms:57W [lenb: simplified format] Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Len Brown <len.brown@intel.com> squish me Signed-off-by: Len Brown <len.brown@intel.com>
2025-06-08tools/power turbostat: Avoid probing the same perf countersZhang Rui
For the RAPL package energy status counter, Intel and AMD share the same perf_subsys and perf_name, but with different MSR addresses. Both rapl_counter_arch_infos[0] and rapl_counter_arch_infos[1] are introduced to describe this counter for different Vendors. As a result, the perf counter is probed twice, and causes a failure in in get_rapl_counters() because expected_read_size and actual_read_size don't match. Fix the problem by skipping the already probed counter. Note, this is not a perfect fix. For example, if different vendors/platforms use the same MSR value for different purpose, the code can be fooled when it probes a rapl_counter_arch_infos[] entry that does not belong to the running Vendor/Platform. In a long run, better to put rapl_counter_arch_infos[] into the platform_features so that this becomes Vendor/Platform specific. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
2025-06-08tools/power turbostat: Allow probing RAPL with platform_features->rapl_msrs ↵Zhang Rui
cleared platform_features->rapl_msrs describes the RAPL MSRs supported. While RAPL Perf counters can be exposed from different kernel backend drivers, e.g. RAPL MSR I/F driver, or RAPL TPMI I/F driver. Thus, turbostat should first blindly probe all the available RAPL Perf counters, and falls back to the RAPL MSR counters if they are listed in platform_features->rapl_msrs. With this, platforms that don't have RAPL MSRs can clear the platform_features->rapl_msrs bits and use RAPL Perf counters only. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
2025-06-08tools/power turbostat: Clean up add perf/msr counter logicZhang Rui
Increase the code readability by moving the no_perf/no_msr flag and the cai->perf_name/cai->msr sanity checks into the counter probe functions. No functional change. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
2025-06-08tools/power turbostat: Introduce add_msr_counter()Zhang Rui
probe_rapl_msr() is reused for probing RAPL MSR counters, cstate MSR counters and MPERF/APERF/SMI MSR counters, thus its name is misleading. Similar to add_perf_counter(), introduce add_msr_counter() to probe a counter via MSR. Introduce wrapper function add_rapl_msr_counter() at the same time to add extra check for Zero return value for specified RAPL counters. No functional change intended. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
2025-06-08tools/power turbostat: Remove add_msr_perf_counter_()Zhang Rui
As the only caller of add_msr_perf_counter_(), add_msr_perf_counter() just gives extra debug output on top. There is no need to keep both functions. Remove add_msr_perf_counter_() and move all the logic to add_msr_perf_counter(). No functional change. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
2025-06-08tools/power turbostat: Remove add_cstate_perf_counter_()Zhang Rui
As the only caller of add_cstate_perf_counter_(), add_cstate_perf_counter() just gives extra debug output on top. There is no need to keep both functions. Remove add_cstate_perf_counter_() and move all the logic to add_cstate_perf_counter(). No functional change. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
2025-06-08tools/power turbostat: Remove add_rapl_perf_counter_()Zhang Rui
As the only caller of add_rapl_perf_counter_(), add_rapl_perf_counter() just gives extra debug output on top. There is no need to keep both functions. Remove add_rapl_perf_counter_() and move all the logic to add_rapl_perf_counter(). No functional change. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
2025-06-08tools/power turbostat: Quit early for unsupported RAPL countersZhang Rui
Quit early for unsupported RAPL counters. No functional change. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
2025-06-08tools/power turbostat: Always check rapl_joules flagZhang Rui
rapl_joules bit should always be checked even if platform_features->rapl_msrs is not set or no_msr flag is used. Signed-off-by: Zhang Rui <rui.zhang@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
2025-06-08tools/power turbostat: Fix AMD package-energy reportingGautham R. Shenoy
commit 05a2f07db888 ("tools/power turbostat: read RAPL counters via perf") that adds support to read RAPL counters via perf defines the notion of a RAPL domain_id which is set to physical_core_id on platforms which support per_core_rapl counters (Eg: AMD processors Family 17h onwards) and is set to the physical_package_id on all the other platforms. However, the physical_core_id is only unique within a package and on platforms with multiple packages more than one core can have the same physical_core_id and thus the same domain_id. (For eg, the first cores of each package have the physical_core_id = 0). This results in all these cores with the same physical_core_id using the same entry in the rapl_counter_info_perdomain[]. Since rapl_perf_init() skips the perf-initialization for cores whose domain_ids have already been visited, cores that have the same physical_core_id always read the perf file corresponding to the physical_core_id of the first package and thus the package-energy is incorrectly reported to be the same value for different packages. Note: This issue only arises when RAPL counters are read via perf and not when they are read via MSRs since in the latter case the MSRs are read separately on each core. Fix this issue by associating each CPU with rapl_core_id which is unique across all the packages in the system. Fixes: 05a2f07db888 ("tools/power turbostat: read RAPL counters via perf") Signed-off-by: Gautham R. Shenoy <gautham.shenoy@amd.com> Signed-off-by: Len Brown <len.brown@intel.com>
2025-06-08tools/power turbostat: Fix RAPL_GFX_ALL typoKaushlendra Kumar
Fix typo in the currently unused RAPL_GFX_ALL macro definition. Signed-off-by: Kaushlendra Kumar <kaushlendra.kumar@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
2025-06-08tools/power turbostat: Add Android support for MSR device handlingKaushlendra Kumar
It uses /dev/msrN device paths on Android instead of /dev/cpu/N/msr, updates error messages and permission checks to reflect the Android device path, and wraps platform-specific code with #if defined(ANDROID) to ensure correct behavior on both Android and non-Android systems. These changes improve compatibility and usability of turbostat on Android devices. Signed-off-by: Kaushlendra Kumar <kaushlendra.kumar@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
2025-06-08tools/power turbostat.8: pm_domain wording fixLen Brown
turbostat.8: clarify that uncore "domains" are Power Management domains, aka pm_domains. Signed-off-by: Len Brown <len.brown@intel.com>
2025-06-08tools/power turbostat.8: fix typo: idle_pct should be pct_idleLen Brown
idle_pct should be pct_idle Signed-off-by: Len Brown <len.brown@intel.com>
2025-06-08Merge tag 'perf-urgent-2025-06-08' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 perf fix from Thomas Gleixner: "A single fix for the x86 performance counters on Intel CPUs: The MSR offset calculations for fixed performance counters are stored at the wrong index in the configuration array causing the general purpose counter MSR offset to be overwritten, so both the general purpose and the fixed counters offsets are incorrect. Correct the array index calculation to fix that" * tag 'perf-urgent-2025-06-08' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: perf/x86/intel: Fix incorrect MSR index calculations in intel_pmu_config_acr()
generated by cgit (git 2.34.1) at 2025-09-11 07:38:00 +0000