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2021-02-24drm/amdgpu: Remove unnecessary conversion to boolJiapeng Chong
Fix the following coccicheck warnings: ./drivers/gpu/drm/amd/amdgpu/athub_v2_1.c:79:40-45: WARNING: conversion to bool not needed here. ./drivers/gpu/drm/amd/amdgpu/athub_v2_1.c:81:40-45: WARNING: conversion to bool not needed here. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-24drm/amdgpu/display: initialize the variable 'i'Souptick Joarder
>> drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:9804:38: >> warning: variable 'i' is uninitialized when used here >> [-Wuninitialized] timing = &edid->detailed_timings[i]; ^ drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.c:9714:7: note: initialize the variable 'i' to silence this warning int i; ^ = 0 1 warning generated. Initialize the variable 'i'. Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Souptick Joarder <jrdr.linux@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-24drm/amdgpu/vcn3.0: add wptr/rptr reset/update for share memorySonny Jiang
Because of dpg, the rptr/wptr need to be saved on fw shared memory, and restore them back in RBC_RB_RPTR/WPTR in kernel at power up. Signed-off-by: Sonny Jiang <sonny.jiang@amd.com> Reviewed-by: Leo Liu <leo.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-24drm/amd/display: Enable ASSR in DMStylon Wang
This patch enables ASSR if display declares such support in DPCD. Signed-off-by: Stylon Wang <stylon.wang@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-24drm/amdgpu: disable mec2 fw bin loadingJohn Clements
disable mec2 fw bin loading and reference on unsupported ASIC Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: John Clements <john.clements@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-24drm/amdgpu: fix wrong executable setting for dimgrey_cavefish_reg_init.cTao Zhou
Remove executable configuration for the file. Reported-by: Ming Wang <wangming01@loongson.cn> Signed-off-by: Tao Zhou <tao.zhou1@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-24drm/amdgpu: fix shutdown and poweroff process failed with s0ixPrike Liang
In the shutdown and poweroff opt on the s0i3 system we still need un-gate the gfx clock gating and power gating before destory amdgpu device. Fixes: 628c36d7b238e2 ("drm/amdgpu: update amdgpu device suspend/resume sequence for s0i3 support") Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1499 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Prike Liang <Prike.Liang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-24drm/amdgpu/sdma5.2: Remove unnecessary conversion to boolJiapeng Chong
Fix the following coccicheck warnings: ./drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c:1621:40-45: WARNING: conversion to bool not needed here. ./drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c:1619:40-45: WARNING: conversion to bool not needed here. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-24drm/amd/display/dc/core/dc_link_ddc: Remove unnecessary conversion to boolJiapeng Chong
Fix the following coccicheck warnings: ./drivers/gpu/drm/amd/display/dc/core/dc_link_ddc.c:544:34-39: WARNING: conversion to bool not needed here. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-24drm/amdgpu/swsmu/navi1x: Remove unnecessary conversion to boolJiapeng Chong
Fix the following coccicheck warnings: ./drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c:900:47-52: WARNING: conversion to bool not needed here. Reviewed-by: Evan Quan <evan.quan@amd.com> Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-24drm/amd/pm/swsmu: Avoid using structure_size uninitialized in ↵Nathan Chancellor
smu_cmn_init_soft_gpu_metrics Clang warns: drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu_cmn.c:764:2: warning: variable 'structure_size' is used uninitialized whenever switch default is taken [-Wsometimes-uninitialized] default: ^~~~~~~ drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu_cmn.c:770:23: note: uninitialized use occurs here memset(header, 0xFF, structure_size); ^~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu_cmn.c:753:25: note: initialize the variable 'structure_size' to silence this warning uint16_t structure_size; ^ = 0 1 warning generated. Return in the default case, as the size of the header will not be known. Fixes: de4b7cd8cb87 ("drm/amd/pm/swsmu: unify the init soft gpu metrics function") Link: https://github.com/ClangBuiltLinux/linux/issues/1304 Reviewed-by: Kevin Wang <kevin1.wang@amd.com> Signed-off-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-24drm/amd/display: Allow spatial dither to 10 bpc on all DCEMario Kleiner
Spatial dithering to 10 bpc depth was disabled for all DCE's. Testing on DCE-8.3 and DCE-11.2 did not show any obvious ill effects, but a measureable precision improvement (via colorimeter) when displaying a fp16 framebuffer to a 10 bpc DP or HDMI connected HDR-10 monitor. v2: enable it for all DCEs (Alex) Signed-off-by: Mario Kleiner <mario.kleiner.de@gmail.com> Cc: Alex Deucher <alexdeucher@gmail.com> Reviewed-by: Mario Kleiner <mario.kleiner.de@gmail.com> (v2) Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-24drm/amd/display: Fix system hang after multiple hotplugs (v3)Qingqing Zhuo
[Why] mutex_lock() was introduced in dm_disable_vblank(), which could be called in an IRQ context. Waiting in IRQ would cause issues like kernel lockup, etc. [How] Handle code that requires mutex lock on a different thread. v2: squash in compilation fix without CONFIG_DRM_AMD_DC_DCN (Alex) v3: squash in warning fix (Wei) Signed-off-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
2021-02-22drm/amd/display: 3.2.124Aric Cyr
Signed-off-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-22drm/amd/display: [FW Promotion] Release 0.0.53Anthony Koo
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-22drm/amd/display: reduce scope for local varAric Cyr
[Why] No reason to have uninitialized var at top of function [How] Move it to minimum scope where it's actuallty used Signed-off-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-22drm/amd/display: Don't optimize bandwidth before disabling planesAric Cyr
[Why] There is a window of time where we optimize bandwidth due to no streams enabled will enable PSTATE changing but HUBPs are not disabled yet. This results in underflow counter increasing in some hotplug scenarios. [How] Set the optimize-bandwidth flag for later processing once all the HUBPs are properly disabled. Signed-off-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-22drm/amd/display: Synchronize displays with different timingsVladimir Stempen
[why] Vendor based fan noise improvement [how] Report timing synchronizable when DP streams time frame difference is less than 0.05 percent. Adjust DP DTOs and sync displays using MASTER_UPDATE_LOCK_DB_X_Y Signed-off-by: Vladimir Stempen <vladimir.stempen@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-22drm/amd/display: move trace buffer to uncached memory.Yongqiang Sun
[Why & How] Move dmub trace buffer to uncached memory. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-22drm/amd/display: Check for DSC support instead of ASIC revisionEryk Brol
[why] This check for ASIC revision is no longer useful and causes lightup issues after a topology change in MST DSC scenario. In this case, DSC configs should be recalculated for the new topology. This check prevented that from happening on certain ASICs that do, in fact, support DSC. [how] Change the ASIC revision to instead check if DSC is supported. Signed-off-by: Eryk Brol <eryk.brol@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-22drm/amd/display: enable audio on DP seamless bootAnthony Wang
[Why] Some external displays with DP can use seamless boot, but their audio endpoints are only enabled after hotplug. On boot, these displays inherit UEFI timings without properly initializing audio. [How] Enable display audio when seamless booting with an external monitor over DP. Signed-off-by: Anthony Wang <anthony1.wang@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-22drm/amd/display: disable seamless boot for DP MSTAnthony Wang
[Why] Seamless boot over DP MST is not POR, but is not explicitly disabled. [How] Add check for DP MST and return false in dc_validate_seamless_boot_timing. Signed-off-by: Anthony Wang <anthony1.wang@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-22drm/amd/display: Refactor debugfs entries for all connectorsStylon Wang
[Why] Debugfs entries being moved from DP/eDP only to be available on all connectors are cluttering the code. [How] Refactor the registration of these debugfs entries. Signed-off-by: Stylon Wang <stylon.wang@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-22drm/amd/display: Remove Assert from dcn10_get_dig_frontendEric Bernstein
[Why] In some cases, this function is called when DIG BE is not connected to DIG FE, in which case a value of zero isn't invalid and assert should not be hit. [How] Remove assert and handle ENGINE_ID_UNKNOWN result in calling function. Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-22drm/amd/display: Add vupdate_no_lock interrupts for DCN2.1Rodrigo Siqueira
When run igt@kms_vrr in a device that uses DCN2.1 architecture, we noticed multiple failures. Furthermore, when we tested a VRR demo, we noticed a system hang where the mouse pointer still works, but the entire system freezes; in this case, we don't see any dmesg warning or failure messages kernel. This happens due to a lack of vupdate_no_lock interrupt, making the userspace wait eternally to get the event back. For fixing this issue, we need to add the vupdate_no_lock interrupt in the interrupt list. Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Bindu Ramamurthy <bindu.r@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-22drm/amdgpu: remove unused variable from struct amdgpu_boNirmoy Das
Fixes: 62914a99dee5a ("drm/amdgpu: Use mmu_interval_insert instead of hmm_mirror") Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-22drm/amdkfd: Cleanup kfd_process if init_cwsr_apu failsFelix Kuehling
If init_cwsr_apu fails, we currently leave the kfd_process structure in place anyway. The next kfd_open will then succeed, using the existing kfd_process structure. Fix that by cleaning up the kfd_process after a failure in init_cwsr_apu. Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Philip Yang <philip.yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-22drm/amdkfd: Use mmu_notifier_getFelix Kuehling
We use mmu_notifier_put to free the MMU notifier. That needs to be paired with mmu_notifier_get to work correctly. Othewrise the next patch would cause a kernel oops. Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Philip Yang <philip.yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-22Revert "drm/amd/display: reuse current context instead of recreating one"Anson Jacob
This reverts commit 8866a67ab86cc0812e65c04f1ef02bcc41e24d68. Reason for revert: This breaks hotplug of HDMI on some systems, resulting in a blank screen. Caused general hangs on boot/hotplugs. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1487 Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1492 Bug: https://bugzilla.kernel.org/show_bug.cgi?id=211649 Signed-off-by: Anson Jacob <Anson.Jacob@amd.com> Reviewed-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-18drm/amd/display: Simplify bool conversionYang Li
Fix the following coccicheck warning: ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c:8142:16-21: WARNING: conversion to bool not needed here Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-18drm/amd/pm: do not issue message while write "r" into pp_od_clk_voltageHuang Rui
We should commit the value after restore them back to default as well. $ echo "r" > pp_od_clk_voltage $ echo "c" > pp_od_clk_voltage Signed-off-by: Huang Rui <ray.huang@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-18drm/amd/display: Old sequence for HUBP blankAurabindo Pillai
New proposed sequence for HUBP blanking causes regressions where the hardware would fail to enter blank which triggers an assert in the new sequence. This change brings back the old sequence. Fixes: 985faf2c4ecb60 ("drm/amd/display: New sequence for HUBP blank") Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Bhawanpreet Lakha <bhawanpreet.lakha@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-18drm/amdgpu: mark local function as staticNirmoy Das
Mark amdgpu_ras_debugfs_create_ctrl_node() as static. Fixes: eb14235668777b ("drm/amdgpu: do not keep debugfs dentry") Reported-by: kernel test robot <lkp@intel.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-18drm/amd/display: 3.2.123Aric Cyr
DC version 3.2.123 brings improvements in multiple areas. In summary, we highlight: - Firmware release 0.0.52 - Bug fixes on MPC OGAM sequence, display experience, etc. - Improvements on timing, transmitter control, etc. Signed-off-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-18drm/amd/display: [FW Promotion] Release 0.0.52Anthony Koo
[How] Add new aux cmd fields for acquire and release Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-18drm/amd/display: Implement transmitter control v1.7Eric Bernstein
[Why] Moving definition of transmitter control from atomfirmware to internal header. [How] Update the command table code to call 1.7 and make it the default fallback path. Signed-off-by: Eric Bernstein <eric.bernstein@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-18drm/amd/display: AVMUTE simplificationChris Park
[Why] Simplify AVMUTE logic in coding [How] Avoid multiple calls on TMDS AVMUTE as updated logic now demands it. Signed-off-by: Chris Park <Chris.Park@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-18drm/amd/display: Copy over soc values before bounding box creationSung Lee
[Why] With certain fclock overclocks, state 1 may be chosen as the closest clock level. This may result in this state being empty if not populated beforehand, resulting in black screens and screen corruption. [How] Copy over all soc states to clock_limits before bounding box creation to avoid any cases with empty states. Signed-off-by: Sung Lee <sung.lee@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com> Acked-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-18drm/amd/display: Add Freesync HDMI support to DMStylon Wang
[Why] Add necessary support for Freesync HDMI in Linux DM [How] - Support Freesync HDMI by calling DC interace - Report Freesync capability to vrr_range debugfs from DRM - Depends on coming DMCU/DMUB firmware to enable feature Signed-off-by: Stylon Wang <stylon.wang@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-18drm/amd/display: Populate dcn2.1 bounding box before state duplicationSung Lee
[Why] If system is overclocked, only 1 bounding box state will be sent by SMU. This results in an empty state being copied for DML calculations causing black screens and corruption. [How] Fully populate bounding box before duplicating last state. Signed-off-by: Sung Lee <sung.lee@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-18drm/amd/display: Fix MPC OGAM power on/off sequenceNicholas Kazlauskas
[Why] Color corruption can occur on bootup into a login manager that applies a non-linear gamma LUT because the LUT may not actually be powered on before writing. It's cleared on the next full pipe reprogramming as we switch to LUTB from LUTA and the pipe accessing the LUT has taken it out of light sleep mode. [How] The MPCC_OGAM_MEM_PWR_FORCE register does not force the current power mode when set to 0. It only forces when set light sleep, deep sleep or shutdown. The register to actually force power on and ignore sleep modes is MPCC_OGAM_MEM_PWR_DIS - a value of 0 will enable power requests and a value of 1 will disable them. When PWR_FORCE!=0 is combined with PWR_DIS=0 then MPCC OGAM memory is forced into the state specified by the force bits. If PWR_FORCE is 0 then it respects the mode specified by MPCC_OGAM_MEM_LOW_PWR_MODE if the RAM LUT is not in use. We set that bit to shutdown on low power, but otherwise it inherits from bootup defaults. So for the fix: 1. Update the sequence to "force" power on when needed We can use MPCC_OGAM_MEM_PWR_DIS for this to turn on the memory even when the block is in bypass and pending to be enabled for the next frame. We need this for both low power enabled or disabled. If we don't set this then we can run into issues when we first program the LUT from bootup. 2. Don't apply FORCE_SEL Once we enable power requests with DIS=0 we run into the issue of the RAM being forced into light sleep and being unusable for display output. Leave this 0 like we used to for DCN20. 3. Rely on MPCC OGAM init to determine light sleep/deep sleep MPC low power debug mode isn't enabled on any ASIC currently but we'll respect the setting determined during init if it is. Lightly tested as working with IGT tests and desktop color adjustment. 4. Change the MPC resource default for DCN30 It was interleaving the dcn20 and dcn30 versions before depending on the sequence. 5. REG_WAIT for it to be on whenever we're powering up the memory Otherwise we can write register values too early and we'll get corruption. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-18drm/amd/display: Add dc_dmub_srv helpers for in/out DMCUB commandsNicholas Kazlauskas
[Why] We added these in DMCUB for runtime feature detection but we didn't have helpers to call these with DC error handling/logging. [How] Add helpers. Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-18drm/amd/display: changing sr exit latencyMartin Leung
[Why] Hardware team remeasured, need to update timings to increase latency slightly and avoid intermittent underflows. [How] sr exit latency update. Signed-off-by: Martin Leung <martin.leung@amd.com> Reviewed-by: Alvin Lee <Alvin.Lee2@amd.com> Acked-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-18Revert "drm/amd/display: Unblank hubp based on plane visibility"Wesley Chalmers
This reverts commit fd1c85d3ac2ccfec33b007399e6677b41899a888 [Why] We are not implementing the planned new HW sequence to disable HUBP. [How] Revert most related changes to minimize possibility of regression. Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by: Martin Leung <Martin.Leung@amd.com> Acked-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-18Revert "drm/amd/display: New path for enabling DPG"Wesley Chalmers
This reverts commit f8e792dc5c45d306a542b9ee991ae80e1c78e4c5 [Why] We are not implementing the planned new HW sequence for HUBP disable. [How] Revert most related changes to minimize regressions. Signed-off-by: Wesley Chalmers <Wesley.Chalmers@amd.com> Reviewed-by: Martin Leung <Martin.Leung@amd.com> Acked-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-18drm/amd/display: remove global optimize seamless boot stream countLewis Huang
[Why] In following sequence driver will add counter twice on same edp stream. 1. Boot into OS. 2. Set timing with edp only. 3. Set timing with edp and external monitor. 4. Set visibility on for edp. Step 2 and 3 will add seamless boot counter twice and subtract it once in step 4. [How] Remove global counter and calculate it is used. Signed-off-by: Lewis Huang <Lewis.Huang@amd.com> Reviewed-by: Martin Leung <Martin.Leung@amd.com> Acked-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-18drm/amd/display: Change ABM sample ratePo-Ting Chen
[Why] To get the pixel statistics on every frame, change ABM sample rate from 2 to 1. [How] Change LS, HS and BL sample rate to 1. Signed-off-by: Po-Ting Chen <robin.chen@amd.com> Reviewed-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Qingqing Zhuo <Qingqing.Zhuo@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-18drm/radeon: do not use drm middle layer for debugfs (v2)Nirmoy Das
Use debugfs API directly instead of drm middle layer. v2: squash in build fix (Alex) Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-18drm/radeon: add rdev in ring structNirmoy Das
Retrieving radeon device struct from ring struct will be used in next patch where debugfs's show function can only pass one private data pointer. Signed-off-by: Nirmoy Das <nirmoy.das@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2021-02-18drm/radeon: Remove unused function pointer typedef radeon_packet3_check_tChen Lin
Remove the 'radeon_packet3_check_t' typedef as it is not used. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Chen Lin <chen.lin5@zte.com.cn> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit (git 2.34.1) at 2025-09-12 06:31:28 +0000