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Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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As Documentation/arm64/booting.txt says, the cpu-release-addr
location should be reserved.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
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At first, 256 byte of the head of DRAM space was reserved for some
reasons. However, as the progress of development, it turned out
unnecessary, and it was never used in the end. Move the CPU release
address to leave no space.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
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This node consists of various system-level configuration registers.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
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git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt64
Renesas ARM64 Based SoC DT Updates for v4.8
* Fix W=1 dtc warnings and other cleanups
* Enable watchdog timer
* Enable DMA for I2C
* Increase the size of GIC-400 mapped registers: be nicer to hypervisors
* Support RTS/CTS hardware flow control
* tag 'renesas-arm64-dt-for-v4.8' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
arm64: dts: r8a7795: Drop 0x from unit address of gic
arm64: dts: salvator-x: Fix W=1 dtc warnings
arm64: dts: r8a7795: Fix W=1 dtc warnings
arm64: dts: r8a7795: Use SYSC "always-on" PM Domain for RWDT node
arm64: dts: salvator-x: Enable watchdog timer
arm64: dts: r8a7795: Add RWDT node
arm64: dts: r8a7795: enable DMA for I2C
arm64: dts: r8a7795: Increase the size of GIC-400 mapped registers
arm64: dts: salvator-x: SCIF1 supports RTS/CTS hardware flow control
Signed-off-by: Olof Johansson <olof@lixom.net>
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Update reserved-memory in accordance with memory the detailed memory map
for 8916, so that we will be able to reference the firmware memory
regions.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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This adds the devicetree node for the SCM firmware.
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
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Add the PMU so we can get proper perf event support on this SoC.
Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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Add device bindings for CPUs to suspend using PSCI as the enable-method.
Cc: <devicetree@vger.kernel.org>
Signed-off-by: Lina Iyer <lina.iyer@linaro.org>
Tested-by: Andy Gross <andy.gross@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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This patch enables bam dma node, dma is used for both tx and rx on spi
and on high speed serial.
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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Add the necessary properties to enable the SD-card on db410c boards.
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Tested-by: Kevin Hilman <khilman@baylibre.com>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
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Add "dis_rxdet_inp3_quirk" boolean property to USB3 node. This property
is used to disable rx detection in P3 PHY mode.
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Add "dis_rxdet_inp3_quirk" boolean property to USB3 node. This property
is used to disable rx detection in P3 PHY mode.
Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Commit 86c679a52294 ("clk: tegra: pll: Fix _pll_ramp_calc_pll logic and
_calc_dynamic_ramp_rate") changed the PLL divider computation logic to
consistently use P-divider values from tables as real dividers rather
than the hardware values. Unfortunately for some reason many of the
Tegra210 clocks didn't have their tables updated (most likely an over-
sight by me when applying the patches). This commit fixes them all up.
Cc: Jon Hunter <jonathanh@nvidia.com>
Cc: Rhyland Klein <rklein@nvidia.com>
Acked-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
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MPIDR_EL1[63:32] value is equal to 0 for the CPUs of the LS1043A and
LS2080A SoCs. The ARM CPU binding allows #address-cells to be set to 1,
since MPIDR_EL1[63:32] bits are not used for CPUs identification. Update
the #address-cells and reg properties accordingly.
Signed-off-by: Alison Wang <alison.wang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
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This merge brings over the DT ethernet nodes from 32-bit (used so that
we can get the MAC address for it) so that we can expose it on arm64
as well.
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While this devicetree also works for booting in 32-bit mode, it's
placed in arm64 since it's a 64-bit CPU (as suggested by Arnd).
Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Stephen Warren <swarren@wwwdotorg.org> (v1)
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
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Signed-off-by: Eric Anholt <eric@anholt.net>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Rob Herring <robh@kernel.org>
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This adds thermal zone and tsadc nodes to rk3399 dtsi, rk3399 thermal
data is including the cpu and gpu sensor zone node.
The thermal zone node is the node containing all the required info
for describing a thermal zone, including its cooling device bindings.
The thermal zone node must contain, apart from its own properties, one
sub-node containing trip nodes and one sub-node containing all the zone
cooling maps.
The following is the parameter is introduced:
* polling-delay:
The maximum number of milliseconds to wait between polls
* polling-delay-passive:
The maximum number of milliseconds to wait between polls when performing
passive cooling.
* trips:
A sub-node which is a container of only trip point nodes required to
describe the thermal zone.
* cooling-maps:
A sub-node which is a container of only cooling device map nodes, used to
describe the relation between trips and cooling devices.
* cooling-device:
A phandle of a cooling device with its specifier, referring to which
cooling device is used in this cooling specifier binding. In the cooling
specifier, the first cell is the minimum cooling state and the second cell
is the maximum cooling state used in this map.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Initial support for R-Car M3-W (r8a7796), including basic core clocks,
and SCIF2 (console) and INTC-AP (GIC) module clocks.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
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Extract the code to support parts common to all members of the R-Car
Gen3 SoC family into a separate file, to ease sharing among SoC-specific
drivers.
Note that while the cpg_pll_configs[] arrays and the selection of the
config based on the MODE bits are identical on R-Car H3 and R-Car M3-W,
they are not common, and may be different on other R-Car Gen3 SoCs.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
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Add all R-Car M3-W Clock Pulse Generator Core Clock Outputs, as listed
in Table 8.2b ("List of Clocks [R-Car M3-W]") of the R-Car Gen3
datasheet (rev. 0.51 + Errata for Rev051 Mar 31 2016).
Note that internal CPG clocks (S0, S1, S2, S3, SDSRC, and SSPSRC) are
not included, as they are used as internal clock sources only, and never
referenced from DT.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
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Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Rob Herring <robh@kernel.org>
Tested-by: Simon Horman <horms+renesas@verge.net.au>
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Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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Add dtsi file to support lg1313 SoC which based on Cortex-A53.
Also add dts file to support lg1312 reference board which based
on lg1313 SoC.
Signed-off-by: Chanho Min <chanho.min@lge.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
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This patch adds the device nodes for the DISP function blocks
comprising the display subsystem.
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: Cawa Cheng <cawa.cheng@mediatek.com>
Signed-off-by: Jie Qiu <jie.qiu@mediatek.com>
Signed-off-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
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Update DTSI file to add the reset controller node.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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Add node for ethernet interface and pinctrl pins.
Enable on odroid-C2 and P20x boards.
Acked-by: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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Add DT nodes for additional UARTs (UART B & C in EE domain) and add pins
for all EE domain UARTs.
Acked-by: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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Acked-by: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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Update DTS and DTSI files to enable the pin controller. We also now
support the blinking blue LED on the Odroid-C2.
Signed-off-by: Carlo Caione <carlo@endlessm.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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Add the two new compatibles for the Amlogic Meson GXBB pin controllers.
Signed-off-by: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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Add two new buses in the DTS: hiu and periphs buses.
In the Amlogic S905/GXBB SoC several devices (clock / eth / pin
controllers, etc...) are mapped under these two buses. Add them in the
DT before starting to add new devices.
Signed-off-by: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
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Add DT bindings for the Meson SoC Reset Controller documentation and the
associated include file.
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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This patch adds the platform driver for the Amlogic Meson SoC Reset
Controller.
The Meson8b and GXBB SoCs are supported.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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Prior to commit 6c96f05c8bb8 ("reset: Make [of_]reset_control_get[_foo]
functions wrappers"), the "optional" functions returned -ENOTSUPP when
CONFIG_RESET_CONTROLLER was not set.
Revert back to the old behavior by changing the new
__devm_reset_control_get() and __of_reset_control_get() functions to
return ERR_PTR(-ENOTSUPP) when compiled without CONFIG_RESET_CONTROLLER.
Otherwise they will return -EINVAL causing users to think that an error
occurred when CONFIG_RESET_CONTROLLER is not set.
Fixes: 6c96f05c8bb8 ("reset: Make [of_]reset_control_get[_foo] functions wrappers")
Signed-off-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
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Add support to the Northstar 2 Device tree file for the ARM CCI-400 PMU.
Signed-off-by: Jon Mason <jonmason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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Add all of the UARTs present on NS2 and enable them in the SVK device
tree file. Also, do some magic to make sure that uart3 is discovered as
ttyS0 (as that is the console UART).
Signed-off-by: Jon Mason <jonmason@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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This enables the GPIO support for Broadcom NS2 SoC
Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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This enables the pinctrl support for Broadcom NS2 SoC
Signed-off-by: Yendapally Reddy Dhananjaya Reddy <yendapally.reddy@broadcom.com>
Reviewed-by: Ray Jui <ray.jui@broadcom.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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We have one dual-port SATA3 AHCI controller present in
NS2 SoC.
This patch enables SATA3 AHCI controller and SATA3 PHY
for NS2 SoC in NS2 DT.
Signed-off-by: Anup Patel <anup.patel@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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The Broadcom iProc SoCs have AHCI compliant SATA controller. This
patch adds common compatible string for AHCI SATA controller on
iProc SoCs.
Signed-off-by: Anup Patel <anup.patel@broadcom.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
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The hub and the ethernet in its port 1 are hardwired on the board.
Compared to the adapters that can be plugged into the USB ports, this
one has no serial EEPROM to store its MAC. Nevertheless, the Raspberry Pi
has the MAC address for this adapter in its ROM, accessible from its
firmware.
U-Boot can read out the address and set the local-mac-address property of the
node with "ethernet" alias. Let's add the node so that U-Boot can do its
business.
Model B rev2 and Model B+ entries were verified by me, the hierarchy and
pid/vid pair for the Version 2 was provided by Peter Chen. Original
Model B is a blind shot, though very likely correct.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
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Add the core io-domain nodes to grf and pmugrf which individual
boards than just have to enable and add the necessary supplies to.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Add the supply-links according to the R88 schematics.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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Add the core io-domain nodes to grf and pmugrf which individual
boards than just have to enable and add the necessary supplies to.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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