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2014-11-23Merge tag 'imx-soc-3.19' into imx/dtShawn Guo
The i.MX SoC update for 3.19: - Update i.MX6 suspend code to check DDR instead of CPU type, as the difference we need to handle is between LPDDR2 and DDR3, not SoCs. - Set anatop properly for LPDDR2 in DSM mode - Add support for new SoC LS1021A which integrates dual Cortex-A7 - Add ENET initialization for i.MX6SX platform - Add cpufreq support for i.MX53 platform - Add a SNVS based poweroff driver for i.MX6 platforms - Use ARM Global Timer as clocksource on VF610 Note: the change set is built on top of tag imx-fixes-3.18-2 to resolve a conflict on file arch/arm/mach-imx/clk-vf610.c.
2014-11-23power: reset: imx-snvs-poweroff: add power off driver for i.mx6Robin Gong
This driver register pm_power_off with snvs power off function. If your boards NOT use PMIC_ON_REQ to turn on/off external pmic, or use other pin to do, please disable the driver in dts, otherwise, your pm_power_off maybe overwrote by this driver. Signed-off-by: Robin Gong <b38343@freescale.com> Acked-By: Sebastian Reichel <sre@kernel.org> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-23ARM: imx: temporarily remove CONFIG_SOC_FSL from LS1021AArnd Bergmann
The newly introduced LS1021A SoC selects CONFIG_SOC_FSL, which is originally symbol used for the PowerPC based platforms and guards lots of code that does not build on ARM. This breaks allmodconfig, so let's remove it for now, until either all those drivers are fixed or they use a dependency on IMX instead. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-23ARM: imx: clk-vf610: get input clocks from assigned clocksStefan Agner
With the clock assignment device tree changes, the clocks get initialized properly but the search for those clocks fails with errors: [ 0.000000] i.MX clk 4: register failed with -17 [ 0.000000] i.MX clk 5: register failed with -17 This is because the module can't find those clocks anymore, and tries to initialize fixed clocks with the same name. Get the clock modules input clocks from the assigned clocks by default by using of_clk_get_by_name(). If this function returns not a valid clock, fall back to the old behaviour and search the input clock from the device tree's /clocks/$name node. Signed-off-by: Stefan Agner <stefan@agner.ch> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-23ARM: imx: Add Freescale LS1021A SMP supportJingchang Lu
Freescale LS1021A SoCs deploy two cortex-A7 processors, this adds bring-up support for the secondary core. Signed-off-by: Jingchang Lu <b35083@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-23ARM: imx: Add initial support for Freescale LS1021AJingchang Lu
The LS1021A SoC is a dual-core Cortex-A7 based processor, this adds the initial support for it. Signed-off-by: Jingchang Lu <b35083@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-23ARM: imx53: add cpufreq supportLucas Stach
Instanciate device for the generic cpufreq-dt driver. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
2014-11-23ARM: imx53: clk: add ARM clockLucas Stach
The ARM clock is a virtual clock feeding the ARM partition of the SoC. It controls multiple other clocks to ensure the right sequencing when cpufreq changes the CPU clock rate. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-11-23ARM: imx: add CPU clock typeLucas Stach
This implements a virtual clock used to abstract away all the steps needed in order to change the ARM clock, so we don't have to push all this clock handling into the cpufreq driver. While it will be used for i.MX53 at first it is generic enough to be used on i.MX6 later on. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-11-23ARM: imx5: add step clock, used when reprogramming PLL1Lucas Stach
This is the bypass clock used to feed the ARM partition while we reprogram PLL1 to another rate. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-11-23ARM: imx: add enet init for i.mx6sxFugang Duan
Add enet init for i.mx6sx: - Add phy ar8031 fixup - Set enet clock source from internal PLL Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-11-23ARM: imx6sx: add imx6sx iomux-gpr field defineFugang Duan
Add imx6sx iomux-gpr register field define in "imx6q-iomuxc-gpr.h" header file, which is not fully define all iomux-gpr registers and fields, only align with freescale internal tree related GPR macro define. Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-11-23ARM: vf610: Add ARM Global Timer clocksource optionStefan Agner
Add the ARM Global Timer as clocksource/scheduler clock option and use it as default scheduler clock. This leaves the PIT timer for other users e.g. the secondary Cortex-M4 core. Also, the Global Timer has double the precission (running at pheripheral clock compared to IPG clock) and a 64-bit incrementing counter register. We still keep the PIT timer as an secondary option in case the ARM Global Timer is not available. Signed-off-by: Stefan Agner <stefan@agner.ch> Acked-by: Bill Pringlemeir <bpringlemeir@nbsps.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-11-23ARM: imx: add anatop settings for LPDDR2 when enter DSM modeAnson Huang
For LPDDR2 platform, no need to enable weak2P5 in DSM mode, it can be pulled down to save power(~0.65mW). And per design team's recommendation, we should disconnect VDDHIGH and SNVS in DSM mode on i.MX6SL. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-11-23ARM: imx: replace cpu type check with ddr type checkAnson Huang
As the DDR/IO and MMDC setting are different on LPDDR2 and DDR3, we used cpu type to decide how to do these settings in suspend before which is NOT flexible, take i.MX6SL for example, although it has LPDDR2 on EVK board, but users can also use DDR3 on other boards, so it is better to read the DDR type from MMDC then decide how to do related settings. Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
2014-11-23Merge tag 'imx-fixes-3.18-2' into imx/socShawn Guo
The i.MX fixes for 3.18, 2nd round: - Fix a regression on Vybrid platform which is caused by commit dc4805c2e78b (ARM: imx: remove ENABLE and BYPASS bits from clk-pllv3 driver), and results in a missing configuration on PLL clocks. - Fix a regression with i.MX defconfig files where CONFIG_SPI option gets lost accidentally.
2014-11-22Merge branch 'timers-urgent-for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull timer fix from Thomas Gleixner: "A single bugfix for an init order problem in the sun4i subarch clockevents code" * 'timers-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: clockevent: sun4i: Fix race condition in the probe code
2014-11-22Merge branch 'for-linus' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs Pull vfs fixes from Al Viro: "Assorted fixes, most in overlayfs land" * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs: ovl: ovl_dir_fsync() cleanup ovl: update MAINTAINERS ovl: pass dentry into ovl_dir_read_merged() ovl: use lockless_dereference() for upperdentry ovl: allow filenames with comma ovl: fix race in private xattr checks ovl: fix remove/copy-up race ovl: rename filesystem type to "overlay" isofs: avoid unused function warning vfs: fix reference leak in d_prune_aliases()
2014-11-22i2c: omap: fix i207 errata handlingAlexander Kochetkov
commit 6d9939f651419a63e091105663821f9c7d3fec37 (i2c: omap: split out [XR]DR and [XR]RDY) changed the way how errata i207 (I2C: RDR Flag May Be Incorrectly Set) get handled. 6d9939f6514 code doesn't correspond to workaround provided by errata. According to errata ISR must filter out spurious RDR before data read not after. ISR must read RXSTAT to get number of bytes available to read. Because RDR could be set while there could no data in the receive FIFO. Restored pre 6d9939f6514 way of handling errata. Found by code review. Real impact haven't seen. Tested on Beagleboard XM C. Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com> Fixes: 6d9939f651419a63e09110 i2c: omap: split out [XR]DR and [XR]RDY Tested-by: Felipe Balbi <balbi@ti.com> Reviewed-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2014-11-22usb: xhci: rework root port wake bits if controller isn't allowed to wakeupLu Baolu
When system is being suspended, if host device is not allowed to do wakeup, xhci_suspend() needs to clear all root port wake on bits. Otherwise, some platforms may generate spurious wakeup, even if PCI PME# is disabled. The initial commit ff8cbf250b44 ("xhci: clear root port wake on bits"), which also got into stable, turned out to not work correctly and had to be reverted, and is now rewritten. Cc: stable <stable@vger.kernel.org> # v3.2+ Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> Suggested-by: Alan Stern <stern@rowland.harvard.edu> Acked-by: Alan Stern <stern@rowland.harvard.edu> [Mathias Nyman: reword commit message] Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-11-22USB: xhci: Reset a halted endpoint immediately when we encounter a stall.Mathias Nyman
If a device is halted and reuturns a STALL, then the halted endpoint needs to be cleared both on the host and device side. The host side halt is cleared by issueing a xhci reset endpoint command. The device side is cleared with a ClearFeature(ENDPOINT_HALT) request, which should be issued by the device driver if a URB reruen -EPIPE. Previously we cleared the host side halt after the device side was cleared. To make sure the host side halt is cleared in time we want to issue the reset endpoint command immedialtely when a STALL status is encountered. Otherwise we end up not following the specs and not returning -EPIPE several times in a row when trying to transfer data to a halted endpoint. Fixes: bcef3fd (USB: xhci: Handle errors that cause endpoint halts.) Cc: <stable@vger.kernel.org> # v2.6.33+ Tested-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-11-22Revert "xhci: clear root port wake on bits if controller isn't wake-up capable"Lu Baolu
commit ff8cbf250b44 ("xhci: clear root port wake on bits if controller isn't") can cause device detection error if runtime PM is enabled, and S3 wake is disabled. Revert it. https://bugzilla.kernel.org/show_bug.cgi?id=85701 This commit got into stable and should be reverted from there as well. Cc: stable <stable@vger.kernel.org> # v3.2+ Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com> Reported-by: Dmitry Nezhevenko <dion@inhex.net> [Mathias Nyman: reword commit message] Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-11-22USB: xhci: don't start a halted endpoint before its new dequeue is setMathias Nyman
A halted endpoint ring must first be reset, then move the ring dequeue pointer past the problematic TRB. If we start the ring too early after reset, but before moving the dequeue pointer we will end up executing the same problematic TRB again. As we always issue a set transfer dequeue command after a reset endpoint command we can skip starting endpoint rings at reset endpoint command completion. Without this fix we end up trying to handle the same faulty TD for contol endpoints. causing timeout, and failing testusb ctrl_out write tests. Fixes: e9df17e (USB: xhci: Correct assumptions about number of rings per endpoint.) Cc: <stable@vger.kernel.org> #v2.6.35 Tested-by: Felipe Balbi <balbi@ti.com> Signed-off-by: Mathias Nyman <mathias.nyman@linux.intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-11-22USB: uas: Add no-uas quirk for Hitachi usb-3 enclosures 4971:1012Hans de Goede
These disks have a broken uas implementation, the tag field of the status iu-s is not set properly, so we need to fall-back to usb-storage for these. Cc: stable@vger.kernel.org # 3.16 Signed-off-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2014-11-22Merge tag 'usb-serial-3.18-rc6' of ↵Greg Kroah-Hartman
git://git.kernel.org/pub/scm/linux/kernel/git/johan/usb-serial into usb-linus Johan writes: USB-serial fixes for v3.18-rc6 Three fixes for bugs related to TTY error reporting, which can to lead to data being dropped by the line discipline. Included is also some new device ids for ftdi_sio and cp210x. Signed-off-by: Johan Hovold <johan@kernel.org>
2014-11-22ARM: dts: rockchip: temporarily disable smp on rk3288Heiko Stuebner
Stock firmware on rk3288 does not initizalize the CNTVOFF registers of the architected timer correctly. This introduces issues with the newly added SMP support for rk3288, resulting in rcu stalls due to differing timer values per core. There exist preliminary and tested patches for u-boot for this problem, but there are a minority of boards using other bootloaders like coreboot. There also is currently a second solution for miss-initialized architected timers in the works: - clocksource: arch_timer: Fix code to use physical timers when requested - clocksource: arch_timer: Allow the device tree to specify uninitialized timer registers Therefore disable smp on rk3288 again till these are finalized, also allowing coreboot-based boards to boot again. Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-11-22ARM: dts: add missing clock to MFC device for exynos4Marek Szyprowski
sclk_mfc is required for MFC device since commit 0c2272170d78f826f6e97f99fb8a67fc17feef07 ("media: s5p-mfc: rename special clock to sclk_mfc"), so add it to exynos4 dts. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-11-22ARM: dts: Specify audio clock parents and rates for exynos4412-odroid-commonSylwester Nawrocki
This ensures the core and the audio subsystem clocks are configured properly, as expected by the sound machine driver. These bits are missing to obtain proper audio sample rates in kernel v3.17, where audio support for Odroid X2/U3 was first added. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-11-22ARM: dts: Add trackpad to exynos5250-springAndreas Faerber
The HP Chromebook 11 uses an Atmel maXTouch as trackpad. The keymap was found by trial-and-error. Signed-off-by: Andreas Faerber <afaerber@suse.de> Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-11-22ARM: dts: Add temperature sensor to exynos5250-springAndreas Faerber
Spotted in the Chrome OS 3.8 based device tree. Needs CONFIG_SENSORS_LM90. Signed-off-by: Andreas Faerber <afaerber@suse.de> Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-11-22ARM: dts: Add usb3503 pinctrl to exynos5250-springAndreas Faerber
Reported-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Andreas Faerber <afaerber@suse.de> Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-11-22ARM: dts: Add max77693-haptic node for exynos4412-trats2Jaewon Kim
This patch adds max77693-haptic node to support for haptic motor driver. Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-11-22ARM: dts: add pwm node for exynos4412-trats2Jaewon Kim
This patch add PWM(Pulse Width Modulation) node and handle to use pwm property. Signed-off-by: Jaewon Kim <jaewon02.kim@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-11-22ARM: dts: Specify default clocks for Exynos4 camera devicesSylwester Nawrocki
Specify the default mux and divider clocks in device tree to ensure the FIMC devices on Trats, Trats2, Universal_c210 and Odroid X2/U3 boards are clocked from recommended clock source and with maximum supported frequency. For Trats2 also the MIPI-CSIS and the camera sensor clocks are configured, the 'clock-frequency' property is deprecated in favour of 'assigned-clock-rates' property. Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-11-22ARM: EXYNOS: move restart code into pmu driverPankaj Dubey
Let's register restart handler from PMU driver for restart functionality. So that we can remove restart hooks from machine specific file, and thus moving ahead when PMU moved to driver folder, this functionality can be reused for ARM64 based Exynos SoC's. Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Acked-by: Guenter Roeck <linux@roeck-us.net> Tested-by: Vivek Gautam <gautam.vivek@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-11-22clk: exynos5440: move restart code into clock driverPankaj Dubey
Let's register restart handler for Exynos5440 from it's clock driver for restart functionality. So that we can cleanup restart hooks from machine specific file. CC: Sylwester Nawrocki <s.nawrocki@samsung.com> CC: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Acked-by: Guenter Roeck <linux@roeck-us.net> Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-11-22ARM: EXYNOS: add exynos3250 PMU supportBartlomiej Zolnierkiewicz
This patch prepares the PMU code for the future: - suspend/resume (S2R) support - cpuidle AFTR/W-AFTR modes support on Exynos3250. Cc: Vikas Sajjan <vikas.sajjan@samsung.com> Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com> Acked-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> [kgene.kim@samsung.com: fixed coding style] Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-11-22ARM: dts: Enable TMU support for exynos4412-trats2Lukasz Majewski
This patch enables support for TMU at Exynos4412 based Trats2 board. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Reviewed-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-11-22ARM: dts: Device tree node definition for TMU on exynos4x12Lukasz Majewski
The TMU device tree node definition for Exynos4x12 family of SoCs. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Reviewed-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Reviewed-by: Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-11-22arm: mvebu: add .dts file for Synology DS414Arnaud Ebalard
Synology DS414 is a 4-bay NAS powered by a Marvell Armada XP (mv78230 dual-core @1.33Ghz). It is very similar on many aspects to previous 4-bay synology models based on Marvell kirkwood SoC. Here is a short summary of the device: - 1GB RAM - Boot on SPI flash (64Mbit Micron N25Q064) - 2 GbE interfaces (Armada MAC connected to two Marvell 88E1512 PHY via RGMII) - 1 front USB 2.0 ports (directly handled by the Armada 370) - 2 rear USB 3.0 ports (handled by an EtronTech EJ168A XHCI controller on the PCIe bus) - 4 internal SATA ports handled by a Marvell 88SX7042 SATA-II controller on the PCIe bus) - Seiko S-35390A I2C RTC chip - UART0 providing serial console - UART1 used for poweroff (connected to a Microchip PIC16F883) Additional note: the front LEDs the and the two fans are not directly connected to the SoC and under its control. The former are presumably driven by the SATA controller, the latter by the PIC. [ jac: fixed up s/ge[01]_rgmii_pins/pmx_ge[01]_rgmii/ to match armada-xp.dtsi ] Acked-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Arnaud Ebalard <arno@natisbad.org> Link: https://lkml.kernel.org/r/5b678d6d1f2f42f4bf0d087878b9d8024d463ea7.1416613429.git.arno@natisbad.org Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22arm: mvebu: add .dts file for Synology DS213jArnaud Ebalard
Synology DS213j is a 2-bay NAS powered by a Marvell Armada 370 (88F6710 @1.2Ghz). It is very similar on many aspects to previous 2-bay synology models based on Marvell kirkwood SoC. Here is a short summary of the device: - 512MB RAM - boot on SPI flash (64Mbit Micron N25Q064) - 1 GbE interface (Armada MAC connected to a Marvell 88E1512 PHY via SGMII) - 2 rear USB 2.0 ports (directly handled by the Armada 370) - 2 internal SATA ports handled by the Armada 370: 2 GPIO for presence, 2 for powering them - two front amber LED (disk1, disk2) controlled by the SoC - Seiko S-35390A I2C RTC chip - UART0 providing serial console - UART1 used for poweroff (connected to a TI MSP430F2111) - Fan handled via 4 GPIO (3 for speed, 1 for alarm) Acked-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Arnaud Ebalard <arno@natisbad.org> Link: https://lkml.kernel.org/r/20f1a03897df1d825b62abdd525e588a8e39b3ec.1416613429.git.arno@natisbad.org Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22arm: mvebu: define and use common Armada XP SPI pinctrl settingArnaud Ebalard
This patch defines common Armada XP pinctrl settings in armada-xp.dtsi for the supported SPI interface (MPP36-39) and use it as default for Armada XP spi interface. That being done, it removes the now redundant definitions in armada-xp-axpwifiap.dts. Note: this patch has the potential to break out-of-tree users w/o specific pinctrl settings for their spi interfaces if the default above does not match their config (i.e. if they do not use CS0). Acked-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Arnaud Ebalard <arno@natisbad.org> Link: https://lkml.kernel.org/r/d404b7abd80ee5a0fd8e8d3586d33cd37740d589.1416613429.git.arno@natisbad.org Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22arm: mvebu: define and use common Armada XP UART2/3 pinctrl settingsArnaud Ebalard
This patch defines common Armada XP pinctrl settings for uart2 and uart3 interfaces (uart0 and uart1 rx/tx do not rely on MPP): uart2: MPP42-43 as default uart3: MPP44-45 as default Suggested-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Arnaud Ebalard <arno@natisbad.org> Link: https://lkml.kernel.org/r/fd51c080c7139a67ec01df8d797f1e88ce557796.1416613429.git.arno@natisbad.org Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22arm: mvebu: define and use common Armada 370 UART pinctrl settingsArnaud Ebalard
This patch defines common Armada 370 pinctrl settings for uart0 and uart1 interfaces: uart0: MPP0-1 as default uart1: MPP41-42 as default Note: this patch has the potential to break out-of-tree users w/o specific pinctrl settings for their uart interfaces if the default above does not match their config. Suggested-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Arnaud Ebalard <arno@natisbad.org> Link: https://lkml.kernel.org/r/31412e57955c98bc9cc47b70726b5072af945cc3.1416613429.git.arno@natisbad.org Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22arm: mvebu: define and use common Armada 370 SPI pinctrl settingsArnaud Ebalard
This patch defines common Armada 370 pinctrl settings for spi0 and spi1 interfaces: spi0: MPP33-36 as default, MPP32,63-65 as available alternate config spi1: MPP49-52 as default Currently, the Armada 370 DB .dts file has no explicit pinctrl info for the spi0 interface used to access the flash on the board. The patch fixes that by also adding explicit pinctrl info (MPP32,63-65) for this SPI interface. Note: this patch has the potential to break out-of-tree users w/o specific pinctrl settings for their spi interfaces if the default above does not match their config. Suggested-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Arnaud Ebalard <arno@natisbad.org> Link: https://lkml.kernel.org/r/1e812eb63b37718e273463e22e4d7512f8f0b624.1416613429.git.arno@natisbad.org Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22arm: mvebu: move Armada 370/XP pinctrl node definition armada-370-xp.dtsiArnaud Ebalard
What was done by Sebastian in 264a05e19bf5 ("ARM: mvebu: armada-xp: Add node alias to pinctrl and add base address") and 01c434225ee6 ("ARM: mvebu: armada-xp: Use pinctrl node alias") can also be done for Armada 370, i.e. - Rename Armada 370 pinctrl node to pin-ctrl with its address encoded - Add a node alias to access the pinctrl node easily. - use the newly available alias in existing Armada 370 .dts files We can even go a bit further by putting the pinctrl node definition in armada-370-xp.dtsi, with only its reg property defined. This allows us to then also use the newly defined node alias in armada-xp.dtsi, armada-370.dtsi. Suggested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Suggested-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Arnaud Ebalard <arno@natisbad.org> Link: https://lkml.kernel.org/r/b54eb45e5242728aace3ce8aef2eae4251f8dea3.1416613429.git.arno@natisbad.org Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22arm: mvebu: use recently introduced uart label for stdout-pathArnaud Ebalard
Now that labels for uartX are available in Marvell Armada .dtsi files, this patch replaces the "/soc/internal-regs/serial@12000" found in armada-xp-lenovo-ix4-300d.dts file for stdout-path property by the more concise &uart0. Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Suggested-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Arnaud Ebalard <arno@natisbad.org> Link: https://lkml.kernel.org/r/d1a883510e01f7f212a385e826dccbef903fae42.1416613429.git.arno@natisbad.org Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22arm: mvebu: add uartX labels for Armada SoC serial nodesArnaud Ebalard
This patch adds uartX labels for Armada SoC serial nodes. This is a preliminary work to be able to easily reference the serial lines in Device Tree files. One expected use is when providing stdout-path property for barebox. Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Arnaud Ebalard <arno@natisbad.org> Link: https://lkml.kernel.org/r/0683d1a823fe9b75849f3dafcf1cf6ee291cdca6.1416613429.git.arno@natisbad.org Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22arm: mvebu: fix vendor prefix typo in kirkwood-synology.dtsiArnaud Ebalard
As reported by Andrew, the vendor prefix for Seiko Instruments, Inc. S-35390A I2C RTC chip in kirkwood-synology.dtsi has a typo (ssi instead of sii). This patches fixes it. Note: i2c devices ignore the optional vendor prefix, which explains why it worked with the typo and also why there is no backward compatibility issues with the fix. Reported-by: Andrew Lunn <andrew@lunn.ch> Acked-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Arnaud Ebalard <arno@natisbad.org> Link: https://lkml.kernel.org/r/0444140a267d982c3e5f5f2b7b5f2dc41d010e2a.1416613429.git.arno@natisbad.org Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-22ARM: mvebu: fix ordering in Armada 370 .dtsiUwe Kleine-König
Commit a095b1c78a35 ("ARM: mvebu: sort DT nodes by address") missed placing the system-controller in the correct order. Fixes: a095b1c78a35 ("ARM: mvebu: sort DT nodes by address") Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Andrew Lunn <andrew@lunn.ch> Link: https://lkml.kernel.org/r/20141114204333.GS27002@pengutronix.de Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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