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2024-08-20clk: qcom: videocc-sm8550: Use HW_CTRL_TRIGGER flag for video GDSC'sVedang Nagar
The video driver will be using the newly introduced dev_pm_genpd_set_hwmode() API to switch the video GDSC to HW/SW control modes at runtime. Hence use HW_CTRL_TRIGGER flag instead of HW_CTRL for video GDSC's. Signed-off-by: Vedang Nagar <quic_vnagar@quicinc.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240812134752.28031-1-quic_vnagar@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15clk: qcom: dispcc-sm8250: use special function for Lucid 5LPE PLLDmitry Baryshkov
According to msm-5.10 the lucid 5lpe PLLs have require slightly different configuration that trion / lucid PLLs, it doesn't set PLL_UPDATE_BYPASS bit. Add corresponding function and use it for the display clock controller on Qualcomm SM8350 platform. Fixes: 205737fe3345 ("clk: qcom: add support for SM8350 DISPCC") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240804-sm8350-fixes-v1-2-1149dd8399fe@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15clk: qcom: dispcc-sm8250: use CLK_SET_RATE_PARENT for branch clocksDmitry Baryshkov
Add CLK_SET_RATE_PARENT for several branch clocks. Such clocks don't have a way to change the rate, so set the parent rate instead. Fixes: 80a18f4a8567 ("clk: qcom: Add display clock controller driver for SM8150 and SM8250") Cc: stable@vger.kernel.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240804-sm8350-fixes-v1-1-1149dd8399fe@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15clk: qcom: ipq5332: Use icc-clk for enabling NoC related clocksVaradarajan Narayanan
Use the icc-clk framework to enable few clocks to be able to create paths and use the peripherals connected on those NoCs. Remove CLK_IGNORE_UNUSED from gpll4_main as all consumers have been identified. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Link: https://lore.kernel.org/r/20240730054817.1915652-5-quic_varada@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15clk: qcom: ipq5332: Register gcc_qdss_tsctr_clk_srcVaradarajan Narayanan
gcc_qdss_tsctr_clk_src (enabled in the boot loaders and dependent on gpll4_main) was not registered as one of the ipq5332 clocks. Hence clk_disable_unused() disabled 'gpll4_main' assuming there were no consumers for 'gpll4_main' resulting in system freeze or reboots. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Fixes: 3d89d52970fd ("clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoC") Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Link: https://lore.kernel.org/r/20240730054817.1915652-4-quic_varada@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15dt-bindings: usb: qcom,dwc3: Update ipq5332 clock detailsVaradarajan Narayanan
Unlike MSM SoC, IPQ SoC doesn't use RPM to aggregate bandwidth requests and scale the NoC frequency. The NoCs are turned on and set to a specific frequency at boot time and that is used for the lifetime of the system. Hence interconnect was not considered previously. The same approach was used for PCIe and at that point the consensus was to move to interconnect. Hence implemented the ICC driver and updating the existing USB driver to use the ICC driver. USB uses icc-clk framework to enable the NoC interface clock. Hence the 'iface' clock is removed from the list of clocks. Update the clock-names list accordingly. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Link: https://lore.kernel.org/r/20240730054817.1915652-3-quic_varada@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15Merge branch '20240730054817.1915652-2-quic_varada@quicinc.com' into ↵Bjorn Andersson
clk-for-6.12 Merge IPQ5332 interconnect binding additions through topic branchs to allow making the constants available in DeviceTree branch as well.
2024-08-15dt-bindings: interconnect: Add Qualcomm IPQ5332 supportVaradarajan Narayanan
Add interconnect-cells to clock provider so that it can be used as icc provider. Add master/slave ids for Qualcomm IPQ5332 Network-On-Chip interfaces. This will be used by the gcc-ipq5332 driver for providing interconnect services using the icc-clk framework. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Link: https://lore.kernel.org/r/20240730054817.1915652-2-quic_varada@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15clk: qcom: gcc-msm8998: Add Q6 BIMC and LPASS core, ADSP SMMU clocksAngeloGioacchino Del Regno
Add the Q6 BIMC, LPASS core/adsp SMMU clocks to support audio related functionality on MSM8998 and APQ variants. As a final step to entirely enable the required clock tree for the lpass iommu and audio dsp, add the lpass core/adsp GDSCs. As a side note, it was found out that disabling the lpass core GDSC at any time would cause a system lockup (and reboot): disabling this GDSC will leave the lpass iommu completely unclocked, losing its state entirely - including the secure contexts that have been previously set-up from the bootloader/TrustZone. Losing this IOMMU configuration will trigger a hypervisor fault, which will reboot the system; the only workaround for this issue is to declare the lpass core gdsc as always-on. It should also not be forgotten that this is all about firmware and there may be a version of it that doesn't enable this GDSC at all before booting Linux, which is the reason why this specific declaration wasn't simply omitted. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Marc Gonzalez <mgonzalez@freebox.fr> Link: https://lore.kernel.org/r/20240814-lpass-v1-2-a5bb8f9dfa8b@freebox.fr Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15Merge branch '20240814-lpass-v1-1-a5bb8f9dfa8b@freebox.fr' into clk-for-6.12Bjorn Andersson
Merge updates to MSM8998 GCC binding include file through topic branch, to make available the newly added constants to both clock and DeviceTree branch.
2024-08-15dt-bindings: clock: gcc-msm8998: Add Q6 and LPASS clocks definitionsAngeloGioacchino Del Regno
Add definitions for the Q6 BIMC, LPASS core and adsp smmu clocks, required to enable audio functionality on MSM8998. Add the GDSC definitions for the LPASS_ADSP_GDSC and LPASS_CORE_GDSC as a final step to enable the required clock tree for the lpass iommu and for the audio dsp itself. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Signed-off-by: Marc Gonzalez <mgonzalez@freebox.fr> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20240814-lpass-v1-1-a5bb8f9dfa8b@freebox.fr Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15clk: qcom: Fix SM_CAMCC_8150 dependenciesSatya Priya Kakitapalli
SM_CAMCC_8150 depends on SM_GCC_8150, which inturn depends on ARM64. Hence add the dependency to avoid below kernel-bot warning. WARNING: unmet direct dependencies detected for SM_GCC_8150 Depends on [n]: COMMON_CLK [=y] && COMMON_CLK_QCOM [=y] && (ARM64 || COMPILE_TEST [=n]) Selected by [y]: - SM_CAMCC_8150 [=y] && COMMON_CLK [=y] && COMMON_CLK_QCOM [=y] Fixes: ea73b7aceff6 ("clk: qcom: Add camera clock controller driver for SM8150") Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202408020234.jg9wrvhd-lkp@intel.com/ Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Link: https://lore.kernel.org/r/20240813085846.941855-1-quic_skakitap@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15clk: qcom: gcc-sm8150: De-register gcc_cpuss_ahb_clk_srcSatya Priya Kakitapalli
The branch clocks of gcc_cpuss_ahb_clk_src are marked critical and hence these clocks vote on XO blocking the suspend. De-register these clocks and its source as there is no rate setting happening on them. Fixes: 4433594bbe5d ("clk: qcom: gcc: Add global clock controller driver for SC8180x") Cc: stable@vger.kernel.org Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Link: https://lore.kernel.org/r/20240812-gcc-sc8180x-fixes-v2-5-8b3eaa5fb856@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15clk: qcom: gcc-sc8180x: Fix the sdcc2 and sdcc4 clocks freq tableSatya Priya Kakitapalli
Update the frequency tables of gcc_sdcc2_apps_clk and gcc_sdcc4_apps_clk as per the latest frequency plan. Fixes: 4433594bbe5d ("clk: qcom: gcc: Add global clock controller driver for SC8180x") Cc: stable@vger.kernel.org Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Link: https://lore.kernel.org/r/20240812-gcc-sc8180x-fixes-v2-4-8b3eaa5fb856@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15clk: qcom: gcc-sc8180x: Add GPLL9 supportSatya Priya Kakitapalli
Add the missing GPLL9 pll and fix the gcc_parents_7 data to use the correct pll hw. Fixes: 4433594bbe5d ("clk: qcom: gcc: Add global clock controller driver for SC8180x") Cc: stable@vger.kernel.org Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Link: https://lore.kernel.org/r/20240812-gcc-sc8180x-fixes-v2-3-8b3eaa5fb856@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15dt-bindings: clock: qcom: Add GPLL9 support on gcc-sc8180xSatya Priya Kakitapalli
Add the missing GPLL9 which is required for the gcc sdcc2 clock. Fixes: 0fadcdfdcf57 ("dt-bindings: clock: Add SC8180x GCC binding") Cc: stable@vger.kernel.org Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Link: https://lore.kernel.org/r/20240812-gcc-sc8180x-fixes-v2-2-8b3eaa5fb856@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15clk: qcom: gcc-sc8180x: Register QUPv3 RCGs for DFS on sc8180xSatya Priya Kakitapalli
QUPv3 clocks support DFS on sc8180x platform but currently the code changes for it are missing from the driver, this results in not populating all the DFS supported frequencies and returns incorrect frequency when the clients request for them. Hence add the DFS registration for QUPv3 RCGs. Fixes: 4433594bbe5d ("clk: qcom: gcc: Add global clock controller driver for SC8180x") Cc: stable@vger.kernel.org Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Link: https://lore.kernel.org/r/20240812-gcc-sc8180x-fixes-v2-1-8b3eaa5fb856@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15clk: qcom: clk-rpmh: Fix overflow in BCM voteMike Tipton
Valid frequencies may result in BCM votes that exceed the max HW value. Set vote ceiling to BCM_TCS_CMD_VOTE_MASK to ensure the votes aren't truncated, which can result in lower frequencies than desired. Fixes: 04053f4d23a4 ("clk: qcom: clk-rpmh: Add IPA clock support") Cc: stable@vger.kernel.org Signed-off-by: Mike Tipton <quic_mdtipton@quicinc.com> Reviewed-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Imran Shaik <quic_imrashai@quicinc.com> Link: https://lore.kernel.org/r/20240809-clk-rpmh-bcm-vote-fix-v2-1-240c584b7ef9@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15dt-bindings: clock: qcom: Drop required-opps in required on SM8650 camccJagadeesh Kona
On SM8650, the minimum voltage corner supported on MMCX from cmd-db is sufficient for clock controllers to operate and there is no need to specify the required-opps. Hence remove the required-opps property from the list of required properties for SM8650 camcc bindings. This fixes: arch/arm64/boot/dts/qcom/sm8650-hdk.dtb: clock-controller@ade0000: 'required-opps' is a required property arch/arm64/boot/dts/qcom/sm8650-mtp.dtb: clock-controller@ade0000: 'required-opps' is a required property arch/arm64/boot/dts/qcom/sm8650-qrd.dtb: clock-controller@ade0000: 'required-opps' is a required property Fixes: 1ae3f0578e0e ("dt-bindings: clock: qcom: Add SM8650 camera clock controller") Reported-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Closes: https://lore.kernel.org/all/0f13ab6b-dff1-4b26-9707-704ae2e2b535@linaro.org/ Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202407070147.C9c3oTqS-lkp@intel.com/ Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Link: https://lore.kernel.org/r/20240801064448.29626-3-quic_jkona@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15dt-bindings: clock: qcom: Drop required-opps in required on sm8650 videoccJagadeesh Kona
On SM8650, the minimum voltage corner supported on MMCX from cmd-db is sufficient for clock controllers to operate and there is no need to specify the required-opps. Hence remove the required-opps property from the list of required properties for SM8650 videocc bindings. This fixes: arch/arm64/boot/dts/qcom/sm8650-hdk.dtb: clock-controller@aaf0000: 'required-opps' is a required property arch/arm64/boot/dts/qcom/sm8650-mtp.dtb: clock-controller@aaf0000: 'required-opps' is a required property arch/arm64/boot/dts/qcom/sm8650-qrd.dtb: clock-controller@aaf0000: 'required-opps' is a required property Fixes: a6a61b9701d1 ("dt-bindings: clock: qcom: Add SM8650 video clock controller") Reported-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Closes: https://lore.kernel.org/all/0f13ab6b-dff1-4b26-9707-704ae2e2b535@linaro.org/ Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202407070147.C9c3oTqS-lkp@intel.com/ Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Link: https://lore.kernel.org/r/20240801064448.29626-2-quic_jkona@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15dt-bindings: clock: qcom,qcs404-turingcc: convert to dtschemaRayyan Ansari
Convert the bindings for the Turing Clock Controller on QCS404 from the old text format to yaml. Signed-off-by: Rayyan Ansari <rayyan.ansari@linaro.org> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240716085622.12182-2-rayyan.ansari@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15dt-bindings: clock: Add x1e80100 LPASSCC reset controllerSrinivas Kandagatla
X1E80100 LPASS (Low Power Audio Subsystem) clock controller provides reset support when it is under the control of Q6DSP. Add x1e80100 compatible to the existing sc8280xp as these reset controllers have same reg layout and compatible. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240624-x1e-swr-reset-v2-2-8bc677fcfa64@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15dt-bindings: clock: Add x1e80100 LPASS AUDIOCC reset controllerSrinivas Kandagatla
X1E80100 LPASS (Low Power Audio Subsystem) Audio clock controller provides reset support when it is under the control of Q6DSP. Add x1e80100 compatible to the existing sc8280xp as these reset controllers have same reg layout and compatible. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240624-x1e-swr-reset-v2-1-8bc677fcfa64@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15clk: qcom: a53-pll: Add MSM8226 a7pll supportLuca Weiss
The MSM8226 has one PLL for its Cortex-A7 cores. The frequencies will be specified in devicetree. Signed-off-by: Luca Weiss <luca@lucaweiss.eu> Link: https://lore.kernel.org/r/20240619-msm8226-cpufreq-v1-4-85143f5291d1@lucaweiss.eu Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15dt-bindings: clock: qcom,a53pll: Add msm8226-a7pll compatibleLuca Weiss
Add the compatible for the A7PLL found in MSM8226 SoCs. Signed-off-by: Luca Weiss <luca@lucaweiss.eu> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240619-msm8226-cpufreq-v1-3-85143f5291d1@lucaweiss.eu Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15dt-bindings: clock: qcom,a53pll: Allow opp-table subnodeLuca Weiss
Allow placing an opp-table as a subnode that can be assigned using operating-points-v2 to specify the frequency table for the PLL. Signed-off-by: Luca Weiss <luca@lucaweiss.eu> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240619-msm8226-cpufreq-v1-2-85143f5291d1@lucaweiss.eu Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15clk: qcom: Add GPUCC driver support for SM4450Ajit Pandey
Add Graphics Clock Controller (GPUCC) support for SM4450 platform. Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240611133752.2192401-8-quic_ajipan@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15clk: qcom: Add CAMCC driver support for SM4450Ajit Pandey
Add Camera Clock Controller (CAMCC) support for SM4450 platform. Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240611133752.2192401-6-quic_ajipan@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-15clk: qcom: Add DISPCC driver support for SM4450Ajit Pandey
Add Display Clock Controller (DISPCC) support for SM4450 platform. Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240611133752.2192401-4-quic_ajipan@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-14clk: qcom: clk-alpha-pll: Fix CAL_L_VAL override for LUCID EVO PLLAjit Pandey
In LUCID EVO PLL CAL_L_VAL and L_VAL bitfields are part of single PLL_L_VAL register. Update for L_VAL bitfield values in PLL_L_VAL register using regmap_write() API in __alpha_pll_trion_set_rate callback will override LUCID EVO PLL initial configuration related to PLL_CAL_L_VAL bit fields in PLL_L_VAL register. Observed random PLL lock failures during PLL enable due to such override in PLL calibration value. Use regmap_update_bits() with L_VAL bitfield mask instead of regmap_write() API to update only PLL_L_VAL bitfields in __alpha_pll_trion_set_rate callback. Fixes: 260e36606a03 ("clk: qcom: clk-alpha-pll: add Lucid EVO PLL configuration interfaces") Cc: stable@vger.kernel.org Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Acked-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Link: https://lore.kernel.org/r/20240611133752.2192401-2-quic_ajipan@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-14Merge branch '20240611133752.2192401-1-quic_ajipan@quicinc.com' into ↵Bjorn Andersson
clk-for-6.12 Merge the SM4450 display, camera and GPU bindings through a topic branch, to make it possible to merge them into the DeviceTree source branch as well.
2024-08-14dt-bindings: clock: qcom: add GPUCC clocks on SM4450Ajit Pandey
Add device tree bindings for the graphics clock controller on Qualcomm SM4450 platform. Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20240611133752.2192401-7-quic_ajipan@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-14dt-bindings: clock: qcom: add CAMCC clocks on SM4450Ajit Pandey
Add device tree bindings for the camera clock controller on Qualcomm SM4450 platform. Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20240611133752.2192401-5-quic_ajipan@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-14dt-bindings: clock: qcom: add DISPCC clocks on SM4450Ajit Pandey
Add device tree bindings for the display clock controller on Qualcomm SM4450 platform. Signed-off-by: Ajit Pandey <quic_ajipan@quicinc.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240611133752.2192401-3-quic_ajipan@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-08-04clk: qcom: camcc-sm8150: Correct qcom_cc_really_probe() argumentBjorn Andersson
The SM8150 Camera Clock controller was merged using the old arguments for qcom_cc_really_probe(), correct this. Fixes: ea73b7aceff6 ("clk: qcom: Add camera clock controller driver for SM8150") Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-07-31clk: qcom: fold dispcc-sm8650 info dispcc-sm8550Dmitry Baryshkov
There is a very minor difference between display clock controller drivers for SM8550 and SM8650 platforms. Fold the second one into the first one to reduce kernel footprint. The bindings for these two hardware blocks are fully compatible. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Link: https://lore.kernel.org/r/20240717-dispcc-sm8550-fixes-v2-6-5c4a3128c40b@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-07-31clk: qcom: dispcc-sm8550: use rcg2_shared_ops for ESC RCGsDmitry Baryshkov
Follow the recommendations and park disp_cc_mdss_esc[01]_clk_src to the XO instead of disabling the clocks by using the clk_rcg2_shared_ops. Fixes: 90114ca11476 ("clk: qcom: add SM8550 DISPCC driver") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240717-dispcc-sm8550-fixes-v2-5-5c4a3128c40b@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-07-31clk: qcom: dispcc-sm8650: Update the GDSC flagsDmitry Baryshkov
Add missing POLL_CFG_GDSCR to the MDSS GDSC flags. Fixes: 90114ca11476 ("clk: qcom: add SM8550 DISPCC driver") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240717-dispcc-sm8550-fixes-v2-4-5c4a3128c40b@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-07-31clk: qcom: dispcc-sm8550: make struct clk_init_data constDmitry Baryshkov
The clk_init_data instances are not changed at runtime. Mark them as constant data. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240717-dispcc-sm8550-fixes-v2-3-5c4a3128c40b@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-07-31clk: qcom: dispcc-sm8550: use rcg2_ops for mdss_dptx1_aux_clk_srcDmitry Baryshkov
clk_dp_ops should only be used for DisplayPort pixel clocks. Use clk_rcg2_ops for disp_cc_mdss_dptx1_aux_clk_src. Fixes: 90114ca11476 ("clk: qcom: add SM8550 DISPCC driver") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240717-dispcc-sm8550-fixes-v2-2-5c4a3128c40b@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-07-31clk: qcom: dispcc-sm8550: fix several supposed typosDmitry Baryshkov
Fix seveal odd-looking places in SM8550's dispcc driver: - duplicate entries in disp_cc_parent_map_4 and disp_cc_parent_map_5 - using &disp_cc_mdss_dptx0_link_div_clk_src as a source for disp_cc_mdss_dptx1_usb_router_link_intf_clk The SM8650 driver has been used as a reference. Fixes: 90114ca11476 ("clk: qcom: add SM8550 DISPCC driver") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240717-dispcc-sm8550-fixes-v2-1-5c4a3128c40b@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-07-31Merge branch '20240717-dispcc-sm8550-fixes-v2-7-5c4a3128c40b@linaro.org' ↵Bjorn Andersson
into clk-for-6.12 Merge the SM8550/SM8650 display clock controller binding header file merge through a topic branch, to ensure the bindings are kept in sync between clock and DeviceTree source branches.
2024-07-31dt-bindings: clock: qcom,sm8650-dispcc: replace with symlinkDmitry Baryshkov
The display clock controller indices for SM8650 and SM8550 are completely equal. Replace the header file for qcom,sm8650-dispcc with the symlink to the qcom,sm8550-dispcc header file. Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20240717-dispcc-sm8550-fixes-v2-7-5c4a3128c40b@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-07-31clk: qcom: Add camera clock controller driver for SM8150Satya Priya Kakitapalli
Add support for the camera clock controller for camera clients to be able to request for camcc clocks on SM8150 platform. Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Link: https://lore.kernel.org/r/20240731062916.2680823-8-quic_skakitap@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-07-31clk: qcom: clk-alpha-pll: Add support for Regera PLL opsTaniya Das
Regera PLL ops are required to control the Regera PLL from clock controller drivers, hence add the Regera PLL ops and configure function. Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240731062916.2680823-6-quic_skakitap@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-07-31Merge branch '20240731062916.2680823-7-quic_skakitap@quicinc.com' into ↵Bjorn Andersson
clk-for-6.12 Merge SM8150 camera clock controller binding through topic branch, to allow this to be shared with DeviceTree source branches as well.
2024-07-31dt-bindings: clock: qcom: Add SM8150 camera clock controllerSatya Priya Kakitapalli
Add device tree bindings for the camera clock controller on Qualcomm SM8150 platform. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Link: https://lore.kernel.org/r/20240731062916.2680823-7-quic_skakitap@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-07-31clk: qcom: gcc-sc8180x: Add missing USB MP resetsBjorn Andersson
The USB multiport controller needs a few additional resets, add these to the driver. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Link: https://lore.kernel.org/r/20240730-sc8180x-usb-mp-v2-2-a7dc4265b553@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2024-07-31Merge branch '20240730-sc8180x-usb-mp-v2-1-a7dc4265b553@quicinc.com' into ↵Bjorn Andersson
clk-for-6.12 Merge the sc8180x multiport reset DeviceTree constants through a topic branch, to allow them also to be made available to DeviceTree source.
2024-07-31dt-bindings: clock: qcom: Add missing USB MP resetsBjorn Andersson
The USB multiport controller needs a few missing resets, describe them in the binding. Acked-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Bjorn Andersson <quic_bjorande@quicinc.com> Link: https://lore.kernel.org/r/20240730-sc8180x-usb-mp-v2-1-a7dc4265b553@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
generated by cgit (git 2.34.1) at 2025-09-11 09:14:19 +0000